CN112713200A - Optimized heterojunction solar cell and preparation method thereof - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims description 43
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 32
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- 229910052709 silver Inorganic materials 0.000 claims description 18
- 239000004332 silver Substances 0.000 claims description 18
- 238000004140 cleaning Methods 0.000 claims description 16
- 238000007639 printing Methods 0.000 claims description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 6
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- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses an optimized heterojunction solar cell, which comprises: the silicon substrate comprises a silicon layer substrate, a first intrinsic amorphous silicon layer, a first amorphous silicon film layer, a first conductive film layer and a first metal electrode, wherein the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the first conductive film layer and the first metal electrode are sequentially arranged on the front surface of the silicon layer substrate; the second intrinsic amorphous silicon layer, the second amorphous silicon film layer, the second conductive film layer and the second metal electrode are sequentially arranged on the back surface of the silicon layer substrate; wherein the thickness of the second conductive film layer is 10 +/-3 nm thicker than that of the first conductive film layer. The invention provides an optimized heterojunction solar cell and a preparation method thereof, the preparation process adopts different film thicknesses for conductive film layers on the front surface and the back surface on the basis of the original process, the solar cell prepared by the preparation process does not influence other performances, and simultaneously the square resistance of the film layer on the back surface of the cell is continuously reduced, so that a high filling factor is obtained, the efficiency is improved, and the solar cell has a far-reaching market development prospect.
Description
Technical Field
The invention belongs to the field of solar cell manufacturing, and relates to an optimized heterojunction solar cell and a preparation method thereof.
Background
The solar cell is a semiconductor device which can convert solar energy into electric energy, and photo-generated current is generated in the solar cell under the illumination condition, and the electric energy is output through an electrode. With the continuous progress of solar cell production technology, the development of high efficiency cells with more advantageous conversion efficiency is more and more emphasized. A silicon-based heterojunction solar cell (HJT cell: HIT is an abbreviation of heterjunctionwith Intrinsic Thin-layer, meaning an Intrinsic Thin-film heterojunction, and is also called HJT or SHJ since HIT has been applied by the japan tri-ocean company as a registered trademark) in which the surface is passivated with an amorphous silicon Intrinsic layer (a-Si: h (i)) is one of the important research directions. The heterojunction technology can combine ultrahigh battery efficiency and double-sided power generation performance; the heterojunction technology has relatively simple process steps, and after primary volume production, the efficiency is improved, and the cost is reduced; heterojunctions are an effective transition for future advances in photovoltaic technology to 25% efficiency levels.
The HJT battery adopts an N-type silicon wafer, alkaline texturing is carried out to form a pyramid textured surface, the amorphous silicon, the doped amorphous silicon and the transparent conductive thin film layer are deposited on two sides to form a passivation layer, a back field, an emitting electrode and a conductive layer, and finally metal is printed or electroplated to form an electrode. The photoelectric property of the transparent conductive film is closely related to the parameters of evaporation process conditions of the transparent conductive film, but most of mass production modes adopt the same process conditions for coating the film on the front surface and the back surface, so that the optimization of the photoelectric property of the TCO film is limited to a certain extent.
In order to solve the problems, the invention provides an optimized heterojunction solar cell, wherein the conductive film layers on the front side and the back side are different in film thickness on the basis of the original process, and the sheet resistance of the film layer on the back side of the cell is continuously reduced on the basis of not influencing other performances, so that a high filling factor is obtained, the efficiency is improved, and the optimized heterojunction solar cell has a far-reaching market development prospect.
Disclosure of Invention
In view of the above, the invention provides an optimized heterojunction solar cell and a preparation method thereof, the preparation process of the invention adopts different film thicknesses for the conductive film layers on the front surface and the back surface on the basis of the original process, and the solar cell prepared by the preparation process of the invention does not affect other performances, and simultaneously continuously reduces the square resistance of the film layer on the back surface of the cell, thereby obtaining high filling factor, bringing efficiency improvement and having a far-reaching market development prospect.
In order to achieve the purpose, the invention adopts the following technical scheme:
an optimized heterojunction solar cell, comprising: a silicon layer substrate, further comprising:
the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the first conductive film layer and the first metal electrode are sequentially arranged on the front surface of the silicon layer substrate;
the second intrinsic amorphous silicon layer, the second amorphous silicon film layer, the second conductive film layer and the second metal electrode are sequentially arranged on the back surface of the silicon layer substrate;
wherein the thickness of the second conductive film layer is 10 +/-3 nm thicker than that of the first conductive film layer.
The preparation process of the invention is based on the original process, and adopts different film thicknesses for the conductive film layers on the front surface and the back surface. After the thickness of the conductive film layer reaches 70nm, the resistivity is rapidly reduced, the transmittance can reach more than 80%, and the resistivity still slowly decreases with the continuous increase of the thickness of the conductive film layer, because the conductive film layer gradually becomes compact with the extension of the film coating time, the crystallization growth is facilitated, the grain boundary scattering is weakened by the increase of the crystallization degree of the conductive film layer and the increase of the grain size, the mobility of carriers is improved, and the resistivity of the film is gradually reduced. However, when a certain thickness is reached, the light transmittance of the film is inevitably affected because the increase in the thickness of the film gradually increases the absorption and scattering of visible light. Therefore, the preparation process of the invention continuously increases the thickness of the conductive film on the back by 10nm, and continuously optimizes the resistivity of the film on the premise of sacrificing a small amount of light transmittance of the back, thereby reducing the square resistance, improving the filling factor of the cell and improving the electrical property.
Preferably, the thickness is 10nm thick.
The filling factor of the battery piece can be improved by 0.2% by adopting the thickness; if the value is too low, effective electrical property improvement cannot be brought, and if the value is too high, the transmittance of the second conductive film layer is influenced, so that current loss is brought
Preferably, the silicon layer substrate is an N-type monocrystalline silicon wafer, the resistivity is 1.0-7.0 omega-cm, and the thickness is 50-200 um.
Preferably, the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer each have a thickness of 5-20 nm.
Preferably, the first amorphous silicon film layer is a P-type amorphous silicon film layer, and the second amorphous silicon film layer is an N-type amorphous silicon film layer; or the first amorphous silicon film layer is an N-type amorphous silicon film layer, and the second amorphous silicon film layer is a P-type amorphous silicon film layer;
the thickness of the P-type amorphous silicon film layer is 5-20nm, and the thickness of the N-type amorphous silicon film layer is 5-30 nm.
The above thickness can provide a higher open circuit voltage to the solar cell and reduce dark current.
Preferably, the first conductive film layer and the second conductive film layer are transparent conductive film layers, the transparent conductive film layers are made of any one of ITO, IWO or AZO, and the thickness of the first conductive film layer is 60-120 nm.
The material has excellent comprehensive photoelectric performance and wide application, and maintains higher transmittance and smaller resistivity.
Preferably, the first metal electrode and the second metal electrode are both silver electrodes, and the front surface and the back surface of each silver electrode comprise a main grid and a fine grid line;
wherein, the number of the main grid lines is 1-20, the width of the grid lines is 0.8-1.2mm, the number of the auxiliary grid lines is 80-200, and the width of the grid lines is 20-60 μm.
The preparation method of the optimized heterojunction solar cell comprises the following steps:
(1) texturing and cleaning the silicon layer substrate to form a double-sided textured structure;
(2) depositing a first intrinsic amorphous silicon layer, a first amorphous silicon film layer and a first conductive film layer on the front surface of the silicon layer substrate, and depositing a second intrinsic amorphous silicon layer, a second amorphous silicon film layer and a second conductive film layer on the back surface of the silicon layer substrate;
and respectively printing a first metal electrode and a second metal electrode on the front surface of the first conductive film layer and the back surface of the second conductive film layer, and curing to obtain the optimized heterojunction solar cell.
Preferably, the wool making in the step (1) adopts an alkali solution, and the alkali solution is a KOH or NaOH solution; and the cleaning adopts ammonia water hydrogen peroxide solution.
Preferably, in the step (2), the deposition methods of the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the second intrinsic amorphous silicon layer and the second amorphous silicon film layer are plasma enhanced chemical vapor deposition or catalytic chemical vapor deposition, and the deposition methods of the first conductive film layer and the second conductive film layer are reactive plasma deposition.
The method has low damage and adopts evaporation to have lower substrate surface bombardment.
Preferably, the printing in step (3) is screen printing; the curing temperature is 180-220 ℃, and the curing time is 10-30 min.
Compared with the prior art, the invention has the following beneficial effects: compared with the conventional process method, the electrical performance of the HJT cell prepared by the preparation process disclosed by the invention is improved by 0.1% in conversion efficiency, and mainly the filling factor is improved by 0.2%. The preparation process of the invention is based on the original process, different film thicknesses are adopted for the conductive film layers on the front surface and the back surface, the solar cell prepared by the preparation process of the invention does not influence other performances, and simultaneously the sheet resistance of the film layer on the back surface of the cell is continuously reduced, thereby obtaining high filling factor, obtaining lower sheet resistance on the back surface, improving the conversion efficiency of the cell and having far-reaching market development prospect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an optimized heterojunction solar cell according to the present invention.
Wherein in the figure:
1. a first metal electrode; 2. a first conductive film layer; 3. a first amorphous silicon layer; 4. a first intrinsic amorphous silicon layer; 5. a silicon layer substrate; 6. a second intrinsic amorphous silicon layer; 7. a second amorphous silicon layer; 8. a second conductive film layer; 9. a second metal electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an optimized heterojunction solar cell comprises: a substrate 5 of a silicon layer, and,
the first intrinsic amorphous silicon layer 4, the first amorphous silicon film layer 3, the first conductive film layer 2 and the first metal electrode 1 are sequentially arranged on the front surface of the silicon layer substrate 5;
the second intrinsic amorphous silicon layer 6, the second amorphous silicon film layer 7, the second conductive film layer 8 and the second metal electrode 9 are sequentially arranged on the back surface of the silicon layer substrate 5;
wherein the thickness of the second conductive film layer 8 is 10nm thicker than the thickness of the first conductive film layer 2.
Example 1
An optimized heterojunction solar cell comprises the following preparation process steps:
(1) carrying out texturing cleaning on the N-type monocrystalline silicon wafer to form a double-sided textured structure, wherein the size of the textured surface is controlled to be 3-7 um; the resistivity of the N-type monocrystalline silicon wafer is 3 omega-cm, the thickness of the N-type monocrystalline silicon wafer is 180 mu m, the opposite side width of the N-type monocrystalline silicon wafer is 166mm, wool making is carried out through 49% NaOH solution, and cleaning is carried out through 30% ammonia hydrogen peroxide solution;
(2) depositing a first intrinsic amorphous silicon layer, a first amorphous silicon film layer and a first conductive film layer on the front surface of the silicon layer substrate, and depositing a second intrinsic amorphous silicon layer, a second amorphous silicon film layer and a second conductive film layer on the back surface of the silicon layer substrate; the deposition method of the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the second intrinsic amorphous silicon layer and the second amorphous silicon film layer is a plasma enhanced chemical vapor deposition method, and the deposition method of the first conductive film layer and the second conductive film layer is a reactive plasma deposition method; the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 10 nm; the first amorphous silicon film layer is a P-type amorphous silicon film layer, and the thickness of the first amorphous silicon film layer is 10 nm; the second amorphous silicon film layer is an N-type amorphous silicon film layer, and the thickness of the second amorphous silicon film layer is 10 nm; the first conductive film layer and the second conductive film layer are made of ITO (indium tin oxide), the thickness of the first conductive film layer is 60nm, and the thickness of the second conductive film layer is controlled to be 70nm by changing the transmission speed of the substrate;
(3) respectively printing a first metal electrode and a second metal electrode on the front surface of the first conductive film layer and the back surface of the second conductive film layer, wherein the first metal electrode and the second metal electrode are silver electrodes, the front surface and the back surface of each silver electrode respectively comprise a main grid and a fine grid line, the number of the main grid lines is 0.8mm, the number of the auxiliary grid lines is 80, the width of the grid lines is 20 mu m, and then curing at the temperature of 180 plus materials and 220 ℃ for 10min to obtain the optimized heterojunction solar cell.
Example 2
An optimized heterojunction solar cell comprises the following preparation process steps:
(1) carrying out texturing cleaning on the N-type monocrystalline silicon wafer to form a double-sided textured structure, wherein the size of the textured surface is controlled to be 3-7 um; the resistivity of the N-type monocrystalline silicon wafer is 3 omega-cm, the thickness of the N-type monocrystalline silicon wafer is 180 mu m, the opposite side width of the N-type monocrystalline silicon wafer is 166mm, wool making is carried out through 49% NaOH solution, and cleaning is carried out through 30% ammonia hydrogen peroxide solution;
(2) depositing a first intrinsic amorphous silicon layer, a first amorphous silicon film layer and a first conductive film layer on the front surface of the silicon layer substrate, and depositing a second intrinsic amorphous silicon layer, a second amorphous silicon film layer and a second conductive film layer on the back surface of the silicon layer substrate; the deposition method of the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the second intrinsic amorphous silicon layer and the second amorphous silicon film layer is a plasma enhanced chemical vapor deposition method, and the deposition method of the first conductive film layer and the second conductive film layer is a reactive plasma deposition method; the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 10 nm; the first amorphous silicon film layer is a P-type amorphous silicon film layer, and the thickness of the first amorphous silicon film layer is 10 nm; the second amorphous silicon film layer is an N-type amorphous silicon film layer, and the thickness of the second amorphous silicon film layer is 10 nm; the first conductive film layer and the second conductive film layer are made of ITO (indium tin oxide), the thickness of the first conductive film layer is 110nm, and the thickness of the second conductive film layer is controlled to be 120nm by changing the transmission speed of the substrate;
(3) respectively printing a first metal electrode and a second metal electrode on the front surface of the first conductive film layer and the back surface of the second conductive film layer, wherein the first metal electrode and the second metal electrode are silver electrodes, the front surface and the back surface of each silver electrode respectively comprise a main grid and a fine grid line, the number of the main grid lines is 1, the width of the grid lines is 0.8mm, the number of the auxiliary grid lines is 80, and the width of the grid lines is 20 mu m, and then curing at the temperature of 220 ℃ of 180-.
Example 3
An optimized heterojunction solar cell comprises the following preparation process steps:
(1) carrying out texturing cleaning on the N-type monocrystalline silicon wafer to form a double-sided textured structure, wherein the size of the textured surface is controlled to be 3-7 um; the resistivity of the N-type monocrystalline silicon wafer is 3 omega-cm, the thickness of the N-type monocrystalline silicon wafer is 180 mu m, the opposite side width of the N-type monocrystalline silicon wafer is 166mm, wool making is carried out through 49% NaOH solution, and cleaning is carried out through 30% ammonia hydrogen peroxide solution;
(2) depositing a first intrinsic amorphous silicon layer, a first amorphous silicon film layer and a first conductive film layer on the front surface of the silicon layer substrate, and depositing a second intrinsic amorphous silicon layer, a second amorphous silicon film layer and a second conductive film layer on the back surface of the silicon layer substrate; the deposition method of the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the second intrinsic amorphous silicon layer and the second amorphous silicon film layer is a plasma enhanced chemical vapor deposition method, and the deposition method of the first conductive film layer and the second conductive film layer is a reactive plasma deposition method; the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 10 nm; the first amorphous silicon film layer is a P-type amorphous silicon film layer, and the thickness of the first amorphous silicon film layer is 10 nm; the second amorphous silicon film layer is an N-type amorphous silicon film layer, and the thickness of the second amorphous silicon film layer is 10 nm; the first conductive film layer and the second conductive film layer are made of IWO (IWO), the thickness of the first conductive film layer is 60nm, and the thickness of the second conductive film layer is controlled to be 70nm by changing the transmission speed of the substrate;
(3) respectively printing a first metal electrode and a second metal electrode on the front surface of the first conductive film layer and the back surface of the second conductive film layer, wherein the first metal electrode and the second metal electrode are silver electrodes, the front surface and the back surface of each silver electrode respectively comprise a main grid and a fine grid line, the number of the main grid lines is 1, the width of the grid lines is 0.8mm, the number of the auxiliary grid lines is 80, and the width of the grid lines is 20 mu m, and then curing at the temperature of 220 ℃ of 180-.
Example 4
An optimized heterojunction solar cell comprises the following preparation process steps:
(1) carrying out texturing cleaning on the N-type monocrystalline silicon wafer to form a double-sided textured structure, wherein the size of the textured surface is controlled to be 3-7 um; the resistivity of the N-type monocrystalline silicon wafer is 3 omega-cm, the thickness of the N-type monocrystalline silicon wafer is 180 mu m, the opposite side width of the N-type monocrystalline silicon wafer is 166mm, the N-type monocrystalline silicon wafer is subjected to texturing through 49% NaOH solution, and is cleaned through 30% ammonia hydrogen peroxide solution;
(2) depositing a first intrinsic amorphous silicon layer, a first amorphous silicon film layer and a first conductive film layer on the front surface of the silicon layer substrate, and depositing a second intrinsic amorphous silicon layer, a second amorphous silicon film layer and a second conductive film layer on the back surface of the silicon layer substrate; the deposition method of the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the second intrinsic amorphous silicon layer and the second amorphous silicon film layer is a plasma enhanced chemical vapor deposition method, and the deposition method of the first conductive film layer and the second conductive film layer is a reactive plasma deposition method; the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 10 nm; the first amorphous silicon film layer is a P-type amorphous silicon film layer, and the thickness of the first amorphous silicon film layer is 10 nm; the second amorphous silicon film layer is an N-type amorphous silicon film layer, and the thickness of the second amorphous silicon film layer is 10 nm; the first conductive film layer and the second conductive film layer are made of IWO (IWO), the thickness of the first conductive film layer is 110nm, and the thickness of the second conductive film layer is controlled to be 120nm by changing the transmission speed of the substrate;
(3) respectively printing a first metal electrode and a second metal electrode on the front surface of the first conductive film layer and the back surface of the second conductive film layer, wherein the first metal electrode and the second metal electrode are silver electrodes, the front surface and the back surface of each silver electrode respectively comprise a main grid and a fine grid line, the number of the main grid lines is 1, the width of the grid lines is 0.8mm, the number of the auxiliary grid lines is 80, and the width of the grid lines is 20 mu m, and then curing at the temperature of 220 ℃ of 180-.
Example 5
An optimized heterojunction solar cell comprises the following preparation process steps:
(1) carrying out texturing cleaning on the N-type monocrystalline silicon wafer to form a double-sided textured structure, wherein the size of the textured surface is controlled to be 3-7 um; the resistivity of the N-type monocrystalline silicon wafer is 1 omega cm, the thickness of the N-type monocrystalline silicon wafer is 50um, the opposite side width of the N-type monocrystalline silicon wafer is 166mm, the texturing is carried out through a 49% NaOH solution, and the cleaning is carried out through a 30% ammonia hydrogen peroxide solution;
(2) depositing a first intrinsic amorphous silicon layer, a first amorphous silicon film layer and a first conductive film layer on the front surface of the silicon layer substrate, and depositing a second intrinsic amorphous silicon layer, a second amorphous silicon film layer and a second conductive film layer on the back surface of the silicon layer substrate; the deposition method of the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the second intrinsic amorphous silicon layer and the second amorphous silicon film layer is a plasma enhanced chemical vapor deposition method, and the deposition method of the first conductive film layer and the second conductive film layer is a reactive plasma deposition method; the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 5 nm; the first amorphous silicon film layer is a P-type amorphous silicon film layer, and the thickness of the first amorphous silicon film layer is 5 nm; the second amorphous silicon film layer is an N-type amorphous silicon film layer, and the thickness of the second amorphous silicon film layer is 5 nm; the first conductive film layer and the second conductive film layer are made of IWO (IWO), the thickness of the first conductive film layer is 60nm, and the thickness of the second conductive film layer is controlled to be 67nm by changing the transmission speed of the substrate;
(3) respectively printing a first metal electrode and a second metal electrode on the front surface of the first conductive film layer and the back surface of the second conductive film layer, wherein the first metal electrode and the second metal electrode are silver electrodes, the front surface and the back surface of each silver electrode respectively comprise a main grid and a fine grid line, the number of the main grid lines is 1, the width of the grid lines is 0.8mm, the number of the auxiliary grid lines is 80, and the width of the grid lines is 20 mu m, and then curing at the temperature of 220 ℃ of 180-.
Example 6
An optimized heterojunction solar cell comprises the following preparation process steps:
(1) carrying out texturing cleaning on the N-type monocrystalline silicon wafer to form a double-sided textured structure, wherein the size of the textured surface is controlled to be 3-7 um; the resistivity of the N-type monocrystalline silicon wafer is 7 omega-cm, the thickness of the N-type monocrystalline silicon wafer is 200um, the opposite side width of the N-type monocrystalline silicon wafer is 166mm, the N-type monocrystalline silicon wafer is subjected to texturing through 49% NaOH solution, and is cleaned through 30% ammonia hydrogen peroxide solution;
(2) depositing a first intrinsic amorphous silicon layer, a first amorphous silicon film layer and a first conductive film layer on the front surface of the silicon layer substrate, and depositing a second intrinsic amorphous silicon layer, a second amorphous silicon film layer and a second conductive film layer on the back surface of the silicon layer substrate; the deposition method of the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the second intrinsic amorphous silicon layer and the second amorphous silicon film layer is a plasma enhanced chemical vapor deposition method, and the deposition method of the first conductive film layer and the second conductive film layer is a reactive plasma deposition method; the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 20 nm; the first amorphous silicon film layer is a P-type amorphous silicon film layer, and the thickness of the first amorphous silicon film layer is 20 nm; the second amorphous silicon film layer is an N-type amorphous silicon film layer, and the thickness of the second amorphous silicon film layer is 30 nm; the first conductive film layer and the second conductive film layer are made of IWO (IWO), the thickness of the first conductive film layer is 110nm, and the thickness of the second conductive film layer is controlled to be 123nm by changing the transmission speed of the substrate;
(3) respectively printing a first metal electrode and a second metal electrode on the front surface of the first conductive film layer and the back surface of the second conductive film layer, wherein the first metal electrode and the second metal electrode are silver electrodes, the front surface and the back surface of each silver electrode respectively comprise a main grid and a fine grid line, the number of the main grid lines is 20, the width of each grid line is 1.2mm, the number of the auxiliary grid lines is 200, the width of each grid line is 60 mu m, and then curing at the temperature of 220 ℃ of 180-.
Comparative example
The preparation process of the conventional heterojunction structure battery comprises the following steps:
(1) carrying out texturing cleaning on the N-type monocrystalline silicon wafer to form a double-sided textured structure, wherein the size of the textured surface is controlled to be 3-7 um; the resistivity of the N-type monocrystalline silicon wafer is 3 omega-cm, the thickness of the N-type monocrystalline silicon wafer is 180 mu m, the opposite side width of the N-type monocrystalline silicon wafer is 166mm, wool making is carried out through 49% NaOH solution, and cleaning is carried out through 30% ammonia hydrogen peroxide solution;
(2) depositing a first intrinsic amorphous silicon layer, a first amorphous silicon film layer and a first conductive film layer on the front surface of the silicon layer substrate, and depositing a second intrinsic amorphous silicon layer, a second amorphous silicon film layer and a second conductive film layer on the back surface of the silicon layer substrate; the deposition method of the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the second intrinsic amorphous silicon layer and the second amorphous silicon film layer is a plasma enhanced chemical vapor deposition method, and the deposition method of the first conductive film layer and the second conductive film layer is a reactive plasma deposition method; the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 10 nm; the first amorphous silicon film layer is a P-type amorphous silicon film layer, and the thickness of the first amorphous silicon film layer is 10 nm; the second amorphous silicon film layer is an N-type amorphous silicon film layer, and the thickness of the second amorphous silicon film layer is 10 nm; the first conductive film layer and the second conductive film layer are made of IWO (IWO), the thickness of the first conductive film layer is 110nm, and the thickness of the second conductive film layer is controlled to be 110nm by changing the transmission speed of the substrate;
(3) respectively printing a first metal electrode and a second metal electrode on the front surface of the first conductive film layer and the back surface of the second conductive film layer, wherein the first metal electrode and the second metal electrode are silver electrodes, the front surface and the back surface of each silver electrode respectively comprise a main grid and a fine grid line, the number of the main grid lines is 1, the width of the grid lines is 0.8mm, the number of the auxiliary grid lines is 80, and the width of the grid lines is 20 mu m, and then curing at the temperature of 220 ℃ of 180-.
The solar cells of examples 1 to 4 and comparative example were subjected to electrical property tests, and the results are shown in table 1.
TABLE 1 Battery test Performance results plot
| Grouping | Eta/％ | Voc/mV | Isc/mA | FF/％ |
| Comparative example | 0 | 0 | 0 | 0 |
| Example 1 | -0.2 | 0 | -202 | -0.08 |
| Example 2 | 0.1 | 0 | 10 | 0.2 |
| Example 3 | -0.2 | 0 | -180 | 0.03 |
| Example 4 | 0.1 | 0 | 20 | 0.2 |
From the above, different conductive thin film materials are adopted, and the Isc cannot be effectively improved under the condition of a lower film thickness; on the basis of the conventional film thickness, the back surface thin film layer is increased by 10nm, so that the FF is improved, and the conversion efficiency of the battery is improved by 0.2%.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An optimized heterojunction solar cell, comprising: a silicon layer substrate, further comprising:
the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the first conductive film layer and the first metal electrode are sequentially arranged on the front surface of the silicon layer substrate;
the second intrinsic amorphous silicon layer, the second amorphous silicon film layer, the second conductive film layer and the second metal electrode are sequentially arranged on the back surface of the silicon layer substrate;
wherein the thickness of the second conductive film layer is 10 +/-3 nm thicker than that of the first conductive film layer.
2. The optimized heterojunction solar cell of claim 1, wherein the silicon layer substrate is an N-type monocrystalline silicon wafer, has a resistivity of 1.0-7.0 Ω -cm and a thickness of 50-200 μm.
3. The optimized heterojunction solar cell of claim 1, wherein the thickness of each of said first intrinsic amorphous silicon layer and said second intrinsic amorphous silicon layer is 5-20 nm.
4. The optimized heterojunction solar cell of claim 1, wherein the first amorphous silicon film layer is a P-type amorphous silicon film layer, and the second amorphous silicon film layer is an N-type amorphous silicon film layer; or the first amorphous silicon film layer is an N-type amorphous silicon film layer, and the second amorphous silicon film layer is a P-type amorphous silicon film layer;
the thickness of the P-type amorphous silicon film layer is 5-20nm, and the thickness of the N-type amorphous silicon film layer is 5-30 nm.
5. The optimized heterojunction solar cell of claim 1, wherein the first conductive film layer and the second conductive film layer are transparent conductive film layers, the material of the transparent conductive film layers is any one of ITO, IWO or AZO, and the thickness of the first conductive film layer is 60-120 nm.
6. The optimized heterojunction solar cell of claim 1, wherein said first metal electrode and said second metal electrode are silver electrodes, and said silver electrodes comprise a main grid and a fine grid line on both front and back sides;
wherein, the number of the main grid lines is 1-20, the width of the grid lines is 0.8-1.2mm, the number of the auxiliary grid lines is 80-200, and the width of the grid lines is 20-60 μm.
7. The preparation method of the optimized heterojunction solar cell is characterized by comprising the following steps:
(1) texturing and cleaning the silicon layer substrate to form a double-sided textured structure;
(2) depositing a first intrinsic amorphous silicon layer, a first amorphous silicon film layer and a first conductive film layer on the front surface of the silicon layer substrate in sequence, and depositing a second intrinsic amorphous silicon layer, a second amorphous silicon film layer and a second conductive film layer on the back surface of the silicon layer substrate in sequence;
(3) and respectively printing a first metal electrode and a second metal electrode on the front surface of the first conductive film layer and the back surface of the second conductive film layer, and curing to obtain the optimized heterojunction solar cell.
8. The method for manufacturing an optimized heterojunction solar cell according to claim 7, wherein in the step (1), an alkaline solution is adopted for texturing, and the alkaline solution is a 49% KOH or NaOH solution; the cleaning adopts 30% ammonia water hydrogen peroxide solution with the mass ratio of 1: 1.
9. The method according to claim 7, wherein the first intrinsic amorphous silicon layer, the first amorphous silicon film layer, the second intrinsic amorphous silicon layer and the second amorphous silicon film layer are deposited by plasma enhanced chemical vapor deposition or catalytic chemical vapor deposition, and the first conductive film layer and the second conductive film layer are deposited by reactive plasma deposition.
10. The method for manufacturing an optimized heterojunction solar cell according to claim 7, wherein the printing in the step (3) is screen printing; the curing temperature is 180-220 ℃, and the curing time is 10-30 min.
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