CN111739986A - Method for improving short-circuit current of high-efficiency crystalline silicon heterojunction solar cell - Google Patents
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Abstract
The invention relates to a method for improving short-circuit current of a high-efficiency crystalline silicon heterojunction solar cell, which comprises the following steps: firstly, texturing and cleaning an N-type silicon substrate: after feeding, removing pollutants such as organic matters on the surface of the silicon wafer through pre-cleaning, removing a cutting damage layer through rough polishing, making wool after water washing, then washing with water and then alkali washing, then washing with water and acid washing twice, and finally drying and discharging; preparing a double-sided intrinsic amorphous silicon layer by slow-deposition PECVD; deposition power is 18~20 mW/cm, deposition rate is 2~ 3A/s. The cleaning and texturing process of the invention omits a correction step, and does not carry out round decoration on the pyramid textured surface, thereby reducing the surface reflectivity of the silicon wafer, and meanwhile, the PECVD deposition amorphous silicon thin film process adopts a slow deposition method, so that the short-circuit current is obviously improved, thereby improving the photoelectric conversion efficiency of the cell.
Description
Technical Field
The invention relates to the technical field of photovoltaic high-efficiency batteries, in particular to a method for improving short-circuit current of a high-efficiency crystalline silicon heterojunction solar battery.
Background
With the rapid development of photovoltaic technology, the conversion efficiency of crystalline silicon solar cells is improved year by year. In the current photovoltaic industry, the conversion efficiency of monocrystalline silicon solar cells has reached more than 20%, and the conversion efficiency of polycrystalline silicon solar cells has reached more than 18.5%. However, the silicon-based solar cells produced in large scale and having a conversion efficiency of 22.5% or more are only the Back Contact (IBC) of SunPower corporation in usa and the amorphous silicon/crystalline silicon Heterojunction (HJT) with Intrinsic Thin layer of panasonic corporation in japan. Compared with the IBC solar cell, the HJT cell has the advantages of less energy consumption, simple process flow, small temperature coefficient and the like, and the advantages are also the reasons that the HJT solar cell can be distinguished from a plurality of high-efficiency silicon-based solar cell schemes.
At present, China is popularizing distributed solar photovoltaic power generation, and due to the fact that roof resources are limited, and the distributed photovoltaic power generation requires a solar cell module with high conversion efficiency, the HJT solar cell has the advantages of high efficiency and double-sided power generation, and the distributed solar cell module shows wide application prospects in distributed photovoltaic power stations.
Among them, the silicon-based Heterojunction (HJT) solar cell has advantages of high conversion efficiency, high open-circuit voltage, low temperature coefficient, no induced degradation (LID), no induced degradation (PID), and low process temperature, which have become one of the hottest research directions.
In the preparation process of the HJT solar cell, texturing and cleaning are the first procedure, a clean crystalline silicon surface is provided for preparing a good amorphous silicon layer by PECVD, so the texturing and cleaning has great influence on the conversion efficiency of the HJT solar cell, wherein the water washing mode is crucial to the efficiency and stability of the cell. Referring to fig. 1, the mainstream process flow of the conventional cleaning and texturing of HJT is as follows, firstly, pre-cleaning is performed to remove pollutants such as organic matters on the surface of a silicon wafer, then, rough polishing is performed to remove a cutting damage layer, and then, texturing is performed to form a pyramid texturing surface, so that the purposes of reducing reflectivity and improving light trapping effect are achieved, and the whole process flow of the cleaning and texturing is completed through subsequent acid and alkali cleaning. One of the methods is a correction method, which is a method of chemically etching silicon by using HF/HNO3, HF/O3, KOH, or the like, so as to make sharp pyramids smooth by chemical etching, as shown in fig. 2, thereby being beneficial to more uniform amorphous silicon thin films deposited by CVD in the next process, but the problem is that the reflectivity is increased by more than 0.5%, which results in a decrease in short-circuit current of the HJT battery.
Disclosure of Invention
The invention aims to overcome the defects and provide a method for improving the short-circuit current of the high-efficiency crystalline silicon heterojunction solar cell, so that the conversion efficiency of the HJT cell is improved by improving the short-circuit current, and the performance of the heterojunction solar cell is improved.
The purpose of the invention is realized as follows:
a method for improving the short-circuit current of a high-efficiency crystalline silicon heterojunction solar cell comprises the following steps: (1) carrying out texturing and cleaning treatment on an N-type silicon substrate with the size of 156.75mm and the thickness of 180 um; (2) preparing a double-sided intrinsic amorphous silicon layer by PECVD; (3) selecting an N-type amorphous silicon film as a light receiving surface doping layer, and preparing the N-type amorphous silicon doping layer by using plasma enhanced chemical vapor deposition; (4) preparing a p-type amorphous silicon doped layer by using plasma chemical vapor deposition; (5) depositing TCO conductive film by using PVD and RPD methods; (6) forming front and back Ag electrodes by screen printing; (7) curing to form good ohmic contact between the silver grid line and the TCO conductive film; (8) testing the electrical property of the battery; after feeding, removing pollutants such as organic matters on the surface of the silicon wafer through pre-cleaning, removing a cutting damage layer through rough polishing, making wool after water washing, washing with water and then alkali, washing with water and acid, drying and discharging.
Further, the deposition power of the double-sided intrinsic amorphous silicon layer prepared by PECVD is 18-20 mW/cm, and the deposition rate is 2-3A/s.
Furthermore, the thickness of the amorphous silicon intrinsic layer (2) is 5-10 nm.
Furthermore, the thickness of the n-type amorphous silicon doped layer is 4-8 nm, and the thickness of the p-type amorphous silicon doped layer is 7-15 nm.
Furthermore, the thickness of the TCO conductive film is 70-110 nm.
Compared with the prior art, the invention has the beneficial effects that:
according to the cleaning and texturing method, a correction step is omitted, and round modification is not performed on the pyramid texturing surface, so that the surface reflectivity of a silicon wafer is reduced, meanwhile, a slow deposition method is adopted in a PECVD (plasma enhanced chemical vapor deposition) amorphous silicon thin film process, the deposition power of an amorphous silicon intrinsic layer is changed from 25-28mW/cm to 18-20 mW/cm, and the deposition rate is changed from 5-7A/s to 2-3A/s; under the condition that the open circuit voltage of the HJT solar cell prepared by the method is kept unchanged, the short circuit current is obviously improved, so that the photoelectric conversion efficiency of the cell is improved.
Drawings
Fig. 1 is a schematic structural diagram of a conventional heterojunction solar cell.
FIG. 2 is a schematic view of a silicon wafer textured structure after modification in the prior art.
FIG. 3 is a flow chart of the cleaning and texturing process of the present invention.
Detailed Description
Example 1:
referring to fig. 3, the method for improving the short-circuit current of the high-efficiency crystalline silicon heterojunction solar cell according to the invention comprises the following steps:
(1) carrying out texturing and cleaning treatment on an N-type silicon substrate with the size of 156.75mm and the thickness of 180 um;
after feeding, removing pollutants such as organic matters on the surface of the silicon wafer through pre-cleaning, removing a cutting damage layer through rough polishing, making wool after water washing, then washing with water and then alkali washing, then washing with water and acid washing twice, and finally drying and discharging;
(2) preparing a double-sided intrinsic amorphous silicon layer by PECVD, wherein the thickness of the double-sided intrinsic amorphous silicon layer is 6 nm; deposition power is 18 mW/cm, deposition rate is 2A/s;
(3) selecting an N-type amorphous silicon film as a light receiving surface doping layer, and preparing the N-type amorphous silicon doping layer by using plasma enhanced chemical vapor deposition, wherein the thickness is 6 nm;
(4) preparing a p-type amorphous silicon doped layer by using plasma chemical vapor deposition, wherein the total thickness is 10 nm;
(5) depositing a TCO conductive film by using a PVD (physical vapor deposition) and RPD (reverse phase deposition) method, wherein the thickness of the TCO conductive film is 100 nm;
(6) forming front and back Ag electrodes by screen printing;
(7) curing to form good ohmic contact between the silver grid line and the TCO conductive film;
(8) a test of the electrical performance of the cells was conducted.
Example 2:
referring to fig. 3, the method for improving the short-circuit current of the high-efficiency crystalline silicon heterojunction solar cell according to the invention comprises the following steps:
(1) carrying out texturing and cleaning treatment on an N-type silicon substrate with the size of 156.75mm and the thickness of 180 um;
after feeding, removing pollutants such as organic matters on the surface of the silicon wafer through pre-cleaning, removing a cutting damage layer through rough polishing, making wool after water washing, then washing with water and then alkali washing, then washing with water and acid washing twice, and finally drying and discharging;
(2) preparing a double-sided intrinsic amorphous silicon layer by PECVD, wherein the thickness of the double-sided intrinsic amorphous silicon layer is 6 nm; deposition power is 19 mW/cm, deposition rate is 2.5A/s;
(3) selecting an N-type amorphous silicon film as a light receiving surface doping layer, and preparing the N-type amorphous silicon doping layer by using plasma enhanced chemical vapor deposition, wherein the thickness is 6 nm;
(4) preparing a p-type amorphous silicon doped layer by using plasma chemical vapor deposition, wherein the total thickness is 10 nm;
(5) depositing a TCO conductive film by using a PVD (physical vapor deposition) and RPD (reverse phase deposition) method, wherein the thickness of the TCO conductive film is 100 nm;
(6) forming front and back Ag electrodes by screen printing;
(7) curing to form good ohmic contact between the silver grid line and the TCO conductive film;
(8) a test of the electrical performance of the cells was conducted.
Example 3:
referring to fig. 3, the method for improving the short-circuit current of the high-efficiency crystalline silicon heterojunction solar cell according to the invention comprises the following steps:
(1) carrying out texturing and cleaning treatment on an N-type silicon substrate with the size of 156.75mm and the thickness of 180 um;
after feeding, removing pollutants such as organic matters on the surface of the silicon wafer through pre-cleaning, removing a cutting damage layer through rough polishing, making wool after water washing, then washing with water and then alkali washing, then washing with water and acid washing twice, and finally drying and discharging;
(2) preparing a double-sided intrinsic amorphous silicon layer by PECVD, wherein the thickness of the double-sided intrinsic amorphous silicon layer is 6 nm; deposition power is 20mW/cm, deposition rate is 3A/s;
(3) selecting an N-type amorphous silicon film as a light receiving surface doping layer, and preparing the N-type amorphous silicon doping layer by using plasma enhanced chemical vapor deposition, wherein the thickness is 6 nm;
(4) preparing a p-type amorphous silicon doped layer by using plasma chemical vapor deposition, wherein the total thickness is 10 nm;
(5) depositing a TCO conductive film by using a PVD (physical vapor deposition) and RPD (reverse phase deposition) method, wherein the thickness of the TCO conductive film is 100 nm;
(6) forming front and back Ag electrodes by screen printing;
(7) curing to form good ohmic contact between the silver grid line and the TCO conductive film;
(8) a test of the electrical performance of the cells was conducted.
And (3) reflectivity testing: the silicon wafers after cleaning and texturing of examples 1 to 3 were tested for surface reflectance, and the results are as follows:
| condition | Reflectivity after cleaning and texturing |
| Experimental 1 | 10.60% |
| Experimental 2 | 10.80% |
| Experimental 3 | 10.70% |
Comparative example 1:
(1) carrying out texturing and cleaning treatment on an N-type monocrystalline silicon wafer (180 um) with the size of 156.75 mm;
firstly, removing pollutants such as organic matters on the surface of a silicon wafer through pre-cleaning, then removing a cutting damage layer through rough polishing, then making a texture to form a pyramid texture surface, then washing with water and then washing with alkali, then correcting, and then drying and discharging after subsequent acid washing;
and (3) reflectivity testing: the reflectivity tester is used for testing the reflectivity of the surface of the silicon wafer before and after correction, and the result is as follows:
| condition | Before correction | After correction |
| Comparative example 1 | 10.5% | 11.1% |
(2) Preparing intrinsic amorphous silicon layers on the front surface and the back surface by PECVD, wherein the intrinsic amorphous silicon on the front surface and the back surface are deposited by one step at a wavelength of 7 nm; the deposition power is 25-28mW/cm, and the deposition rate is 5-7A/s;
(3) selecting an N-type amorphous silicon film as a light receiving surface doping layer, and preparing an N-type amorphous silicon layer by using plasma enhanced chemical vapor deposition, wherein the thickness is 6 nm;
(4) preparing a p-type amorphous silicon layer by using plasma chemical vapor deposition, wherein the thickness of the p-type amorphous silicon layer is 10 nm;
(5) depositing a TCO conductive film with the thickness of 100nm by using an RPD and PVD method;
(6) forming front and back silver metal electrodes by screen printing;
(7) curing to form good ohmic contact between the silver grid line and the TCO;
(8) a test of the electrical performance of the cells was conducted.
Comparing the data of the examples of the present invention with the prior art of comparative example 1, the electrical performance of the present invention with that of the prior art is shown in the following table, and the electrical performance is compared with that of the prior art, and it can be seen from the table that the absolute value of the conversion efficiency Eta of the Experimental is higher than 0.1% of Baseline, which is mainly reflected in the gain of the current density Jsc.
| Voc（mV） | Isc（mA/cm2） | FF（%） | Eta（%） | |
| Comparative example 1 | 741.1 | 38.75 | 80.05 | 22.99 |
| Example 1 | 741.9 | 38.82 | 80.1 | 23.07 |
| Example 2 | 741.3 | 38.88 | 80.1 | 23.09 |
| Example 3 | 741.5 | 38.90 | 80.09 | 23.10 |
The open-circuit voltage is basically kept unchanged, although the pyramid texture is not modified and smooth, a uniform amorphous silicon film can still be obtained through PECVD process adjustment and a slow deposition mode is adopted, the surface of a silicon wafer can still be well passivated, however, the reflectivity is reduced after the texture is cleaned, the light absorption of the silicon wafer is increased, the short-circuit current is improved, the current density Jsc is increased, and finally the conversion efficiency of the battery is improved.
The above is only a specific application example of the present invention, and the protection scope of the present invention is not limited in any way. All the technical solutions formed by equivalent transformation or equivalent replacement fall within the protection scope of the present invention.
Claims (5)
1. A method for improving the short-circuit current of a high-efficiency crystalline silicon heterojunction solar cell comprises the following steps: (1) carrying out texturing and cleaning treatment on an N-type silicon substrate with the size of 156.75mm and the thickness of 180 um; (2) preparing a double-sided intrinsic amorphous silicon layer by PECVD; (3) selecting an N-type amorphous silicon film as a light receiving surface doping layer, and preparing the N-type amorphous silicon doping layer by using plasma enhanced chemical vapor deposition; (4) preparing a p-type amorphous silicon doped layer by using plasma chemical vapor deposition; (5) depositing TCO conductive film by using PVD and RPD methods; (6) forming front and back Ag electrodes by screen printing; (7) curing to form good ohmic contact between the silver grid line and the TCO conductive film; (8) testing the electrical property of the battery; the method is characterized in that: the process of the texturing cleaning treatment comprises the following steps: after feeding, removing pollutants such as organic matters on the surface of the silicon wafer through pre-cleaning, removing a cutting damage layer through rough polishing, making wool after water washing, washing with water and then alkali, washing with water and acid, drying and discharging.
2. The method for improving the short-circuit current of the high-efficiency crystalline silicon heterojunction solar cell as claimed in claim 1, wherein the method comprises the following steps: the deposition power for preparing the double-sided intrinsic amorphous silicon layer by PECVD is 18-20 mW/cm, and the deposition rate is 2-3A/s.
3. The method for improving the short-circuit current of the high-efficiency crystalline silicon heterojunction solar cell as claimed in claim 1, wherein the method comprises the following steps: the thickness of the amorphous silicon intrinsic layer (2) is 5-10 nm.
4. The method for improving the short-circuit current of the high-efficiency crystalline silicon heterojunction solar cell as claimed in claim 1, wherein the method comprises the following steps: the thickness of the n-type amorphous silicon doped layer is 4-8 nm, and the thickness of the p-type amorphous silicon doped layer is 7-15 nm.
5. The method for improving the short-circuit current of the high-efficiency crystalline silicon heterojunction solar cell as claimed in claim 1, wherein the method comprises the following steps: the thickness of the TCO conductive film is 70-110 nm.
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| CN114335247A (en) * | 2021-12-29 | 2022-04-12 | 湖州爱康光电科技有限公司 | Double-texturing cleaning process and device for heterojunction battery |
| WO2022142007A1 (en) * | 2020-12-28 | 2022-07-07 | 苏州腾晖光伏技术有限公司 | Efficient heterojunction battery structure and preparation method therefor |
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| US20090020154A1 (en) * | 2007-01-18 | 2009-01-22 | Shuran Sheng | Multi-junction solar cells and methods and apparatuses for forming the same |
| CN103806108A (en) * | 2012-11-08 | 2014-05-21 | 上海神舟新能源发展有限公司 | Improved crystalline silicon battery slice cleaning process |
| CN103606589A (en) * | 2013-07-25 | 2014-02-26 | 昆明铂阳远宏能源科技有限公司 | Amorphous silicon film solar cell and manufacturing method thereof |
| CN108336170A (en) * | 2017-01-17 | 2018-07-27 | Lg电子株式会社 | The method for manufacturing solar cell |
| CN109461780A (en) * | 2018-12-13 | 2019-03-12 | 江苏爱康能源研究院有限公司 | Efficient silicon/crystalline silicon heterojunction solar battery electrode structure of high matching degree and preparation method thereof |
| CN111063612A (en) * | 2019-12-09 | 2020-04-24 | 通威太阳能(眉山)有限公司 | Coating process for improving intrinsic amorphous silicon passivation effect, passivation structure, heterojunction solar cell and preparation process |
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| WO2022142007A1 (en) * | 2020-12-28 | 2022-07-07 | 苏州腾晖光伏技术有限公司 | Efficient heterojunction battery structure and preparation method therefor |
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