CN112702055A - Chip peripheral anti-fuse pre-trimming circuit and trimming method thereof - Google Patents
Chip peripheral anti-fuse pre-trimming circuit and trimming method thereof Download PDFInfo
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- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09403—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors
- H03K19/0941—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors of complementary type
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Abstract
The invention relates to a chip peripheral anti-fuse pre-trimming circuit and a trimming method thereof. The trimming method comprises the following steps: calculating a rough pre-trimming value by using a formula according to an electrical parameter initial value and an electrical parameter target value tested before sintering, and converting to obtain a rough pre-trimming anti-fuse combination; carrying out rough virtual fusing on the antifuse according to the rough pre-trimming antifuse combination and testing a rough electrical parameter value; calculating the deviation of the pre-trimming value by using the trimming step length of the designed electrical parameter, the rough electrical parameter value and the electrical parameter target value; determining a precise pre-trimming range according to the pre-trimming value deviation, virtually fusing the antifuses according to each antifuse trimming combination in the precise pre-trimming range, testing a corresponding electrical parameter pre-trimming value, and obtaining a precise antifuse combination when the tested electrical parameter value is closest to a target value under a certain antifuse combination; and (4) burning the anti-fuse according to the precise anti-fuse combination, and testing and verifying whether the error between the final value and the target value of the electrical parameter meets the requirement.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a chip peripheral antifuse pre-trimming circuit for realizing antifuses by using a CMOS (complementary metal oxide semiconductor) low-voltage process and a trimming method thereof.
Background
An antifuse generally refers to a device or circuit that irreversibly changes from an open state to a short state by burning with a voltage or current, and is generally used to adjust certain electrical parameters in the circuit, such as: reference voltage, frequency, etc.
The antifuse trimming circuit is a circuit for burning and detecting the antifuse, and the antifuse trimming circuit is required to ensure that other devices and circuits in an integrated circuit are not damaged during burning and detect the open and short circuit states of the antifuse besides ensuring reliable and stable burning of the antifuse.
Fig. 1 shows one of the conventional circuits of the trimming circuit for the antifuse, and fig. 1 shows only one of the antifuses and its trimming circuit, i.e. the ith (i =1,2,3, …, n) bit, and in fig. 1, the antifuse AFi is implemented by a PMOS fet; INVi1 and INVi2 are inverters; NMi 1-NMi 3 are NMOS field effect transistors; the signal FSi is an antifuse bit selection signal, and in a test state, when certain antifuse bit needs to be burned, the corresponding FSi is set to be low level, so that NMi1 is turned on, NMi2 is turned off, and FSi of other bits are set to be high level; in the working state, FSi signals of all bits are set to be high level; voltage VB provides NMi3 with a bias voltage such that when the drain voltage of NMi3 is high enough, NMi3 flows a constant current. Thus, in the test state, NMi1 is conducted, the gate of AFi is connected to the ground, a proper high voltage is applied to Ti and current is limited, the high voltage is larger than the gate oxide breakdown voltage of PMOS antifuse AFi, the gate oxide of antifuse AFi is broken down, and the antifuse AFi can be safely short-circuited; in the working state, Ti is set to a normal working voltage, NMi1 of all bits is turned off, NMi2 is turned on, if an antifuse AFi of a bit is opened, the drain of the corresponding NMi3 is pulled down to a low level, TSi (i =1,2,3, …, n) outputs a high level, if the antifuse AFi of a bit is short-circuited, the drain voltage of the corresponding NMi2 is equal to the voltage on Ti, the drain voltage of NMi3 is increased, TSi (i =1,2,3, …, n) outputs a low level, and then TSi (i =1,2,3, …, n) signals of all antifuse trimming circuits are subjected to logic operation to control and adjust the reference voltage parameters and the like.
In the circuit shown in fig. 1, if the PMOS antifuse AFi, the NMOS fets NMi 1-NMi 3, and the inverters INVi1 and INVi2 are all implemented by conventional devices in the standard CMOS low-voltage process, the gate-oxide breakdown voltage of the PMOS antifuse AFi is much larger than the drain-source withstand voltage of devices NMi1, NMi2, and the like, and when the antifuse AFi is short-circuited by fuse, devices NMi1, NMi2, and the like may be damaged. The circuit in fig. 1 needs to reliably and stably burn the antifuse, and also needs to ensure that other devices and circuits in the integrated circuit are not damaged during burning, and only has two solutions: in the first scheme, the antifuse AFi adopts a specially designed structure and circuit or is additionally provided with an extra layer, so that the burning voltage of the antifuse AFi is lower than the withstand voltage of a conventional device, but the scheme can increase the cost of an integrated circuit, reduce the process compatibility of the integrated circuit and require IP authorization in some cases; the second scheme is realized by adopting a high-voltage process, the antifuse AFi, the NMOS fet NMi3, the inverters INVi1 and INVi2 all adopt low-voltage devices, the NMOS fets NMi1 and NMi2 all adopt high-voltage devices, and the withstand voltage of the high-voltage devices is far greater than the burning voltage of the antifuse AFi. However, this approach also increases the cost of the integrated circuit and reduces the process compatibility of the integrated circuit.
The existing various anti-fuse trimming circuits have the defects of poor process compatibility or high circuit cost.
The traditional anti-fuse trimming method has two types:
the first method includes deducing the theoretical trimming formula of the electrical parameter, testing the initial value of the electrical parameter before burning, calculating the trimming value with the theoretical formula according to the initial value and the target value, rounding or rounding the trimming value and converting (for example, converting into binary number) to find the combination of the antifuses needing burning and trimming, burning each antifuse bit by bit, and testing and verifying whether the electrical parameter reaches the target value after burning. The defect of the trimming method is that the product quality of the integrated circuit is reduced due to the influence of random factors such as device matching precision, offset voltage of an operational amplifier or a comparator, test error and the like, and larger errors exist in the calculation value and the test value of a theoretical formula, so that the test production yield is reduced, and the accuracy of electrical parameters is not high.
The second method is to add a pre-trimming circuit to traverse and pre-trim the electrical parameter to be trimmed, the pre-trimming circuit can be placed inside the chip or outside the chip during production test, the electrical parameter to be trimmed changes monotonically between the minimum value and the maximum value through program control, and all possible electrical parameter values are output, the electrical parameter values correspond to various possible anti-fuse combinations one by one, when the tested electrical parameter value is closest to the target value under a certain anti-fuse combination, the anti-fuse combination is recorded, then each anti-fuse is burned according to the anti-fuse combination, and after the burning is finished, the testing is carried out to verify whether the electrical parameter reaches the target value. The drawback of this trimming method is that during the pre-trimming process, all possible antifuse combinations are tested once, when the antifuse bits are more, the production test time is long, the efficiency is low, if the antifuse bits have n bits, test 2 is needednValues, for example, when the antifuse bit has 10 bits, 1024 values need to be tested.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects in the prior art and provide a chip peripheral antifuse pre-trimming circuit and a trimming method thereof, wherein the virtual burning of antifuses and the pre-trimming of electrical parameters are realized by controlling a chip peripheral switch by utilizing the opening and short circuit characteristics before and after the antifuse burning, the precision of the adjusted circuit parameters is improved by the pre-trimming, and the pre-trimming is roughly combined with the pre-trimming and accurately combined with the pre-trimming, so that the pre-trimming process is greatly simplified, the pre-trimming time is shortened, the trimming efficiency is improved, and the production test cost is reduced.
The technical scheme of the invention is that the trimming method of the trimming circuit for the peripheral antifuse of the chip is characterized by comprising the following steps:
testing an initial value TEP _ i of a discharge parameter TEP before burning;
secondly, according to the initial value TEP _ i and the target value TEP _ t, calculating by using a theoretical formula, rounding or rounding to obtain a rough pre-trimming value N _ i, and converting the rough pre-trimming value N _ i to obtain an anti-fuse combination of the rough pre-trimming;
thirdly, performing rough virtual fusing on each antifuse according to the rough pre-trimming antifuse combination according to the bit, and testing a rough electrical parameter value TEP _ r of the TEP;
fourthly, supposing that the trimming step length of the theoretically designed electrical parameter TEP is PTS, calculating rough electrical parameter value deviation TEP _ d = TEP _ t-TEP _ r, calculating TEP _ d/PTS, and obtaining deviation N _ d of the rough pre-trimming value after taking an absolute value and rounding or rounding;
fifthly, determining the range from N-amin to N-amax according to the deviation N _ d, traversing and pre-trimming from the range from N-amin to N-amax, calculating anti-fuse trimming combinations in the range from N-amin to N-amax, virtually burning each anti-fuse according to the position of each anti-fuse trimming combination, testing corresponding TEP pre-trimming values, wherein the TEP pre-trimming values correspond to the anti-fuse combinations one by one, and when the tested electric parameter value is closest to the target value under a certain anti-fuse combination, obtaining an accurate anti-fuse combination and a corresponding accurate pre-trimming value N-a;
sixthly, carrying out bit-by-bit burning on each anti-fuse according to the accurate pre-trimming and adjusting value N-a and the corresponding accurate anti-fuse combination, and testing and verifying whether the error between the final value TEP _ f and the target value TEP _ t of the electrical parameter TEP meets the requirement or not after the burning is finished.
Preferably, the method comprises the following steps: the theoretical formula is as follows:
TEP=K1+K2*N (1)
in the formula: TEP is the reference voltage; k1 is an unknown quantity that varies with temperature, process and supply voltage, but is a constant under the same test conditions; the same test conditions were: the temperature is the same, the process angle is the same, the power supply voltage is the same, and the same chip is obtained; k2 is a pre-designed constant, known; n is a trimming value, the trimming combination of the anti-fuse is obtained after the N is converted, the maximum value of the N is designed in advance and is also known, and the minimum value of the N is zero, namely the trimming is not carried out;
when the adjustment is not performed, N =0, and the formula (1) is substituted to obtain an initial value TEP _ i of the electrical parameter TEP:
TEP_i=K1 (2)
the target value TEP _ t of the electrical parameter TEP is also known and is obtained by substituting equation (1):
TEP_t=K1+K2*N_i (3)
and (3) obtaining a rough pre-trimming value N _ i by combining the formulas (2) and (3):
N_i=(TEP_t-TEP_i)/K2 (4)。
preferably, the method comprises the following steps: step three and step fifthly further include: when the corresponding switch Si (i =1,2,3, …, n) is controlled to perform virtual burning on the corresponding antifuse at the periphery of the chip, that is, when the first burning voltage Ti (i =1,2,3, …, n) is connected to the ground through the corresponding switch Si (i =1,2,3, …, n), the state after the corresponding antifuse is connected to the ground by a short circuit is simulated, and the electrical parameter TEP is changed accordingly; when the first burning voltage Ti (i =1,2,3, …, n) is suspended, the corresponding antifuse bit is not burned virtually.
Preferably, the method comprises the following steps: step four further includes with step fife:
the method includes the steps that N-amin is assumed to be the minimum value of a precise pre-trimming range, N-amax is the maximum value of the precise pre-trimming range, and N-a is a precise pre-trimming value meeting requirements;
second if TEP _ i is the minimum of TEP values,
then when TEP _ d >0, N-amin = N _ i, N-amax = N _ i + N _ d + 1;
when TEP _ d <0, N-amin = N _ i-N _ d-1, N-amax = N _ i;
when TEP _ d =0, N-a = N _ i;
if TEP _ i is the maximum of the TEP values, then
When TEP _ d >0, N-amin = N _ i-N _ d-1, N-amax = N _ i;
when TEP _ d <0, N-amin = N _ i, N-amax = N _ i + N _ d + 1;
when TEP _ d =0, N-a = N _ i.
The other technical solution of the present invention is the trimming circuit for the antifuse at the periphery of the chip, which is characterized in that the trimming circuit for the antifuse at the periphery of the chip is performed according to the trimming method of the trimming circuit for the antifuse at the periphery of the chip, the trimming circuit for the antifuse at the periphery of the chip comprises an integrated circuit, n-bit trimming circuits are arranged inside the integrated circuit and correspond to the first burning voltage Ti (i =1,2,3, …, n) one by one, and the switches Si (i =1,2,3, …, n) are respectively connected to pins of the first burning voltage Ti (i =1,2,3, …, n) of the integrated circuit; VDD is the power supply voltage pin of the integrated circuit; VSS is the ground pin of the integrated circuit; TEP is the output pin of the modified electrical parameter.
The first fusing voltage is the fusing voltage corresponding to each input pin of the integrated circuit.
Preferably, the method comprises the following steps: the switches Si (i =1,2,3, …, n) are each controlled independently such that the pins of the first firing voltage Ti (i =1,2,3, …, n) are each floating, or are each connected to ground, or are each connected to a second firing voltage VTi (i =1,2,3, …, n);
the second fusing voltage is the fusing voltage corresponding to each input pin of the integrated circuit at the periphery of the integrated circuit.
Preferably, the method comprises the following steps: the switch Si (i =1,2,3, …, n) is selected from a MOSFET switch tube, a BJT switch tube, a relay or a combination thereof.
Preferably, the method comprises the following steps: the second burning voltages VTi (i =1,2,3, …, n) are independent or connected to the same voltage, depending on the type of device constituting the antifuse and the trimming circuit.
Compared with the prior art, the invention has the beneficial effects that:
the trimming method of the chip peripheral antifuse pre-trimming and adjusting circuit utilizes the opening and short-circuit characteristics before and after antifuse burning to achieve virtual burning of antifuses and pre-trimming and adjusting of electrical parameters through controlling the chip peripheral switches, in order to shorten trimming time, rough pre-trimming and adjusting are firstly calculated through a theoretical formula, then the range of precise pre-trimming and adjusting is narrowed and locked through the deviation between a rough pre-trimming and adjusting value and a target value, corresponding precise antifuse combinations are obtained through traversing pre-trimming and adjusting in the small range, and then the antifuse burning and trimming are carried out according to the combinations to obtain the electrical parameters meeting requirements; the combination of rough pre-trimming and precise pre-trimming and adjusting greatly simplifies the pre-trimming and adjusting process, shortens the pre-trimming and adjusting time, improves the trimming and adjusting efficiency and reduces the production and test cost.
The anti-fuse and the trimming circuit thereof can be realized by adopting conventional devices of a standard CMOS low-voltage process, and have good process compatibility; the adverse effects of random factors such as device matching precision, offset voltage and the like are reduced through pre-trimming, and the precision of trimmed electrical parameters is greatly improved, so that the product quality of the integrated circuit is improved.
When the antifuse is sintered, the power supply voltage VDD is connected to the power supply voltage which is not more than 5V and can also be grounded, then proper high voltage is added to the first sintering voltage Ti (i =1,2,3, …, n) to sinter the antifuse, the first sintering voltage is generally 8V-19V, because the resistor Ri is placed on field oxygen, the dielectric thickness of the antifuse is far less than the field oxygen thickness, the withstand voltage of Ri is far greater than the first sintering voltage of the antifuse, namely Ri cannot be damaged during sintering, meanwhile, the resistance value of Ri is large, after Ri is subjected to current limiting, the current Iti is small and is of the uA level, and therefore impact of large current on a detection circuit and a constant current source circuit is avoided.
In the anti-fuse trimming circuit, when the anti-fuse is burned in a test state, the detection voltage VSi is short-circuited to the ground, and the detection circuit and the constant current source circuit are safer.
The antifuse trimming circuit provided by the invention has the advantages that the resistor Ri with high voltage resistance and high resistance value on field oxygen is connected with a low-resistance circuit in series, so that high-voltage isolation and current limiting during burning are realized, the impact of high voltage and large current on other circuits of a chip is avoided, the antifuse can be reliably and stably burnt, and the resistor Ri and other devices and circuits in an integrated circuit cannot be damaged during burning, so that the antifuse and the antifuse trimming circuit can be realized by conventional devices of a standard CMOS (complementary metal oxide semiconductor) low-voltage process.
(6) The anti-fuse trimming circuit is a low-resistance circuit from a parasitic diode PDi of a constant current source circuit PMi to a power supply voltage VDD and then to the ground, the low-resistance circuit is connected with a high resistance Ri in series, the voltage drop on the PDi is about 0.7V generally, so the detection voltage VSi is about VDD +0.7V, most of high voltage during burning falls on two ends of the high resistance Ri, the impact of the high voltage on the detection circuit and the constant current source circuit is avoided, and the anti-fuse trimming circuit is safe as long as the (VDD +0.7V) is less than the highest withstand voltage of the detection circuit and the constant current source circuit.
Drawings
FIG. 1 is a diagram of a conventional antifuse trimming circuit;
FIG. 2 is a circuit diagram of an anti-fuse trimming circuit according to the present invention;
FIG. 3 is a circuit diagram of the trimming circuit for the periphery of the chip according to the present invention;
FIG. 4 is a circuit diagram of an anti-fuse trimming circuit according to a second preferred embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings:
fig. 3 shows an embodiment of the on-chip periphery trimming circuit of the present invention.
Referring to fig. 3, the trimming circuit for antifuse at periphery of chip includes an integrated circuit, in which n-bit trimming circuit for antifuse is in one-to-one correspondence with a first burning voltage Ti (i =1,2,3, …, n), and switches Si (i =1,2,3, …, n) are respectively connected to pins of the first burning voltage Ti (i =1,2,3, …, n) of the integrated circuit; VDD is a power supply voltage pin of the integrated circuit; VSS is the ground pin of the integrated circuit; TEP is the output pin of the modified electrical parameter. The switch Si (i =1,2,3, …, n) may be a MOSFET switch tube, a BJT switch tube, a relay, or other switching devices, or a combination of these switching devices, and the switch Si (i =1,2,3, …, n) may be independently controlled, such that pins of the first fusing voltage Ti (i =1,2,3, …, n) may be respectively suspended, may be respectively connected to the ground, and may be respectively connected to the second fusing voltage VTi (i =1,2,3, …, n); the second burning voltages VTi (i =1,2,3, …, n) may be independent or the same voltage connected together, depending on the type of device constituting the antifuse and its trimming circuit.
The trimming method of the trimming circuit for the peripheral antifuse in accordance with the present invention is described with reference to fig. 2 and 3, and includes the following steps:
testing an initial value TEP _ i of a discharge parameter TEP before burning;
calculating by using a theoretical formula according to the initial value TEP _ i and the target value TEP _ t, rounding or rounding to obtain a rough pre-trimming value N _ i, and converting (for example, converting) the rough pre-trimming value N _ i into a binary number to obtain an anti-fuse combination of the rough pre-trimming;
and thirdly, performing rough virtual fusing on each antifuse according to the obtained rough pre-trimming antifuse combination according to the bits, and testing a rough electrical parameter value TEP _ r of the TEP. Because the anti-fuse is open to the ground before being burned, and is short-circuited to the ground after being burned, the anti-fuse of the corresponding bit is virtually burned by controlling the corresponding switch Si (i =1,2,3, …, n) at the periphery of the chip, that is, when the first burning voltage Ti (i =1,2,3, …, n) is connected to the ground through the corresponding switch Si (i =1,2,3, …, n), the state after the corresponding anti-fuse is short-circuited to the ground is simulated, the electrical parameter TEP is changed accordingly, and when the first burning voltage Ti (i =1,2,3, …, n) is suspended, the corresponding anti-fuse bit is not virtually burned;
and fourthly, supposing that the trimming step length of the theoretically designed electrical parameter TEP is PTS, calculating a rough electrical parameter value deviation TEP _ d = TEP _ t-TEP _ r, then calculating TEP _ d/PTS, and obtaining an absolute value and rounding or rounding to obtain a deviation N _ d of a rough pre-trimming value.
The invention can be used for adjusting various electrical parameters, and different theoretical formulas of the electrical parameters are different, and common electrical parameters, such as reference voltage, have the general form of:
TEP=K1+K2*N (1)
in the formula: TEP is the reference voltage; k1 is an unknown quantity, which varies with temperature, process and power supply voltage, but is a constant under the same test conditions (same temperature, same process angle, same power supply voltage, same chip); k2 is a pre-designed constant, known; n is a trimming value, the trimming combination of the anti-fuse is obtained after the N is converted, the maximum value of the N is designed in advance and is also known, and the minimum value of the N is zero, namely the trimming is not carried out;
when the adjustment is not performed, N =0, and the formula (1) is substituted to obtain an initial value TEP _ i of the electrical parameter TEP:
TEP_i=K1 (2)
the target value TEP _ t of the electrical parameter TEP is also known and is obtained by substituting equation (1):
TEP_t=K1+K2*N_i (3)
and (3) obtaining a rough pre-trimming value N _ i by combining the formulas (2) and (3):
N_i=(TEP_t-TEP_i)/K2 (4)。
assuming that N-amin is the minimum value of the fine pre-trimming range and N-amax is the maximum value of the fine pre-trimming range, N-a is the fine pre-trimming value that meets the requirements, since the electrical parameter TEP varies monotonically with the antifuse, if TEP _ i is the minimum value of all possible TEP values,
then when TEP _ d >0, N-amin = N _ i, N-amax = N _ i + N _ d +1,
when TEP _ d <0, N-amin = N _ i-N _ d-1, N-amax = N _ i;
when TEP _ d =0, N-a = N _ i;
if TEP _ i is the maximum of all possible TEP values, then
When TEP _ d >0, N-amin = N _ i-N _ d-1, N-amax = N _ i,
when TEP _ d <0, N-amin = N _ i, N-amax = N _ i + N _ d + 1;
when TEP _ d =0, N-a = N _ i;
fifthly, determining the range from N-amin to N-amax according to the deviation N _ d, performing small-range traversal pre-trimming from N-amin to N-amax, calculating all possible anti-fuse trimming combinations in the range from N-amin to N-amax, performing virtual burning on each anti-fuse according to the position of each anti-fuse trimming combination, testing corresponding TEP pre-trimming values, wherein the TEP pre-trimming values correspond to the anti-fuse combinations one by one, and when the tested electric parameter value is closest to the target value under a certain anti-fuse combination, obtaining an accurate anti-fuse combination and a corresponding accurate pre-trimming value N-a;
sixthly, carrying out bit-by-bit burning on each anti-fuse according to the accurate pre-trimming and adjusting value N-a and the corresponding accurate anti-fuse combination, and testing and verifying whether the error between the final value TEP _ f and the target value TEP _ t of the electrical parameter TEP meets the requirement or not after the burning is finished.
Fig. 2 shows a first embodiment of an antifuse trimming circuit of the present invention.
Referring to fig. 2, fig. 2 only shows one of the antifuse trimming circuits, i.e. the ith (i =1,2,3, …, n), where VDD is the power supply voltage in fig. 2, the bias voltage VB provides a proper bias for the PMOS fet PMi, and when the drain voltage of the PMi is low enough, they form a constant current source circuit, the current Ii of the constant current source is designed to be small, for example, 100nA, to reduce power consumption, and PDi is the parasitic body diode of the PMi; the resistance Ri is a high resistance polycrystalline resistance located on the field oxygen, and the resistance value of Ri is designed to be large, such as 1M Ω; the antifuse is connected between a first burning voltage Ti (i =1,2,3, …, n) and ground, and is implemented by a circuit formed by conventional devices, such as NMOS or PMOS field effect transistors, capacitors of the type of POP, zener diodes, etc., and has the following electrical characteristics: before the sintering, the direct current open circuit is shown under low voltage (less than 5V), and after the sintering, the short circuit is shown; the detection circuit detects the voltage VSi, and the detection circuit may be a circuit such as an inverter, a schmitt trigger, or a comparator, or a combination of these circuits, and the detection voltage VSi of the detection circuit does not flow a current or flow a current.
Fig. 4 shows a second embodiment of an antifuse trimming circuit of the present invention.
The circuit of fig. 4 differs from the circuit of fig. 2 in that: the low-resistance circuit is not composed of a parasitic body diode PDi of a PMOS field effect transistor PMi, but a low-resistance circuit is added between the detection voltage VSi and the ground, the low-resistance circuit is opened or short-circuited to the ground under the control of a signal WT, and the low-resistance circuit can be composed of an NMOS field effect transistor or a PMOS field effect transistor; an integrated circuit employing the circuit of FIG. 4 has two states, WT is high (or low) and the low resistance circuit is shorted to ground in the test state, and WT is low (or high) and the low resistance circuit is open to ground in the normal operating state; in both the test state and the normal operating state, the supply voltage VDD is connected to the normal supply voltage.
The following describes, with reference to fig. 2 and 4, a method for detecting an antifuse trimming circuit implemented by a CMOS low-voltage process according to the present invention, including the following steps:
when the power supply voltage VDD is connected to a normal power supply voltage, before an antifuse is burned, a first burning voltage Ti (i =1,2,3, …, n) is open to the ground, and the first burning voltage Ti (i =1,2,3, …, n) is not externally connected with a voltage, and a current Ii of a constant current source makes a detection voltage VSi equal to the power supply voltage VDD;
secondly, when the detection circuit detects that the detection voltage VSi is larger than the set threshold voltage VTH, the output signal TSi (i =1,2,3, …, n) of the detection circuit is in a high level;
after the antifuse is burned and short-circuited to the ground, the detection voltage VSi is equal to Ii Ri and is a low voltage of mV level;
fourthly, when the detection circuit detects that the detection voltage VSi is smaller than the set threshold voltage VTL, the output TSi (i =1,2,3, …, n) of the detection circuit is at a low level, where VTL is less than or equal to VTH;
the regulated electrical parameters can be controlled and adjusted through the high and low level changes of the output signal TSi (i =1,2,3, …, n) of each anti-fuse trimming circuit, so that the output signal TSi (i =1,2,3, …, n) meets the set requirements.
The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.
Claims (8)
1. A trimming method for a chip peripheral anti-fuse pre-trimming circuit is characterized by comprising the following steps:
testing an initial value TEP _ i of a discharge parameter TEP before burning;
secondly, according to the initial value TEP _ i and the target value TEP _ t, calculating by using a theoretical formula, rounding or rounding to obtain a rough pre-trimming value N _ i, and converting the rough pre-trimming value N _ i to obtain an anti-fuse combination of the rough pre-trimming;
thirdly, performing rough virtual fusing on each antifuse according to the rough pre-trimming antifuse combination according to the bit, and testing a rough electrical parameter value TEP _ r of the TEP;
fourthly, supposing that the trimming step length of the theoretically designed electrical parameter TEP is PTS, calculating rough electrical parameter value deviation TEP _ d = TEP _ t-TEP _ r, calculating TEP _ d/PTS, and obtaining deviation N _ d of the rough pre-trimming value after taking an absolute value and rounding or rounding;
fifthly, determining the range from N-amin to N-amax according to the deviation N _ d, traversing and pre-trimming from the range from N-amin to N-amax, calculating anti-fuse trimming combinations in the range from N-amin to N-amax, virtually burning each anti-fuse according to the position of each anti-fuse trimming combination, testing corresponding TEP pre-trimming values, wherein the TEP pre-trimming values correspond to the anti-fuse combinations one by one, and when the tested electric parameter value is closest to the target value under a certain anti-fuse combination, obtaining an accurate anti-fuse combination and a corresponding accurate pre-trimming value N-a;
sixthly, carrying out bit-by-bit burning on each anti-fuse according to the accurate pre-trimming and adjusting value N-a and the corresponding accurate anti-fuse combination, and testing and verifying whether the error between the final value TEP _ f and the target value TEP _ t of the electrical parameter TEP meets the requirement or not after the burning is finished.
2. The method for trimming the peripheral antifuse pre-trimming circuit of claim 1, wherein the steps are represented by the following theoretical formula:
TEP=K1+K2*N (1)
in the formula: TEP is the reference voltage; k1 is an unknown quantity that varies with temperature, process and supply voltage, but is a constant under the same test conditions; the same test conditions were: the temperature is the same, the process angle is the same, the power supply voltage is the same, and the same chip is obtained; k2 is a pre-designed constant, known; n is a trimming value, the trimming combination of the anti-fuse is obtained after the N is converted, the maximum value of the N is designed in advance and is also known, and the minimum value of the N is zero, namely the trimming is not carried out;
when the adjustment is not performed, N =0, and the formula (1) is substituted to obtain an initial value TEP _ i of the electrical parameter TEP:
TEP_i=K1 (2)
the target value TEP _ t of the electrical parameter TEP is also known and is obtained by substituting equation (1):
TEP_t=K1+K2*N_i (3)
and (3) obtaining a rough pre-trimming value N _ i by combining the formulas (2) and (3):
N_i=(TEP_t-TEP_i)/K2 (4)。
3. the method for trimming the peripheral antifuse pre-trimming circuit of claim 1, wherein the step iii and the step fifthly further comprise: when the corresponding switch Si (i =1,2,3, …, n) is controlled to perform virtual burning on the corresponding antifuse at the periphery of the chip, that is, when the first burning voltage Ti (i =1,2,3, …, n) is connected to the ground through the corresponding switch Si (i =1,2,3, …, n), the state after the corresponding antifuse is connected to the ground by a short circuit is simulated, and the electrical parameter TEP is changed accordingly; when the first burning voltage Ti (i =1,2,3, …, n) is suspended, the corresponding antifuse bit is not burned virtually.
4. The trimming method for the chip peripheral antifuse pre-trimming circuit according to claim 1, wherein the step fifthly further comprises:
the method includes the steps that N-amin is assumed to be the minimum value of a precise pre-trimming range, N-amax is the maximum value of the precise pre-trimming range, and N-a is a precise pre-trimming value meeting requirements;
second if TEP _ i is the minimum of TEP values,
then when TEP _ d >0, N-amin = N _ i, N-amax = N _ i + N _ d + 1;
when TEP _ d <0, N-amin = N _ i-N _ d-1, N-amax = N _ i;
when TEP _ d =0, N-a = N _ i;
if TEP _ i is the maximum of the TEP values, then
When TEP _ d >0, N-amin = N _ i-N _ d-1, N-amax = N _ i;
when TEP _ d <0, N-amin = N _ i, N-amax = N _ i + N _ d + 1;
when TEP _ d =0, N-a = N _ i.
5. A peripheral antifuse pre-trimming circuit, wherein the antifuse pre-trimming is performed by the trimming method of the peripheral antifuse pre-trimming circuit according to claim 1, the peripheral antifuse pre-trimming circuit comprises an integrated circuit, n antifuse trimming circuits are arranged inside the integrated circuit and correspond to first burning voltages Ti (i =1,2,3, …, n) in a one-to-one manner, and switches Si (i =1,2,3, …, n) are respectively connected to pins of the first burning voltages Ti (i =1,2,3, …, n) of the integrated circuit; VDD is the power supply voltage pin of the integrated circuit; VSS is the ground pin of the integrated circuit; TEP is the output pin of the modified electrical parameter.
6. The on-chip antifuse pre-trimming circuit of claim 5, wherein the switches Si (i =1,2,3, …, n) are independently controlled such that pins of the first burning voltage Ti (i =1,2,3, …, n) are respectively floating, or are respectively connected to ground, or are respectively connected to the second burning voltage VTi (i =1,2,3, …, n).
7. The on-chip antifuse pre-trimming circuit of claim 6, wherein the switch Si (i =1,2,3, …, n) is selected from a MOSFET switch transistor, a BJT switch transistor, a relay, or a combination thereof.
8. The on-chip antifuse pre-trimming circuit of claim 5, wherein the second burning voltages VTi (i =1,2,3, …, n) are independent or connected to the same voltage according to the type of the device constituting the antifuse and the trimming circuit.
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