CN112699695B

CN112699695B - RFID reader-writer software verification device and method and electronic equipment

Info

Publication number: CN112699695B
Application number: CN202110305056.8A
Authority: CN
Inventors: 胡建国; 邓锐; 吴劲; 王德明; 丁颜玉; 段志奎
Original assignee: Guangzhou Intelligent City Development Institute
Current assignee: Guangzhou Intelligent City Development Institute
Priority date: 2021-03-23
Filing date: 2021-03-23
Publication date: 2021-07-20
Anticipated expiration: 2041-03-23
Also published as: CN112699695A

Abstract

The invention provides a device and a method for verifying RFID reader software and electronic equipment, wherein the device comprises: the test module is used for generating a clock excitation signal and a register configuration signal and sending the two signals to the reader-writer module; the reader module is used for configuring the initial value of the register according to the register configuration signal and sending a request command in a corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial value of the register; the system is also used for generating receiving interruption after receiving a response frame command replied by the tag chip module so as to reversely trigger the test module to read the current value of the register and finish data communication flow verification according to the current value; and the tag chip module is used for generating a response frame command according to the corresponding protocol communication flow and replying the response frame command to the reader-writer module after receiving the request command. The device can meet the verification requirements of carrying out multi-type protocol communication processes with different communication rates with multi-type RFID chips.

Description

RFID reader-writer software verification device and method and electronic equipment

Technical Field

The invention relates to the technical field of RFID read-write verification, in particular to a device and a method for verifying RFID reader software and electronic equipment.

Background

In the design of each sub-module of an integrated circuit of an RFID, it is usually necessary to pay attention to whether the design of a module or a function is implemented or not at all times so as to verify the correctness and stability of a design function in an RFID card reader module, especially, it is necessary to pay attention to the verification of data interaction communication performance and to find existing problems as soon as possible when a design function has a bug.

In the prior art, a hardware verification platform is generally used for communication performance verification, and the hardware verification platform includes an embedded program, a schematic diagram module, a structural diagram module, and the like, but there are some limitations: firstly, a hardware verification platform needs to test and verify each link of each module in the self verification process, so that the whole verification process is complicated; second, the set-up of a hardware authentication platform is time consuming and labor intensive, and generally supports only single protocol low rate data communications.

There is also a class of conventional software verification platforms, but such conventional software verification platforms often require manual input of stimulus to simulate the reply of the tag chip, which is prone to error and inefficient. Moreover, the conventional software verification platform generally only supports a single-protocol low-speed communication rate, and in the era of rapid and diversified development of communication modes and communication rates, the conventional software verification platform cannot gradually adapt to higher and higher full and complete verification requirements.

Disclosure of Invention

The invention provides a device and a method for verifying software of an RFID reader-writer and electronic equipment, which are used for overcoming the defects that in the prior art, the establishment of a hardware verification platform is time-consuming and labor-consuming, the verification process is complicated, the traditional software verification platform needs manual input excitation and has low efficiency and only supports a single protocol and low communication rate, and the effect of quickly and efficiently verifying communication flow is realized.

The invention provides a RFID reader-writer software verification device, comprising:

the test module is used for generating a clock excitation signal and a register configuration signal and sending the clock excitation signal and the register configuration signal to the reader-writer module through a protocol bus;

the reader module comprises a register and is used for configuring a register initial value according to the register configuration signal and sending a request command in a corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the register initial value; the test module is also used for generating receiving interruption after receiving a response frame command replied by the tag chip module so as to reversely trigger the test module to read the current value of the register and finish data communication flow verification according to the current value;

and the tag chip module is used for generating a response frame command according to the corresponding protocol communication flow and replying the response frame command to the reader-writer module after receiving the request command.

According to the software verification device of the RFID reader-writer provided by the invention, the test module comprises an excitation unit, a configuration unit, at least three protocol interfaces, a bus selection unit and a verification unit, wherein,

the excitation unit is used for generating a clock excitation signal;

the configuration unit is used for generating a register configuration signal;

the at least three protocol interfaces are respectively connected with the bus interface of the reader-writer module through a UART protocol bus, an SPI protocol bus and an IIC protocol bus which respectively correspond to the three protocol interfaces;

the bus selection unit is used for selecting one protocol bus from the UART protocol bus, the SPI protocol bus and the IIC protocol bus as a protocol bus for transmitting the clock excitation signal and the register configuration signal;

and the verification unit is used for reading the current value of the register and finishing the data communication flow verification according to the current value after the receiving interruption is generated by the reader-writer module.

According to the RFID reader software verifying apparatus provided by the present invention, the reader module further includes a control unit, a command requesting unit, and an interrupt unit, wherein,

the control unit is used for configuring the initial register value according to the register configuration signal;

the command request unit is used for sending a request command in a corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial register value;

and the interrupt unit is used for generating receiving interrupt after receiving a response frame command replied by the tag chip module so as to reversely trigger the verification unit in the test module, so that the verification unit reads the current value of the register and completes data communication flow verification according to the current value.

According to the RFID reader software verification device provided by the invention, the corresponding protocol communication flow is one matched with the clock excitation signal and the initial value of the register in a protocol communication flow set, and the protocol communication flow set at least comprises any one of an ISO14443TYPEA protocol communication flow, an ISO14443TYPEB protocol communication flow and an ISO15693 protocol communication flow;

and the ISO14443TYPEA protocol communication flow, the ISO14443TYPEB protocol communication flow and the ISO15693 protocol communication flow respectively have a plurality of communication modes with different communication speed.

The invention also provides a software verification method of the RFID reader-writer, which comprises the following steps:

acquiring a clock excitation signal and a register configuration signal generated by a test module;

configuring an initial value of a register according to the register configuration signal;

sending a request command in a corresponding protocol communication flow to a tag chip module according to the clock excitation signal and the initial register value;

and receiving a response frame command replied by the tag chip module according to the request command and the corresponding protocol communication flow, generating a receiving interrupt to reversely trigger the test module to read the current value of the register and complete data communication flow verification according to the current value.

According to the software verification method of the RFID reader, when the corresponding protocol communication flow is an ISO14443TYPEA protocol communication flow, correspondingly, the sending a request command in the corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial value of the register and the receiving a response frame command replied by the tag chip module according to the request command and the corresponding protocol communication flow generate a receiving interrupt to reversely trigger the test module to read the current value of the register and complete data communication flow verification according to the current value, specifically comprising:

sending a card searching command REQA and/or a waking command WUPA according to the clock excitation signal and the initial value of the register;

receiving an ATQA response frame command replied by the tag chip module and then sending an anti-collision command;

receiving a UID response frame command replied by the tag chip module, and sending a SELECT card selection command after judging that the anti-collision processing process is finished;

receiving an SAK response frame command replied by a tag chip module, and judging whether the UID response frame command is complete or not according to a third bit on the SAK response frame command;

if the SAK response frame command is complete, judging whether the tag chip module follows an ISO/IEC14443-4 protocol or not according to a sixth bit on the SAK response frame command;

if yes, sending a RATS command to the tag chip module, receiving an ATS response frame command replied by the tag chip module, and judging whether the tag chip module supports a high communication rate or not according to a TA interface byte in the ATS response frame command;

if the communication rate is supported, sending a PPS command to the tag chip module to enable the tag chip module to enter a high communication rate state, self-configuring the tag chip module to enter a corresponding high communication rate state according to received PPS response content replied by the tag chip module, and updating the current value of the register;

and sending a random number command to the tag chip module by using the high communication rate, generating a receiving interrupt after receiving a random number replied by the tag chip module at a corresponding high communication rate, reversely triggering the test module to read the current value of the register, and determining that the data communication flow is successfully verified according to the current value.

According to the software verification method for the RFID reader, when the corresponding protocol communication flow is an ISO14443TYPEB protocol communication flow, correspondingly, the sending a request command in the corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial value of the register and the receiving a response frame command replied by the tag chip module according to the request command and the corresponding protocol communication flow generate a receiving interrupt to reversely trigger the test module to read the current value of the register and complete data communication flow verification according to the current value, specifically comprising:

sending a card searching command REQB and/or a waking command WUPB according to the clock excitation signal and the initial value of the register;

receiving an ATQB response frame command replied by the tag chip module, and judging whether the tag chip module supports high communication rate and conforms to an ISO/IEC14443-3 protocol or not according to protocol information bytes in the ATQB response frame command;

if the high communication speed is supported and the ISO/IEC14443-3 protocol is followed, sending an ATTRIB command and changing parameter settings from a fifth bit to an eighth bit of a second byte in the ATTRIB command, sending the changed ATTRIB command to the tag chip module to enable the tag chip module to enter a high communication speed state, entering a corresponding high communication speed state according to self configuration of the changed ATTRIB command, and updating the current value of the register;

According to the software verification method for the RFID reader/writer provided by the present invention, when the corresponding protocol communication flow is an ISO15693 protocol communication flow, correspondingly, the sending a request command in the corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial register value and the receiving a response frame command replied by the tag chip module according to the request command and the corresponding protocol communication flow generate a receiving interrupt to reversely trigger the test module to read the current register value and complete the data communication flow verification according to the current value, specifically comprising:

according to the clock excitation signal and the initial value of the register, the reader module configures the command communication rate of the reader module and sends an INVENTRY command to the tag chip module;

configuring a response rate of a tag chip module according to the INVENTRY command, and determining a communication rate mode and a single-double load wave adopted by the tag chip module according to first to second bits in a first byte request mark of the INVENTRY command;

if the UID response frame command replied by the tag chip module is not received, the INVENTORY command is retransmitted to carry out time slot anti-collision processing;

and directly receiving or receiving a UID response frame command replied by the tag chip module after the time slot anti-collision processing is finished, performing read-write operation on the tag chip module according to the UID response frame command to obtain card internal information in the tag chip module, and generating receiving interruption to reversely trigger the test module to read the current value of the register and determine that the data communication flow is successfully verified according to the current value.

The invention also provides an electronic device, which comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, wherein when the processor executes the computer program, the software verification method of the RFID reader-writer is realized.

The present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the RFID reader software verification method as described in any one of the above.

The invention provides a device, a method and electronic equipment for verifying RFID reader software, wherein the device comprises a test module 110, a reader module 120 and a tag chip module 130, all the modules are matched with each other to work, and can support a plurality of types of protocol communication flows with various types of RFID chips, wherein the communication speeds of the various types of protocol communication flows are different, so that diversified and sufficient verification requirements can be met, the problems of the reader in design can be found out in a short time, and the functional requirements in design are improved; and a label chip module is introduced, so that a response frame command can be quickly and timely automatically generated and replied to the RFID reader-writer module, manual input excitation is not needed to simulate reply of the label chip, and the method is accurate and efficient.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an RFID reader software verification apparatus provided in the present invention;

FIG. 2 is a second schematic structural diagram of a RFID reader software verification apparatus provided in the present invention;

FIG. 3 is a third schematic structural diagram of a RFID reader software verification apparatus provided in the present invention;

FIG. 4 is a schematic flow chart of a software verification method for an RFID reader provided by the present invention;

FIG. 5 is a schematic flow chart of a corresponding protocol communication flow being an ISO14443TYPEA protocol communication flow;

FIG. 6 is a schematic flow chart of a corresponding protocol communication flow being an ISO14443TYPEB protocol communication flow;

FIG. 7 is a schematic flow chart of a corresponding protocol communication flow being an ISO15693 protocol communication flow;

fig. 8 is a schematic structural diagram of an electronic device provided in the present invention.

Reference numerals:

110: a test module; 120: a reader-writer module; 130: a tag chip module;

1101: an excitation unit; 1102: a configuration unit; 1103: at least three protocol interfaces;

1104: a bus selection unit; 1105: a verification unit;

1201: a register; 1202: a control unit; 1203: a command requesting unit;

1204: an interrupt unit;

810: a processor; 820: a communication interface; 830: a memory; 840 a communication bus.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The following describes an RFID reader software verification apparatus, method and electronic device provided by the present invention with reference to fig. 1 to 8.

The invention provides a RFID reader software verification device, fig. 1 is one of the structural schematic diagrams of the RFID reader software verification device provided by the invention, as shown in fig. 1, the device comprises: a test module 110, a reader module 120, and a tag chip module 130, wherein,

the test module 110 is configured to generate a clock excitation signal and a register configuration signal, and send both the clock excitation signal and the register configuration signal to the reader module through a protocol bus.

The test module 110, or the clock excitation signal generated by the test module 110, may also be directly understood as the test excitation testbeacon, that is, the test excitation testbeacon file is written in advance, the test excitation testbeacon file is added to the test module of the test engineering, the simulation condition is compiled in a ModelSim simulation tool, and then the waveform and the value of each module register in the reader/writer module are observed to realize the verification of the design function. The test module 110 is connected to the bus interface in the reader/writer module through one or more protocol interfaces (for example, three protocol interfaces including UART, SPI, and IIC) through a corresponding type of protocol bus, and only one protocol bus is illustrated in fig. 1. When the test module 110 is in operation, the protocol bus is selected to transmit the generated clock excitation signal and the register configuration signal to the reader/writer module through the selected optimal protocol bus. The clock excitation signal is used as excitation trigger information for data interaction communication between a subsequent reader-writer module and the tag chip module, and the register configuration signal is used for configuring a register in the reader-writer module.

The reader module 120 comprises a register, and is configured to configure a register initial value according to the register configuration signal, and send a request command in a corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the register initial value; and the test module is also used for generating receiving interruption after receiving a response frame command replied by the tag chip module so as to reversely trigger the test module to read the current value of the register and finish data communication flow verification according to the current value.

The test module 110 performs data transmission with the reader/writer module through the protocol bus, and the test module 110 configures information such as an initial value of a register in the reader/writer module by registering a configuration signal thereof. And then the reader/writer module 120 makes the reader/writer module 120 be in the request command flow of different protocol communication flows according to the clock excitation signal and the initial register value, and further performs data interaction communication with the tag chip module by using the request command in the protocol communication flow corresponding to the clock excitation signal and the initial register value.

In addition, the reader/writer module 120 also generates a receiving interrupt after receiving a response frame command replied by the tag chip module, so as to reversely trigger the test module 110 to read the current value of the register and complete the data communication flow verification according to the current value.

The tag chip module 130 is configured to generate a response frame command according to the corresponding protocol communication process and reply to the reader module after receiving the request command.

The tag chip module 130 adopts a tag chip design module capable of supporting three protocol communication types of ISO14443TYPEA, TYPEB and ISO 15693. And in practical application, the tag chip module can still be connected with the reader-writer module in a non-contact wireless mode like a common tag chip to be identified. However, for convenience of explanation and transmission, the embodiment shown in fig. 1 is configured to use a wired connection between the tag chip module 130 and the reader/writer module, and specifically, the reader/writer module 120 forms a bidirectional information transmission path (as shown by the bidirectional solid arrow in fig. 1) with the tag chip module 130 through the transmitting bus MODUDATA and the receiving bus OUTI 2.

In addition, the tag chip module 130 can be used to realize various communication rates, such as TYPEA and TYPEB low speed 106kbps, high speed 212kbps, 424kbps, 848 kbps; ISO15693 double subcarrier low speed 6.67kbps, high speed 26.69kbps, single subcarrier low speed 6.62kbps, high speed 26.48kbps, fast inventoryy read mode.

The test module 110 is connected to a bus interface in the reader/writer module 120 through one or more protocol interfaces, the test module 110 serves as a host, the reader/writer module 120 serves as a slave, data interaction is performed between the test module and the reader/writer module 120 through a data protocol bus, and the reader/writer module 120 forms a channel with the tag chip module 130 through a transmission bus MODUDATA and a reception bus OUTI2, thereby comprehensively constituting an RFID reader/writer software verification apparatus. In the apparatus, the test module 110 configures the register in the reader module 120, so that the reader module 120 enters a multi-type protocol communication process with different communication rates with the tag chip module 130, controls the reader module 120 to send a corresponding request command to the tag chip module 130, then the tag chip module 130 replies a response signal such as a response frame command after receiving the request command of the corresponding protocol flow of the reader/writer module 120, and input to the reader-writer module through the receiving bus OUTI2, the reader-writer module will generate receiving interruption after receiving, the test excitation testbeacon reads the value of the register in the reader-writer module after detecting the interruption, and simultaneously observes the current value of the register on the ModelSim, and performing functional analysis processing according to the current numerical value of the register, and further performing full verification and testing of various functional points through the condition of the whole communication interaction of the device.

The RFID reader software verification device provided by the invention comprises a test module 110, a reader module 120 and a tag chip module 130, wherein the modules are matched with each other to work, so that various protocol communication flows with different communication rates and different heights can be supported to be rapidly and effectively carried out with various types of RFID chips, diversified and sufficient verification requirements can be met, the problems of the reader in design can be found out in a short time, and the functional requirements in design are improved; and a label chip module is introduced, so that a response frame command can be quickly and timely automatically generated and replied to the RFID reader-writer module, manual input excitation is not needed to simulate reply of the label chip, and the method is accurate and efficient.

According to the RFID reader software verification apparatus provided by the present invention, fig. 2 is a second schematic structural diagram of the RFID reader software verification apparatus provided by the present invention, as shown in fig. 2, on the basis of the apparatus structure shown in fig. 1, the test module 110 further includes an excitation unit 1101, a configuration unit 1102, at least three protocol interfaces 1103, a bus selection unit 1104 and a verification unit 1105, wherein,

the excitation unit 1101 is configured to generate a clock excitation signal;

the clock excitation signal generated by the excitation unit 1101 can also be directly understood as test excitation testbeacon, that is, the test excitation testbeacon file is written in advance, the test excitation testbeacon file is added into a test module of a test project, the simulation condition is compiled in a model sim simulation tool, and then the waveform and the numerical value of each module register in the reader-writer module are observed to realize the verification of the design function.

The configuration unit 1102 is configured to generate a register configuration signal;

the register configuration signal generated by the configuration unit 1102 is used to configure the register in the reader/writer module.

The at least three protocol interfaces 1103 are respectively connected with the bus interfaces of the reader-writer module through the UART protocol bus, the SPI protocol bus, and the IIC protocol bus corresponding to each protocol interface;

it should be understood that the testprobe includes three bus timings of UART, SPI, and IIC, and certainly, the number of the bus timings may be 3 or more, and the embodiment is described by taking 3 as an example. (UART protocol interface and bus interface are connected through UART protocol bus, see protocol interface I and protocol bus I in FIG. 2; SPI protocol interface and bus interface are connected through SPI protocol bus, see protocol interface II and protocol bus II in FIG. 2; IIC protocol interface and bus interface are connected through IIC protocol bus, see protocol interface III and protocol bus III in FIG. 2).

When the test module 110 is in operation, an optimum protocol bus may be selected to transmit the clock excitation signal generated by the excitation unit 1101 and the register configuration signal generated by the configuration unit 1102 to the reader/writer module through the selected protocol bus.

The three buses differ in that: the three buses can transmit at different communication rates, the UART protocol interface supports the highest communication rate of 1.2Mbps, the SPI protocol interface supports the highest communication rate of 10Mbps, and the IIC protocol interface supports communication rates including a standard mode of 100Kbps, a fast mode of 400Kbps and a high-speed mode of 3.4 Mbps.

The bus selection unit 1104 is configured to select one protocol bus from the UART protocol bus, the SPI protocol bus, and the IIC protocol bus as a protocol bus for transmitting the clock excitation signal and the register configuration signal;

the bus selection unit 1104 is configured to select one protocol bus from the UART protocol bus, the SPI protocol bus, and the IIC protocol bus, and transmit the clock excitation signal generated by the excitation unit 1101 and the register configuration signal generated by the configuration unit 1102 to the reader/writer module through the selected protocol bus. The selection of the most suitable protocol bus may be based on the required communication rate, and is not limited herein.

Two single-bit data lines select0 and select1 (e.g., S1 and S2 of the bus selection unit shown in fig. 2) are further provided between the test module 110 and the reader/writer module 120, and the test module changes the values of select0 and select1 in advance, so that the master/slave selects one protocol bus from the UART protocol bus, the SPI protocol bus, and the IIC protocol bus to perform data transmission according to the two values. Such as: select1, select0 with value 00, indicate that SPI bus is selected for communication; when the numerical value is 01, the IIC bus is selected for communication; when the value is 10, the UART bus is selected for communication; a value of 11 indicates that the selection is invalid.

The verification unit 1105 is configured to, after the receiving interrupt is generated by the reader/writer module, read the current value of the register and complete data communication flow verification according to the current value.

The test module further includes a verification unit 1105, configured to read the current value of the register in the reader/writer module 120 after the reception interrupt is generated by the reader/writer module 120, and simultaneously observe the current value of the register on the ModelSim, perform function analysis processing according to the current value of the register, and complete data communication flow verification according to the current value.

According to the RFID reader software verification apparatus provided by the present invention, fig. 3 is a third schematic structural diagram of the RFID reader software verification apparatus provided by the present invention, as shown in fig. 3, on the basis of the apparatus structure shown in fig. 2, the reader module 120 further includes a control unit 1202, a command request unit 1203 and an interrupt unit 1204, in addition to a register 1201, wherein,

the control unit 1202 is configured to configure the register initial value according to the register configuration signal;

the control unit 1202 is configured to configure information such as the initial value of the register according to the register configuration signal sent by the test module 110.

The command requesting unit 1203 is configured to send a request command in a corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the register initial value;

a command requesting unit 1203, configured to send a request command in a corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the register initial value, where the corresponding protocol communication flow is one of a set of protocol communication flows that matches the clock excitation signal and the register initial value.

The interrupt unit 1204 is configured to generate a receiving interrupt after receiving a response frame command replied by the tag chip module, so as to reversely trigger the verification unit in the test module, so that the verification unit reads the current value of the register and completes data communication flow verification according to the current value.

An interrupt unit 1204, configured to generate a receive interrupt after receiving a response frame command replied by the tag chip module 130, so as to trigger the verification unit 1104 in the test module 110 in a reverse direction, so that the verification unit reads the current value of the register 1201 and completes data communication flow verification according to the current value.

In the apparatus, the test module 110 configures the register in the reader/writer module 120, so that the reader/writer module 120 enters a multi-type protocol communication process capable of rapidly and efficiently performing communication rates with different levels, such as the ISO14443TYPEA protocol communication process, the ISO14443TYPEB protocol communication process, the ISO15693 protocol communication process, and the like, and controls the reader/writer module 120 to send a corresponding request command to the tag chip module 130, then the tag chip module 130 replies a response signal, such as a response frame command, after receiving the request command of the corresponding protocol process of the reader/writer module 120, and inputs the response signal to the reader/writer module through the receiving bus OUTI2, the reader/writer module generates a receiving interrupt after receiving the request command, reads the value of the register in the reader/writer module after detecting the interrupt by the test stimulus testbeacon, and simultaneously observes the current value of the register on the model sim, and performing functional analysis processing according to the current numerical value of the register, and further performing full verification and testing of various functional points through the condition of the whole communication interaction of the device.

The present invention further provides a software verification method for an RFID reader, fig. 4 is a schematic flow chart of the software verification method for an RFID reader provided by the present invention, and as shown in fig. 4, the method includes:

510. acquiring a clock excitation signal and a register configuration signal generated by a test module;

the reader-writer module obtains the clock excitation signal and the register configuration signal generated by the test module, or the test module sends the generated clock excitation signal and the register configuration signal to the reader-writer module through the protocol bus.

520. Configuring an initial value of a register according to the register configuration signal;

and the reader-writer module configures information such as initial values of registers in the reader-writer module according to the register configuration signals.

530. Sending a request command in a corresponding protocol communication flow to a tag chip module according to the clock excitation signal and the initial register value;

and the reader-writer module sends a request command in a corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial value of the register. And the corresponding protocol communication flow is one of the protocol communication flow set matched with the clock excitation signal and the initial value of the register.

540. And receiving a response frame command replied by the tag chip module according to the request command and the corresponding protocol communication flow, generating a receiving interrupt to reversely trigger the test module to read the current value of the register and complete data communication flow verification according to the current value.

The reader-writer module receives a response frame command replied by the tag chip module according to the request command 530 and the corresponding protocol communication flow, generates a receiving interrupt, and feeds back the receiving interrupt information to the test module to reversely trigger the test module to read the current value of the register so as to complete the data communication flow verification according to the current value.

The RFID reader software verification method provided by the invention can support the rapid and effective multi-type protocol communication process with different communication rates and different heights with multi-type RFID chips so as to meet diversified and sufficient verification requirements, can find out the problems of the reader in design in a short time and perfect the functional requirements in design; and the tag chip module is introduced to participate in communication, and a response frame command can be quickly and timely automatically generated to be replied to the RFID reader-writer module, so that manual input excitation is not needed to simulate reply of the tag chip, and the method is accurate and efficient.

According to the RFID reader software verification method provided by the present invention, fig. 5 is a schematic flow chart of a corresponding protocol communication flow being an ISO14443TYPEA protocol communication flow, as shown in fig. 5, when the corresponding protocol communication flow is an ISO14443TYPEA protocol communication flow, correspondingly, on the basis of the embodiment shown in fig. 4, the step 530 and the step 540 specifically include (the step 530 specifically includes the step 631, and the step 540 specifically includes the step 641 and the step 647):

before the method steps are processed, the test module can also generate a plurality of reset signals, and the reader-writer module and the label chip module are reset in advance through the reset signals so as to be in an initialization state. And the test module is set to generate a clock excitation signal of 27.12Mhz for the reader module.

631. Sending a card searching command REQA and/or a waking command WUPA according to the clock excitation signal and the initial value of the register;

according to the 27.12Mhz clock excitation signal and the configured initial value of the register, the reader module sends a card searching command REQA and/or a wake-up command WUPA to the tag chip module.

641. Receiving an ATQA response frame command replied by the tag chip module and then sending an anti-collision command;

the reader-writer module receives the ATQA response frame command replied by the tag chip module and then sends the anti-collision command to the tag chip module again.

642. Receiving a UID response frame command replied by the tag chip module, and sending a SELECT card selection command after judging that the anti-collision processing process is finished;

the reader module receives the UID response frame command replied by the tag chip module and sends a SELECT card selection command after judging that the anti-collision processing process is finished; and if the anti-collision processing process is judged not to be completed, the communication fails.

643. Receiving an SAK response frame command replied by a tag chip module, and judging whether the UID response frame command is complete or not according to a third bit on the SAK response frame command;

and the reader-writer module receives the SAK response frame command replied by the tag chip module and judges whether the UID response frame command is complete or not according to a third bit on the SAK response frame command.

644. If the SAK response frame command is complete, judging whether the tag chip module follows an ISO/IEC14443-4 protocol or not according to a sixth bit on the SAK response frame command;

if the reader-writer module judges whether the UID response frame command is complete, whether the tag chip module follows an ISO/IEC14443-4 protocol or not is continuously judged according to a sixth bit on the SAK response frame command; and if the UID response frame command is judged to be incomplete, executing the anti-collision processing of the next serial level again.

645. If yes, sending a RATS command to the tag chip module, receiving an ATS response frame command replied by the tag chip module, and judging whether the tag chip module supports a high communication rate or not according to a TA interface byte in the ATS response frame command;

if the reader-writer module judges that the tag chip module follows an ISO/IEC14443-4 protocol, sending a RATS command to the tag chip module, receiving an ATS response frame command replied by the tag chip module, and judging whether the tag chip module supports a high communication rate or not according to TA interface bytes in the ATS response frame command; if the label chip module is judged not to follow the ISO/IEC14443-4 protocol, the communication fails; alternatively, the communication fails if the ATS response frame command is not successfully received.

646. If the communication rate is supported, sending a PPS command to the tag chip module to enable the tag chip module to enter a high communication rate state, self-configuring the tag chip module to enter a corresponding high communication rate state according to received PPS response content replied by the tag chip module, and updating the current value of the register;

if the reader-writer module judges that the tag chip module supports the high communication rate, the reader-writer module sends a PPS command to the tag chip module to enable the tag chip module to enter a high communication rate state, and enables the reader-writer module to enter a corresponding high communication rate state according to received PPS response content replied by the tag chip module through self-configuration, and meanwhile, the current numerical value of the register is updated.

And if the reader-writer module judges that the tag chip module does not support high communication rate, the communication rate does not need to be adjusted.

647. And sending a random number command to the tag chip module by using the high communication rate, generating a receiving interrupt after receiving a random number replied by the tag chip module at a corresponding high communication rate, reversely triggering the test module to read the current value of the register, and determining that the data communication flow is successfully verified according to the current value.

The reader-writer module sends a random number command to the tag chip module by using the 646 adjusted high communication rate, and generates a receiving interrupt to reversely trigger the test module to read the current value of the register after receiving the random number replied by the tag chip module at the corresponding high communication rate and determines that the data communication flow is successfully verified according to the current value; and if the reader-writer module fails to successfully receive the random number replied by the tag chip module at the corresponding high communication rate, the communication fails. The high communication rate may be, for example, 212kbps, 424kbps, 848kbps, or the like of the verification high speed rate.

Or, if the reader/writer module determines that the tag chip module does not support the high communication rate, when the tag chip module does not support the high communication rate or does not support the change of the communication rate, the reader/writer module directly sends (directly sends at a low communication rate) a random number command to the tag chip module, receives a random number which is directly replied by the tag chip module (directly replied at a corresponding low communication rate), and can also prove that the communication flow is successfully verified; and if the reader-writer module fails to successfully receive the random number replied by the tag chip module at the corresponding low communication rate, the communication fails.

In the whole process, after the reader-writer module receives the random number replied by the tag chip module, the communication flow between the reader-writer module and the tag chip module conforming to the ISO14443TYPEA protocol is verified successfully. In the verification process, the communication speed between the reader-writer module and the tag chip module can be changed by changing the configuration of the test module on the initial value and the like of the reader-writer register, so that the high-speed and low-speed transmitting and receiving functions of the reader-writer module can be fully verified, and the anti-collision function of the reader-writer module can also be verified.

According to the method for verifying the software of the RFID reader, fig. 6 is a schematic flow chart of a corresponding protocol communication flow being an ISO14443TYPEB protocol communication flow, as shown in fig. 6, when the corresponding protocol communication flow is an ISO14443TYPEB protocol communication flow, correspondingly, on the basis of the embodiment shown in fig. 4, the

steps

530 and 540 specifically include (the step 530 specifically includes the step 731, and the step 540 specifically includes the step 741 and 743):

731. Sending a card searching command REQB and/or a waking command WUPB according to the clock excitation signal and the initial value of the register;

the reader module sends a card searching command REQB and/or a wake-up command WUPB to the tag chip module according to the clock excitation signal of 27.12Mhz and a preset initial value of a register.

741. Receiving an ATQB response frame command replied by the tag chip module, and judging whether the tag chip module supports high communication rate and conforms to an ISO/IEC14443-3 protocol or not according to protocol information bytes in the ATQB response frame command;

the reader-writer module receives an ATQB response frame command replied by the tag chip module, and judges whether the tag chip module supports a high communication rate and simultaneously judges whether the tag chip module conforms to an ISO/IEC14443-3 protocol according to protocol information bytes in the ATQB response frame command.

And if the reader-writer module does not receive the response of the tag chip module, the reader-writer module continues to send a time Slot anti-collision Slot-MARKER frame command to the tag chip module, so that the tag chip module can generate a response to the reader-writer module after the time Slot matching of the tag chip module is completed: replying to the ATQB acknowledge frame command.

742. If the high communication speed is supported and the ISO/IEC14443-3 protocol is followed, sending an ATTRIB command and changing parameter settings from a fifth bit to an eighth bit of a second byte in the ATTRIB command, sending the changed ATTRIB command to the tag chip module to enable the tag chip module to enter a high communication speed state, entering a corresponding high communication speed state according to self configuration of the changed ATTRIB command, and updating the current value of the register;

if the reader-writer module judges that the tag chip module supports the high communication rate and also follows the ISO/IEC14443-3 protocol, the reader-writer module sends an ATTRIB command, changes the parameter settings from the fifth bit to the eighth bit of the second byte in the ATTRIB command to configure the high communication rate, sends the changed ATTRIB command to the tag chip module to enable the tag chip module to enter the high communication rate state, and enters the corresponding high communication rate state according to the changed ATTRIB command in a self-configuration mode, for example, the communication rates of the reader-writer module and the tag communication module are changed into 212kbps or 424kbps or 848kbps and the like, and meanwhile, the current value of the register is updated.

If the reader-writer module judges that the tag chip module can not support high communication rate and conform to the ISO/IEC14443-3 protocol at the same time, the communication fails; or when the reader-writer module fails to set the high communication rate through the ATTRIB command, the communication failure is also determined.

743. And sending a random number command to the tag chip module by using the high communication rate, generating a receiving interrupt after receiving a random number replied by the tag chip module at a corresponding high communication rate, reversely triggering the test module to read the current value of the register, and determining that the data communication flow is successfully verified according to the current value.

After the rate configuration in 742 is completed, the reader-writer module sends a random number command to the tag chip module by using the determined high communication rate, and after receiving a random number replied by the tag chip module at a corresponding high communication rate, generates a receiving interrupt to reversely trigger the test module to read the current value of the register and determines that the data communication flow verification is successful according to the current value; and if the reader-writer module fails to successfully receive the random number replied by the tag chip module at the corresponding high communication rate, the communication fails.

In the whole process, after the reader-writer module receives the random number replied by the tag chip module, the communication flow of the reader-writer module and the tag chip module conforming to the ISO14443TYPEB protocol is successfully verified at one time. In the verification process, the process is the same as the process of verifying the ISO14443TYPEA communication protocol, and the reader-writer module and the tag chip module can be in different protocol communication processes and communication rates by changing the configuration of the initial value of the register in the reader-writer module, so that whether the design function of the communication protocol of the part can be realized can be quickly verified.

According to the RFID reader software verification method provided by the present invention, fig. 7 is a schematic flow chart of a corresponding protocol communication flow being an ISO15693 protocol communication flow, and as shown in fig. 7, when the corresponding protocol communication flow is the ISO15693 protocol communication flow, on the basis of the embodiment shown in fig. 4, correspondingly, the

steps

530 and 540 specifically include (the step 530 specifically includes the step 831, and the step 540 specifically includes the step 841 and 843):

831. According to the clock excitation signal and the initial value of the register, the reader module configures the command communication rate of the reader module and sends an INVENTRY command to the tag chip module;

according to the clock excitation signal of 27.12Mhz and the preset initial value of the register, the reader module configures the command communication rate of itself, or the test module configures the sending rate and the receiving rate of the command communication rate of the reader module. The reader module sends an INVENTROY command to the tag chip module. Wherein, the two sending rate modes of the reader-writer module are a 1-in-4 mode and a 1-in-256 mode; the receiving rate is a double-subcarrier low-speed 6.67kbps, high-speed 26.69kbps or single-subcarrier low-speed 6.62kbps, high-speed 26.48kbps and fast inventoryread mode, and the communication rate required by the communication flow of the ISO15693 protocol is configured from the modes.

841. Configuring a response rate of a tag chip module according to the INVENTRY command, and determining a communication rate mode and a single-double load wave adopted by the tag chip module according to first to second bits in a first byte request mark of the INVENTRY command;

the tag chip module configures the response rate of the tag chip module according to the INVENTORY command, and determines a communication rate mode and a single-double load wave adopted by the tag chip module according to first to second bits in a first byte request mark of the INVENTORY command. Specifically, the 1 st bit and the 2 nd bit in the 1 st byte request flag of the inventantory command respectively determine the mode and the speed adopted by the tag chip module in response, and the single-double load wave and the high-low speed conditions.

842. If the UID response frame command replied by the tag chip module is not received, the INVENTORY command is retransmitted to carry out time slot anti-collision processing;

and if the reader-writer module does not receive the UID response frame command replied by the label chip module, performing error reporting (EOF) (15), and simultaneously retransmitting the INVENTROY command by the reader-writer module to perform time slot anti-collision processing.

843. And directly receiving or receiving a UID response frame command replied by the tag chip module after the time slot anti-collision processing is finished, performing read-write operation on the tag chip module according to the UID response frame command to obtain card internal information in the tag chip module, and generating receiving interruption to reversely trigger the test module to read the current value of the register and determine that the data communication flow is successfully verified according to the current value.

The reader-writer module directly receives or receives a UID response frame command (8-byte UID) replied by the tag chip module after the time slot anti-collision processing is finished, the test module controls the reader-writer module to read, write and block and the like on the tag chip module according to the UID response frame command so as to obtain card internal information in the tag chip module, such as an internal information command, an internal silence command and the like, and meanwhile, the reader-writer module generates receiving interruption so as to reversely trigger the test module to read the current value of the register and determine that the data communication flow is successfully verified according to the current value.

Through the whole processing flow, functions such as protocol communication flow and communication rate of the ISO15693 can be fully tested and verified.

Fig. 8 is a schematic structural diagram of the electronic device provided in the present invention, and as shown in fig. 8, the electronic device may include: a processor (processor)810, a communication Interface 820, a memory 830 and a communication bus 840, wherein the processor 810, the communication Interface 820 and the memory 830 communicate with each other via the communication bus 840. The processor 810 may call logic instructions in the memory 830 to perform the steps of the RFID reader software authentication method, which includes:

In addition, the logic instructions in the memory 830 may be implemented in software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the RFID reader software authentication method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

In another aspect, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, when the program instructions are executed by a computer, the computer being capable of executing the steps of the RFID reader software authentication method provided in the above embodiments, the method including:

In yet another aspect, the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, the computer program, when being executed by a processor, implementing the steps of the RFID reader software authentication method according to the above embodiments, the method including:

The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. Based on such understanding, the above technical solutions may be essentially or partially implemented in the form of software products, which may be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and include instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the index monitoring method according to the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. An RFID reader software verification device, comprising:

the reader-writer module comprises a register, a control unit, a command request unit and an interrupt unit, wherein the control unit is used for configuring an initial value of the register according to the register configuration signal; the command request unit is used for sending a request command in a corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial register value; the interrupt unit is used for generating receiving interrupt after receiving a response frame command replied by the tag chip module so as to reversely trigger the test module to read the current value of the register and complete data communication flow verification according to the current value;

the tag chip module is used for generating a response frame command according to the corresponding protocol communication flow and replying the response frame command to the reader-writer module after receiving the request command;

the test module comprises an excitation unit, a configuration unit, at least three protocol interfaces, a bus selection unit and a verification unit, wherein the excitation unit is used for generating a clock excitation signal; the configuration unit is used for generating a register configuration signal; the at least three protocol interfaces are respectively connected with the bus interface of the reader-writer module through a UART protocol bus, an SPI protocol bus and an IIC protocol bus which respectively correspond to the three protocol interfaces; the bus selection unit is used for selecting one protocol bus from the UART protocol bus, the SPI protocol bus and the IIC protocol bus as a protocol bus for transmitting the clock excitation signal and the register configuration signal; the verification unit is used for reading the current value of the register and finishing the verification of the data communication flow according to the current value after the receiving interruption is generated by the reader-writer module;

two single-bit data lines select0 and select1 are arranged between the test module and the reader-writer module and respectively correspond to S1 and S2 of a bus selection unit, the test module changes the values of select0 and select1 in advance based on the clock excitation signal so as to select one protocol bus from the UART protocol bus, the SPI protocol bus and the IIC protocol bus through the values of select0 and select 1; wherein the values of select1 and select0 are 00, which indicates that the SPI bus is selected; a value of 01 indicates that the IIC bus is selected; a value of 10 indicates selection of the UART bus; a value of 11 indicates that the selection is invalid;

the corresponding protocol communication flow is one of a protocol communication flow set matched with the clock excitation signal and the initial register value, and the protocol communication flow set at least comprises any one of an ISO14443TYPEA protocol communication flow, an ISO14443TYPEB protocol communication flow and an ISO15693 protocol communication flow; and the ISO14443TYPEA protocol communication flow, the ISO14443TYPEB protocol communication flow and the ISO15693 protocol communication flow respectively have a plurality of communication modes with different communication speed.

2. A software verification method for an RFID reader-writer is characterized by comprising the following steps:

acquiring a clock excitation signal and a register configuration signal generated by a test module through a protocol bus;

configuring initial values of registers according to the register configuration signals through a control unit;

sending a request command in a corresponding protocol communication flow to a tag chip module through a command request unit according to the clock excitation signal and the initial register value;

receiving a response frame command replied by the tag chip module according to the request command and the corresponding protocol communication flow through an interrupt unit, generating a receiving interrupt to reversely trigger the test module to read the current value of the register and complete data communication flow verification according to the current value;

the test module generates a clock excitation signal through an excitation unit; the test module generates a register configuration signal through a configuration unit; the test module transmits the clock excitation signal and the register configuration signal through a UART protocol bus, an SPI protocol bus and an IIC protocol bus which are respectively corresponding to at least three protocol interfaces; the test module selects one protocol bus from the UART protocol bus, the SPI protocol bus and the IIC protocol bus through a bus selection unit to serve as the protocol bus for transmitting the clock excitation signal and the register configuration signal; after the read-write module generates a receiving interruption through the verification unit, the test module reads the current value of the register and completes data communication flow verification according to the current value;

two single-bit data lines select0 and select1 are arranged between the test module and the reader-writer module and respectively correspond to S1 and S2 of the bus selection unit, and the test module also changes the values of select0 and select1 in advance based on the clock excitation signal so as to select one protocol bus from the UART protocol bus, the SPI protocol bus and the IIC protocol bus according to the values; wherein the values of select1 and select0 are 00, which indicates that the SPI bus is selected; a value of 01 indicates that the IIC bus is selected; a value of 10 indicates selection of the UART bus; a value of 11 indicates that the selection is invalid;

3. The RFID reader software validation method according to claim 2, wherein when the corresponding protocol communication flow is an ISO14443TYPEA protocol communication flow, correspondingly, the sending a request command in the corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial register value and the receiving a response frame command replied by the tag chip module according to the request command and the corresponding protocol communication flow generate a receiving interrupt to reversely trigger the testing module to read the current register value and complete data communication flow validation according to the current value, specifically comprising:

4. The RFID reader software validation method according to claim 2, wherein when the corresponding protocol communication flow is an ISO14443TYPEB protocol communication flow, correspondingly, the sending a request command in the corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial register value and the receiving a response frame command replied by the tag chip module according to the request command and the corresponding protocol communication flow generate a receiving interrupt to reversely trigger the testing module to read the current register value and complete data communication flow validation according to the current value, specifically comprising:

5. The RFID reader/writer software verification method according to claim 2, wherein when the corresponding protocol communication flow is an ISO15693 protocol communication flow, correspondingly, the sending a request command in the corresponding protocol communication flow to the tag chip module according to the clock excitation signal and the initial register value and the receiving a response frame command replied by the tag chip module according to the request command and the corresponding protocol communication flow, generating a reception interrupt to reversely trigger the test module to read the current register value and complete data communication flow verification according to the current value, specifically comprising:

6. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the RFID reader software authentication method according to any one of claims 2 to 5 when executing the computer program.

7. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the RFID reader software authentication method according to any one of claims 2 to 5.