CN112699588A - Thermoelectric coupling modeling method for power semiconductor chip unit cell - Google Patents

Thermoelectric coupling modeling method for power semiconductor chip unit cell Download PDF

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CN112699588A
CN112699588A CN202110025236.0A CN202110025236A CN112699588A CN 112699588 A CN112699588 A CN 112699588A CN 202110025236 A CN202110025236 A CN 202110025236A CN 112699588 A CN112699588 A CN 112699588A
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李武华
陈宇
吴强
周宇
罗皓泽
何湘宁
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Abstract

The invention discloses a thermoelectric coupling modeling method of power semiconductor chip unit cells, which comprises the following steps: s1, dividing the power semiconductor chip into a multi-cell structure; s2, extracting a voltage-current-temperature three-dimensional model of the chip; s3, extracting a voltage-current-temperature three-dimensional model of the cell; s4, solving the cell current distribution proportion and the corresponding loss under any temperature distribution; s5, generating temperature rise of each cell and superposing to obtain the integral temperature gradient of the chip; s6, repeating the steps S4 and S5 until the temperature gradient deviation converges; and S7, extracting the surface temperature peak values of the chips under different working conditions, and calculating the corresponding thermal resistance of the power module. The invention realizes the thermoelectric coupling modeling and calculation of the power semiconductor chip unit cell by combining the chip lumped Fourier series analysis thermal model and the multi-unit cell distributed electrical model. In addition, the method has the advantages of small required calculation amount, short solving time and no convergence problem, and is particularly suitable for the online prediction of the temperature of the power semiconductor chip.

Description

Thermoelectric coupling modeling method for power semiconductor chip unit cell
Technical Field
The invention belongs to the field of power electronic devices, and particularly relates to a thermoelectric coupling modeling method for power semiconductor chip cells.
Background
The power module is widely applied to a new energy automobile power assembly system. The high power density and high integration trend aggravate the temperature gradient on the surface of the chip, and the electrical parameters of the unit cells have a temperature variation effect, so that the chip forms the characteristic of uneven current density distribution. Due to the fact that the semiconductor chip runs in an overcurrent mode under the extreme working conditions of low-speed large torque, heavy-load stator locked rotor, starting acceleration and the like of the automobile, cellular current is distributed unevenly more seriously, the on-chip temperature field forming mechanism is not clear, and hidden dangers are brought to safe running of the power module. Therefore, modeling and analyzing the on-chip electro-thermal field of the power module is particularly urgent.
The traditional experimental method is mainly divided into a direct measurement method and an indirect measurement method. The direct measurement method mainly utilizes infrared thermal imaging or grating fibers, and needs complex operations such as uncovering, disassembling, glue removing, paint spraying and the like on a power module, so that the direct measurement method is only suitable for off-line measurement. The indirect measurement method mainly utilizes thermosensitive electrical parameters to realize online measurement, but the indirect method can only obtain the average temperature of the chip and cannot obtain the surface temperature distribution of the chip, and when the average temperature of the chip is normal and is locally overheated, the detection is difficult, so that hidden dangers are brought to the operation of the new energy automobile under special working conditions.
Therefore, in order to accurately predict the surface temperature of the chip, scholars at home and abroad mainly adopt a finite element method and rely on foreign commercial software such as COMSOL, ANSYS and the like in a large quantity. However, the finite element simulation software adopts ohm's law for solving the thermoelectric coupling effect, that is, the solving object is required to be pure resistance characteristic, the electrical characteristic of the power semiconductor chip is essentially different from pure resistance, and the conductivity of the chip is also greatly different from that of silicon material, so that the finite element simulation software has limitations in solving and calculating the electrical characteristic problem of the semiconductor chip. In addition, under the actual application working condition, the application environment of the power semiconductor chip is complex, the external working conditions such as voltage, current and the like are in a severe change state, and the finite element commercial software cannot cope with the accurate characterization of the electrical characteristics of the chip under the continuous change of the current, so that the accuracy of predicting the chip electric field is greatly poor.
In view of the above, the invention is based on the characteristic that the Fourier series is easy to fuse various circuit equations compared with the finite element method, and realizes the thermoelectric coupling modeling and calculation of the power semiconductor chip cells by combining the chip lumped Fourier series analysis thermal model and the multi-cell distributed electrical model. In addition, the Fourier series algorithm only carries out polynomial summation operation and is different from a finite element method for solving partial differential equations, so that the method has the advantages of small required calculated amount, short solving time and no convergence problem, and is particularly suitable for online prediction of the temperature of the power semiconductor chip.
Disclosure of Invention
In summary, the chip lumped Fourier series analysis thermal model and the multi-cell distributed electrical model are combined, and thermoelectric coupling modeling and calculation of the power semiconductor chip cells are achieved.
The invention provides a thermoelectric coupling modeling method of power semiconductor chip unit cells, which specifically comprises the following steps:
s1, dividing the power semiconductor chip into a multi-cell structure based on the chip metal layer and the bonding wire layout characteristics;
s2, extracting chip lumped parameters, and establishing a voltage-current-temperature three-dimensional model of the power semiconductor chip by adopting a least square algorithm;
s3, converting the chip lumped parameters into cell distribution parameters according to the characteristics of the multi-cell parallel circuit, and establishing a voltage-current-temperature three-dimensional model of the power semiconductor cells;
s4, solving the cell current distribution proportion and the corresponding loss under any temperature distribution by using a three-dimensional voltage-current-temperature model of the cell and adopting a mathematical interpolation algorithm;
s5, linearly superposing two-dimensional temperature distribution fields formed by cell loss to obtain the integral temperature gradient of the chip;
s6, judging that the integral temperature gradient deviation of the chip is smaller than a certain preset value, considering convergence, otherwise, repeating the steps S4 and S5 until convergence is reached, wherein the obtained temperature distribution is the thermoelectric coupling interaction result of the power semiconductor chip unit cells;
and S7, extracting the integral temperature gradient of the chip under different currents, and calculating the thermal resistance of the power module where the chip is located under the corresponding current.
According to a preferred embodiment of the present invention, the power semiconductor chip dividing process in step S1 specifically includes: firstly, eliminating the structure of chip insulation voltage-resistant ring, gate region and gate electrode bonding wire, selecting chip active region as the region to be divided, and dividing the chip active region into N regions longitudinally according to the number of chip metal layersyA plurality of portions; then dividing according to the bonding wire landing position, wherein one landing position corresponds to one cell, and dividing into N according to the number of bonding wiresxA plurality of portions; final chip can be divided into Nx*NyA matrix multi-cell structure.
According to a preferred embodiment of the present invention, in step S2, a three-dimensional voltage-current-temperature model of the power semiconductor chip is obtained by a least squares algorithm, and the expression form is as follows:
Figure BDA0002890104040000021
wherein, VCEsatIs the saturated on-state voltage drop of the power semiconductor chip, Vce0Is the bias voltage of the power semiconductor chip, r0Is a dynamic resistance of a power semiconductor chip, IchipFor collecting current, T, of power semiconductor chipsjTo illustrate the temperature of the power semiconductor chip, A, B is a pending constant related to temperature and C is a pending constant related to current.
According to a preferred embodiment of the present invention, the voltage-current-temperature three-dimensional model of the power semiconductor unit cell in step S3 is extracted based on the voltage-current-temperature three-dimensional model of the power semiconductor chip according to the characteristics of the multi-unit cell parallel circuit, and the expression is as follows:
VCEsat(Icell_i,Tcell_i)＝ATcell_i+Vce0+(BTcell_i+r0)(NxNyIcell_i)C
wherein, Icell_iIs the current of the power semiconductor cell i, Tcell_iIs the temperature of the power semiconductor cell i.
According to a preferred embodiment of the present invention, the cellular current distribution ratio and the corresponding loss solving process under any temperature distribution in step S4 are as follows: firstly, converting a voltage-current-temperature three-dimensional model of a power semiconductor unit cell into a current-voltage-temperature model, and enabling the expression to be as follows:
Figure BDA0002890104040000031
then for any temperature distribution, the power semiconductor chip current I can be obtainedchipThe solving expression form of the following cellular current and corresponding loss distribution is as follows:
Figure BDA0002890104040000032
Pcell_i＝Icell_iVCEsat
wherein, Pcell_iIs the loss of the power semiconductor cell i.
According to a preferred embodiment of the present invention, the step S5 specifically includes: by using a fast Fourier series algorithm, the coordinate can be obtained as (X)ci,Yci) Temperature rise delta T of the power semiconductor cell icell_iThe solving expression form is as follows:
Figure BDA0002890104040000033
wherein, Wcell、LcellRespectively the width and length of the power semiconductor unit cell, m and n respectively are Fourier series terms, Am、BnRespectively, undetermined coefficients, DeltaT, associated with m, ncell_i(x, y) is the temperature rise caused by the power semiconductor unit cell i at the coordinate (x, y);
temperature rise delta T formed by each power semiconductor unit cellcell_iAnd (x, y) linearly superposing to obtain the integral temperature gradient of the chip, wherein the solving expression form is as follows:
Figure BDA0002890104040000034
wherein, TaIs ambient temperature, Tj(x, y) is the temperature of the power semiconductor chip at the (x, y) coordinate.
According to the preferred embodiment of the present invention, in the whole chip temperature gradient deviation calculating process in step S6, the whole chip is first calculated based on the ambient temperature TaForming an initial forward conduction voltage drop VCEsat (0)Heat loss P thus generated(0)Forming a temperature field distribution T on the surface of the chipj (0)(x, y); then each cell of the chip (X)ci,Yci) Based on the local temperature Tj (0)(Xci,Yci) Form a new chip conduction voltage drop VCEsat (1)Local heat loss P generated from each cellcell_i (1)Temperature rise Δ T formedcell_i (1)Linear superposition of (x, y) to form new temperature field distribution Tj (1)(x, y) and VCEsat (2)(ii) a Iterating with the process, and repeating the steps S4 and S5 until V is obtained after the k-th iterationCEsat (k+1)Deviation is less than a specific preset value, Tj (k)(x, y) is the chip temperature field result after thermoelectric interaction of the power semiconductor chip unit cells; mathematic table adopted in k-th iteration processThe expression is as follows:
Figure BDA0002890104040000041
Figure BDA0002890104040000042
Figure BDA0002890104040000043
Figure BDA0002890104040000044
Figure BDA0002890104040000045
wherein, Pcell_i (k)Is the loss of the power semiconductor cell I at the kth iteration, Icell_i (k)、Icell_i (k+1)The current, V, of the power semiconductor cell i at the kth and (k +1) th iterations, respectivelyCEsat (k)、VCEsat (k+1)The voltage drop of saturated on-state formed by all the power semiconductor unit cells in parallel connection at the k-th iteration and the (k +1) -th iteration respectivelycell_i (k)(x, y) is the temperature rise caused by the power semiconductor cell i at the coordinates (x, y) at the kth iteration, Am (k)、Bn (k)Respectively undetermined coefficients related to m and n at the k iteration, Tj (k)(x, y) is the temperature of the power semiconductor chip at the (x, y) coordinate at the kth iteration, Tcell_i (k)Is the temperature of the power semiconductor cell i at the kth iteration.
According to the preferred embodiment of the present invention, the chip surface temperature peak value T in the step S7jmaxFor calculating the corresponding power module thermal resistance peak value Rth_jmaxCorresponding solving expressionsThe following were used:
Rth_jmax＝(Tjmax-Ta)/(IchipVCEsat)。
the invention realizes the modeling and calculation of the chip temperature considering the electrical characteristics of the power semiconductor, and is particularly suitable for the online prediction of the power semiconductor chip temperature.
Based on the technical scheme, the invention has the following beneficial technical effects:
(1) according to the invention, the chip lumped type thermal model and the multi-element distributed type electrical model are combined, so that the accurate characterization of the electrical characteristics of the chip under the continuous change of the current is realized, the accuracy of the modeling of the chip electroluminescence temperature field is effectively improved, and the defect that the electrical characteristics of the semiconductor chip are difficult to be accounted by the conventional finite element software is overcome.
(2) The Fourier series algorithm adopted by the invention only carries out polynomial summation operation, is different from a finite element method for solving partial differential equations, has the advantages of small calculated amount, short solving time, high response speed and no convergence problem, and can realize the online prediction of the temperature of the power semiconductor chip.
Drawings
FIG. 1 is a schematic diagram of a multi-cell structure of a chip;
FIG. 2 is a cross-sectional view of a power semiconductor chip;
FIG. 3 is a graph comparing the SEMiX603GB12E4p chip turn-on model with the experiment;
fig. 4 is a package structure diagram of a power module semi x603GB12E4 p;
FIG. 5 is a flow chart of a multi-cell electro-thermal iteration;
FIG. 6 is a graph of the current density distribution of the chip at 20A;
FIG. 7 is a graph of the current density distribution of the chip at current 150A;
FIG. 8 is an experimental electrical schematic;
fig. 9 is an infrared thermal imaging diagram when a current of 240A is passed.
Detailed Description
In order to explain the invention in more detail, the invention will be further explained in detail by taking the semex-controlled power semiconductor module SEMiX603GB12E4p as an example, with reference to the accompanying drawings.
The invention provides a thermoelectric coupling modeling method of power semiconductor chip unit cells, which comprises the following specific steps:
s1, dividing the power semiconductor chip into a multi-cell structure based on the chip metal layer and the bonding wire layout characteristics;
s2, extracting chip lumped parameters, and establishing a voltage-current-temperature three-dimensional model of the power semiconductor chip by adopting a least square algorithm;
s3, converting the chip lumped parameters into cell distribution parameters according to the characteristics of the multi-cell parallel circuit, and establishing a voltage-current-temperature three-dimensional model of the power semiconductor cells;
s4, solving the cell current distribution proportion and the corresponding loss under any temperature distribution by using a three-dimensional voltage-current-temperature model of the cell and adopting a mathematical interpolation algorithm;
s5, linearly superposing two-dimensional temperature distribution fields formed by cell loss to obtain the integral temperature gradient of the chip;
s6, judging that the integral temperature gradient deviation of the chip is smaller than a certain preset value, considering convergence, otherwise, repeating the steps S4 and S5 until convergence is reached, wherein the obtained temperature distribution is the thermoelectric coupling interaction result of the power semiconductor chip unit cells;
and S7, extracting the integral temperature gradient of the chip under different currents, and calculating the thermal resistance of the power module where the chip is located under the corresponding current.
Step S1, firstly, eliminating the chip insulation pressure ring and gate electrode area structure, selecting the chip active area as the area to be divided, and dividing the chip active area into 4 parts longitudinally according to the number of the chip transverse metal layers; then dividing according to the bonding wire landing position, wherein one landing position corresponds to one cell and can be divided into 11 parts transversely according to the number of the bonding wires; the resulting chips can be divided into 11 x 4 matrix configurations as shown in fig. 1. The chip thickness is 120 μm, which is much smaller than the thickness of the power module, so the on-chip current can be approximated as a surface current, using a two-dimensional discrete method. The total current flowing is IchipEach cell current is sequentially Icell_1、Icell_2、....、Icell_NFormed ofConducting voltage drop of VCEsat。
In step S2, a cross-sectional view of the power semiconductor chip is shown in fig. 2, where PN junctions between the n-drift region and the p-emitter and p-base regions are denoted as J1 and J2, respectively. The on-state saturation voltage drop of a power semiconductor is composed of four parts, which can be expressed as:
VCEsat(JC,Tj)＝VJ1+Vnd+VJ2+Vch
wherein, VJ1Is J1Junction pressure drop, VndIs n-Drift region voltage drop, VJ2Is J2Junction pressure drop, VchFor channel drop, TjIs the device temperature, JCIs the collector current density flowing through the power semiconductor.
Power semiconductor device n-The drift region has approximately equal hole and electron concentration distributions in the large injection state, on the basis of which VJ1、VJ2、VndAnd VchCan be specifically expressed as:
Figure BDA0002890104040000061
Figure BDA0002890104040000062
Figure BDA0002890104040000063
Figure BDA0002890104040000064
Figure BDA0002890104040000065
wherein p is1Is a carrier concentration of around 0, p2Is W ═ WndThe carrier concentration of (A), k is Boltzmann constant, q is the charge coefficient, NfsAnd NndRespectively n-field stop layer and n-Doping concentration of the drift region, niIs the intrinsic carrier concentration, LchIs the channel length, WcellIs the cell pitch, toxIs the thickness of the oxide, muniIs the electron mobility in the channel, epsilonoxIs the dielectric constant of the gate oxide layer, VGEIs the power semiconductor gate voltage, VGEthIs the gate threshold voltage, Jn_driftIs n-Electron drift current density in the drift region, s0Is n-Approximate slope absolute value of drift region carrier concentration distribution, s0≈(p1-p2)/Wnd，μnAnd mupMobility of electrons and holes, respectively, DnIs the diffusion coefficient of the electrons.
From the above formula, the on-chip voltage drop is directly influenced by the junction temperature and the flowing current, and is also indirectly influenced by the temperature sensitive parameters of the device, mainly including the channel electron mobility μniDrift region carrier mobility mun(μp) Gate threshold voltage VGEth. The above relationship of the semex control power module SEMiX603GB12E4p can be expressed as:
Figure BDA0002890104040000071
Figure BDA0002890104040000072
Figure BDA0002890104040000073
VGEth(Tj)＝5.9-9×10-3(Tj-300)
the SEMiX603GB12E4p chip lumped parameter of the Sammi control module is based on a chip data manual, and the voltage-current-temperature three-dimensional model expression form of the chip is as follows:
Figure BDA0002890104040000074
fig. 3 depicts a comparison between the conduction voltage drop model of the chip adopted by the module semi x603GB12E4p and the experimental results, and the mathematical model is consistent with the experimental results and can be used as a basis for studying the conduction voltage drop characteristics of the chip cells. The influence of the temperature on the forward conduction voltage drop of the chip is related to the grade of the injected current, when the chip current is more than 59.1A, the forward conduction voltage drop is increased along with the increase of the temperature and is a positive temperature characteristic zone, and when the chip current is less than 59.1A, the reverse is a negative temperature characteristic zone.
In step S3, a cellular voltage-current-temperature three-dimensional model is extracted according to the characteristics of the multi-cellular parallel circuit, and the expression form is as follows: vCEsat(Icell_i,Tcell_i)＝-0.00232Tcell_i+0.7855+(0.00007656Tcell_i+0.01972)(44Icell_i)0.836
In step S4, the cell current distribution ratio and the corresponding loss are solved under any temperature distribution, and first, the voltage-current-temperature three-dimensional model of the power semiconductor cell is converted into a current-voltage-temperature model, so that the expression is as follows:
Figure BDA0002890104040000075
then for any temperature distribution, the power semiconductor chip current I can be obtainedchipThe solving expression form of the following cellular current and corresponding loss distribution is as follows:
Figure BDA0002890104040000076
Pcell_i＝Icell_iVCEsat
in step S5, the packaging environment of the power module under study is shown in fig. 4, and the power module is a single-phase upper and lower bridge arm structure, i.e., a moduleEach bridge arm is formed by connecting three power semiconductor chips in parallel, the size (length, width and height) of an active area of each chip is 9.7mm, 14.5mm and 120 mu m, the active area is covered by four discrete metal layers, a gate electrode area is positioned on one side of each chip, and an insulated terminal structure is arranged outside the active area. The DBC (Direct Bond coater, Direct Copper clad ceramic substrate) surface size of one arm was 48.8mm 47 mm. The substrate back surface is mounted on a water cooled plate, which can be considered to be maintained at a coolant temperature Ta22 ℃. The material properties, thickness parameters, and chip coordinates are shown in table 1.
TABLE 1 Power Module Structure parameters, Material parameters and chip location
Parameter(s) Numerical value Parameter(s) Numerical value
kc 98.9W/(m·℃) tN 3mm
kcs、k4 55W/(m·℃) Lchip(active region) 9.7mm
k1、k3、kN 380W/(m·℃) Wchip(active region) 14.5mm
k2 24W/(m·℃) LDBC 118.6mm
tc 0.12mm WDBC 58.6mm
tcs 0.12mm (Xc1,Yc1) (70.7,24.0)mm
t1、t3、t4 0.3mm (Xc2,Yc2) (84.5,34.2)mm
t2 0.32mm (Xc3,Yc3) (97.5,34.2)mm
By using a fast Fourier series algorithm, the coordinate can be obtained as (X)ci,Yci) Temperature rise delta T of the power semiconductor cell icell_iThe solving expression form is as follows:
Figure BDA0002890104040000081
wherein m and n are Fourier series terms respectively, Am、BnRespectively, undetermined coefficients, DeltaT, associated with m, ncell_i(x, y) is the temperature rise caused by the power semiconductor unit cell i at the coordinate (x, y);
temperature rise delta T formed by each power semiconductor unit cellcell_iAnd (x, y) linearly superposing to obtain the integral temperature gradient of the chip, wherein the solving expression form is as follows:
Figure BDA0002890104040000082
wherein, Tj(x, y) is the temperature of the power semiconductor chip at the (x, y) coordinate.
In step S6, the entire chip is first determined based on the ambient temperature TaForming an initial forward conduction voltage drop VCEsat (0)Heat loss P thus generated(0)Forming a temperature field distribution T on the surface of the chipj (0)(x, y); then each cell of the chip (X)ci,Yci) Based on the local temperature Tj (0)(Xci,Yci) Form a new chip conduction voltage drop VCEsat (1)Local heat loss P generated from each cellcell_i (1)Temperature rise Δ T formedcell_i (1)Linear superposition of (x, y) to form new temperature field distribution Tj (1)(x, y) and VCEsat (2)(ii) a Iterating with the process, and repeating the steps S4 and S5 until V is obtained after the k-th iterationCEsat (k+1)Deviation is less than a specific preset value, Tj (k)(x, y) is the chip temperature field result after thermoelectric interaction of the power semiconductor chip unit cells; the iterative process is shown in fig. 5, and the mathematical expression adopted by the kth iterative process is as follows:
Figure BDA0002890104040000091
Figure BDA0002890104040000092
Figure BDA0002890104040000093
Figure BDA0002890104040000094
Figure BDA0002890104040000095
wherein, Pcell_i (k)Is the loss of the power semiconductor cell I at the kth iteration, Icell_i (k)、Icell_i (k+1)The current, V, of the power semiconductor cell i at the kth and (k +1) th iterations, respectivelyCEsat (k)、VCEsat (k+1)The voltage drop of saturated on-state formed by all the power semiconductor unit cells in parallel connection at the k-th iteration and the (k +1) -th iteration respectivelycell_i (k)(x, y) is the temperature rise caused by the power semiconductor cell i at the coordinates (x, y) at the kth iteration, Am (k)、Bn (k)Respectively undetermined coefficients related to m and n at the k iteration, Tj (k)(x, y) is the temperature of the power semiconductor chip at the (x, y) coordinate at the kth iteration, Tcell_i (k)Is the temperature of the power semiconductor cell i at the kth iteration.
The modeling results are as follows: taking the module SEMiX603GB12E4p chip as an example, the positive/negative temperature coefficient demarcation current is 59.1A, and FIG. 6 is a current density distribution diagram when 20A current is passed through the chip. When the current is 20A (negative temperature coefficient area), the current of each unit cell is gathered to the middle of the chip. FIG. 7 is a graph of the current density distribution of a chip through a current of 150A. When the current is 150A (positive temperature coefficient area), the current of each unit cell is in an outward expansion skin distribution characteristic.
Chip surface temperature peak value T in step S7jmaxFor calculating the corresponding power module thermal resistance peak value Rth_jmaxThe corresponding solving expression is as follows:
Rth_jmax＝(Tjmax-Ta)/(IchipVCEsat)。
in order to further verify the effectiveness of the method, the power module is arranged on a heat dissipation cold plate, liquid oil in the heat dissipation cold plate is controlled and stabilized through Jumbo PRESTO A80, and the refrigerating power can reach up to 1.2 kW. The upper surface of the power module is measured by a thermal imager with the model number of Fluke Ti450, the shell temperature of the power module is monitored by an optical fiber thermometer Opsens 15S0208 and an optical fiber probe OTG-F-10 to ensure constancy, and a voltmeter is used for measuring the voltage at two ends of a signal terminal of the module to extract the collector-emitter voltage. As shown in fig. 8, the driving voltage source provides +15V gate voltage to make the power semiconductor chip in a fully conducting state, and the power current source provides a large dc current for heating the module. After different currents are changed, a thermal imaging temperature map and a semiconductor chip voltage drop value are recorded after the temperature is observed to be stable by a thermal imager. The thermal imaging map results for the upper arm at 240A are shown in fig. 9.
TABLE 2 comparison of experimental and model results table (Upper arm)
Figure BDA0002890104040000101
The results of the experiments are shown in table 2 in comparison with the results of the proposed model. The temperature measuring points are sequentially positioned at the centers of the three chips from left to right, and the position coordinates are substituted into the proposed analytic model to obtain corresponding temperatures which are compared with experimental results. The error results of all temperature measuring points do not exceed 2.50%, and the effectiveness of the modeling method is verified.
The embodiments described above are presented to enable a person having ordinary skill in the art to make and use the invention. It will be readily apparent to those skilled in the art that various modifications to the above-described embodiments may be made, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications to the present invention based on the disclosure of the present invention within the protection scope of the present invention.

Claims (8)

1. A thermoelectric coupling modeling method for power semiconductor chip unit cells is characterized by comprising the following steps:
s1, dividing the power semiconductor chip into a multi-cell structure based on the chip metal layer and the bonding wire layout characteristics;
s2, extracting chip lumped parameters, and establishing a voltage-current-temperature three-dimensional model of the power semiconductor chip by adopting a least square algorithm;
s3, converting the chip lumped parameters into cell distribution parameters according to the characteristics of the multi-cell parallel circuit, and establishing a voltage-current-temperature three-dimensional model of the power semiconductor cells;
s4, solving the cell current distribution proportion and the corresponding loss under any temperature distribution by using a three-dimensional voltage-current-temperature model of the cell and adopting a mathematical interpolation algorithm;
s5, linearly superposing two-dimensional temperature distribution fields formed by cell loss to obtain the integral temperature gradient of the chip;
s6, judging that the integral temperature gradient deviation of the chip is smaller than a certain preset value, considering convergence, otherwise, repeating the steps S4 and S5 until convergence is reached, wherein the obtained temperature distribution is the thermoelectric coupling interaction result of the power semiconductor chip unit cells;
and S7, extracting the integral temperature gradient of the chip under different currents, and calculating the thermal resistance of the power module where the chip is located under the corresponding current.
2. The method of claim 1, wherein the step of performing thermoelectric coupling modeling comprises: the power semiconductor chip dividing process in step S1 specifically includes: firstly, eliminating the structure of chip insulation voltage-resistant ring, gate region and gate electrode bonding wire, selecting chip active region as the region to be divided, and dividing the chip active region into N regions longitudinally according to the number of chip metal layersyA plurality of portions; then according to the bonding wireDividing the positions of the falling points, wherein one position of the falling point corresponds to one cell and can be divided into N according to the number of bonding wiresxA plurality of portions; final chip can be divided into Nx*NyA matrix multi-cell structure.
3. The method of claim 1, wherein the step of performing thermoelectric coupling modeling comprises: in the step S2, a three-dimensional voltage-current-temperature model of the power semiconductor chip is obtained by fitting with a least square algorithm, and the expression form is as follows:
Figure FDA0002890104030000011
wherein, VCEsatIs the saturated on-state voltage drop of the power semiconductor chip, Vce0Is the bias voltage of the power semiconductor chip, r0Is a dynamic resistance of a power semiconductor chip, IchipFor collecting current, T, of power semiconductor chipsjTo illustrate the temperature of the power semiconductor chip, A, B is a pending constant related to temperature and C is a pending constant related to current.
4. The method of claim 1, wherein the step of performing thermoelectric coupling modeling comprises: the voltage-current-temperature three-dimensional model of the power semiconductor unit cell in the step S3 is extracted based on the voltage-current-temperature three-dimensional model of the power semiconductor chip according to the characteristics of the multi-unit cell parallel circuit, and the expression form is as follows:
VCEsat(Icell_i,Tcell_i)＝ATcell_i+Vce0+(BTcell_i+r0)(NxNyIcell_i)C
wherein, Icell_iIs the current of the power semiconductor cell i, Tcell_iIs the temperature of the power semiconductor cell i.
5. The method of claim 4, wherein the step of performing thermoelectric coupling modeling comprises: the cell current distribution proportion and the corresponding loss solving process under any temperature distribution in the step S4 are as follows: firstly, converting a voltage-current-temperature three-dimensional model of a power semiconductor unit cell into a current-voltage-temperature model, and enabling the expression to be as follows:
Figure FDA0002890104030000021
then for any temperature distribution, the power semiconductor chip current I can be obtainedchipThe solving expression form of the following cellular current and corresponding loss distribution is as follows:
Figure FDA0002890104030000022
Pcell_i＝Icell_iVCEsat
wherein, Pcell_iIs the loss of the power semiconductor cell i.
6. The method of claim 1, wherein the step of performing thermoelectric coupling modeling comprises: the step S5 specifically includes: by using a fast Fourier series algorithm, the coordinate can be obtained as (X)ci,Yci) Temperature rise delta T of the power semiconductor cell icell_iThe solving expression form is as follows:
Figure FDA0002890104030000023
wherein, Wcell、LcellRespectively the width and length of the power semiconductor unit cell, m and n respectively are Fourier series terms, Am、BnRespectively, undetermined coefficients, DeltaT, associated with m, ncell_i(x, y) is the temperature rise caused by the power semiconductor unit cell i at the coordinate (x, y);
each power semiconductor unit cellTemperature rise Δ T formedcell_iAnd (x, y) linearly superposing to obtain the integral temperature gradient of the chip, wherein the solving expression form is as follows:
Figure FDA0002890104030000024
wherein, TaIs ambient temperature, Tj(x, y) is the temperature of the power semiconductor chip at the (x, y) coordinate.
7. The method of claim 1, wherein the step of performing thermoelectric coupling modeling comprises: in the whole chip temperature gradient deviation calculating process in step S6, the whole chip is first calculated based on the ambient temperature TaForming an initial forward conduction voltage drop VCEsat (0)Heat loss P thus generated(0)Forming a temperature field distribution T on the surface of the chipj (0)(x, y); then each cell of the chip (X)ci,Yci) Based on the local temperature Tj (0)(Xci,Yci) Form a new chip conduction voltage drop VCEsat (1)Local heat loss P generated from each cellcell_i (1)Temperature rise Δ T formedcell_i (1)Linear superposition of (x, y) to form new temperature field distribution Tj (1)(x, y) and VCEsat (2)(ii) a Iterating with the process, and repeating the steps S4 and S5 until V is obtained after the k-th iterationCEsat (k+1)Deviation is less than a specific preset value, Tj (k)(x, y) is the chip temperature field result after thermoelectric interaction of the power semiconductor chip unit cells; the mathematical expression adopted in the kth iteration process is as follows:
Figure FDA0002890104030000031
Figure FDA0002890104030000032
Figure FDA0002890104030000033
Figure FDA0002890104030000034
Figure FDA0002890104030000035
wherein, Pcell_i (k)Is the loss of the power semiconductor cell I at the kth iteration, Icell_i (k)、Icell_i (k+1)The current, V, of the power semiconductor cell i at the kth and (k +1) th iterations, respectivelyCEsat (k)、VCEsat (k+1)The voltage drop of saturated on-state formed by all the power semiconductor unit cells in parallel connection at the k-th iteration and the (k +1) -th iteration respectivelycell_i (k)(x, y) is the temperature rise caused by the power semiconductor cell i at the coordinates (x, y) at the kth iteration, Am (k)、Bn (k)Respectively undetermined coefficients related to m and n at the k iteration, Tj (k)(x, y) is the temperature of the power semiconductor chip at the (x, y) coordinate at the kth iteration, Tcell_i (k)Is the temperature of the power semiconductor cell i at the kth iteration.
8. The method of claim 1, wherein the step of performing thermoelectric coupling modeling comprises: the peak chip surface temperature T in step S7jmaxFor calculating the corresponding power module thermal resistance peak value Rth_jmaxThe corresponding solving expression is as follows:
Rth_jmax＝(Tjmax-Ta)/(IchipVCEsat)。
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