CN112687737A - Horizontal homojunction bipolar transistor and preparation method thereof - Google Patents
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Abstract
The invention discloses a horizontal homojunction bipolar transistor and a preparation method thereof, belonging to the technical field of microelectronics, and comprising the following steps: p-type doped monocrystalline silicon and SiO2Oxide layer, N-type MoS2Thin film, P-type MoS2A film and an electrode layer; wherein, SiO2The oxide layer is positioned on the upper surface of the P-type doped monocrystalline silicon; n type MoS2Thin film and P-type MoS2The films are all located on SiO2Upper surface of oxide layer, and N-type MoS2Thin film and P-type MoS2The films are transversely connected; the electrode layers are respectively positioned in the N-type MoS2Thin film and P-type MoS2The electrode layers are not connected to each other on the upper surface of the film. N type MoS2Thin film and P-type MoS2All films are MoS2As a carrier, the carrier mobility is high, and the interface state is few, so that the amplification factor of the corresponding horizontal homojunction bipolar transistor is high; in addition, the horizontal homojunction bipolar transistor provided by the invention can set the base region width with extremely small size, and the carrier concentration of the emitter region is far greater than that of the base region, so that the extremely high common emitter amplification factor is realized.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a horizontal homojunction bipolar transistor and a preparation method thereof.
Background
In recent years, two-dimensional transition metal chalcogenides (TMDCs) have attracted much attention because of their excellent optical, acoustic, electrical, mechanical, thermal, and other properties. In MoS2For example, intrinsic MoS2Is an n-type semiconductor with a band gap width varying with the number of layers, a single-layer MoS2Is a direct band gap semiconductor with a forbidden band width of 1.8eV, and is compatible with MoS2The forbidden bandwidth of the increasing layer number is gradually reduced to 1.2 eV. MoS2Has extremely high carrier mobility and single-layer MoS2The carrier mobility can reach 410cm2V-1s-1The mobility of the multilayer carrier is up to 500cm2V-1s-1。
Bipolar transistors (BJTs) are conventional semiconductor devices. The method has considerable application and development prospects in the fields of high speed, high power, analog integrated circuits and the like.
Most of BJTs constructed based on two-dimensional materials at present adopt a heterojunction stacking structure, the structure and the preparation process of the heterojunction BJT are complex, a second material needs to be transferred or grown on a raw material, excessive interface states are easily generated, the process controllability is low, the amplification factor is low, and the performance of a device is influenced. The existing horizontal homojunction bipolar transistor adopts an electric field regulation or solution method doping mode to change the P type and the N type of a semiconductor material, so that the bipolar transistor is formed. The type of a semiconductor material is regulated and controlled by an electric field, the type of the applicable material is few, the regulation and control effect is poor, the operation is complex, and the applied electric field can seriously influence the transmission speed of current carriers in a transistor, so that the amplification factor is reduced. The horizontal homojunction bipolar transistor is prepared by a solution doping method, so that the device is low in reliability, complex in process and poor in repeatability, and is also incompatible with the traditional CMOS process, and the relevant sizes of an emitter region, a base region and a collector region in the bipolar transistor are difficult to specifically control by using the solution doping method, and the specific control of the doping concentrations of different regions of the device is difficult to realize, so that the amplification factor of the device is low.
Disclosure of Invention
In view of the above defects or improvement requirements of the prior art, the present invention provides a horizontal homojunction bipolar transistor and a method for manufacturing the same, which aims to solve the technical problem of low amplification factor of the prior art.
To achieve the above object, in a first aspect, the present invention provides a horizontal homojunction bipolar transistor, comprising: p-type doped monocrystalline silicon and SiO2Oxide layer, N-type MoS2Thin film, P-type MoS2A film and an electrode layer;
wherein, SiO2The oxide layer is positioned on the upper surface of the P-type doped monocrystalline silicon; n type MoS2Thin film and P-type MoS2The films are all located on SiO2Upper surface of oxide layer, and N-type MoS2Thin film and P-type MoS2The films are transversely connected; the electrode layers are respectively positioned in the N typeMoS2Thin film and P-type MoS2The electrode layers are not connected to each other on the upper surface of the film.
Further preferably, SiO2The thickness of the oxide layer is 50nm-100 nm; the thickness of the P-type doped monocrystalline silicon is 350-550 mu m; n type MoS2Thin film and P-type MoS2The thickness of the film is 0.65nm-10 nm.
Further preferably, the MoS N-type2Thin film and P-type MoS2The films are connected through covalent bonds.
Further preferably, the MoS N-type2The film is prepared by adopting a chemical vapor deposition method; p type MoS2The film is prepared by adopting a low-energy ion implantation doping method.
Further preferably, the electrode layer comprises two layers of metal stacked one on top of the other.
Further preferably, the lower metal of the electrode layer is Ti, and the thickness is 5nm-15 nm; the upper layer metal of the electrode layer is Au, and the thickness is 60-100 nm.
In a second aspect, the present invention provides a method for preparing a horizontal homojunction bipolar transistor, comprising the following steps:
s1, selecting SiO on the upper surface2P-type doped monocrystalline silicon of oxide layer as substrate on SiO2Preparation of N-type MoS on oxide layer2Film, obtaining a first sample;
s2, carrying out first ultraviolet photoetching on the surface of the first sample, and developing to obtain partial N-type MoS2The film is exposed, and part of the N-type MoS2A second sample having a film covered with a photoresist;
s3, doping the obtained second sample by adopting a low-energy ion implantation method, and removing the photoresist to obtain a third sample;
s4, carrying out second ultraviolet photoetching on the surface of the third sample, and developing to obtain the MoS with the partial area of N type2The film and partial area are P-type MoS2A fourth sample of film;
and S5, evaporating metal on the surface of the obtained fourth sample to obtain an electrode layer, and removing the photoresist to obtain the horizontal homojunction bipolar transistor.
Further preferably, in step S1, the chemical vapor deposition method is used to deposit SiO2Preparation of N-type MoS on oxide layer2A film.
Further preferably, the uv lithography comprises: spin-coating photoresist, and performing pre-baking, pre-exposure, post-baking and post-exposure operations; in the ultraviolet photoetching process, a spin coater is adopted to rotate at 1500r/min for 10-20 s and then at 4000r/min for 25-35 s, and then photoresist is coated in a spinning mode; the pre-exposure time is 1.4 s-2 s; the pre-drying temperature is 90-100 ℃; the post-baking temperature is 110-120 ℃; the post-exposure time is 14 s-20 s.
Further preferably, in the step S3, during the doping of the obtained second sample by the low-energy ion implantation method, the doping gas is O2The pressure is 3-7 Pa, the doping radio frequency power is 3-10W, and the doping time is 20-40 s.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
1. the invention provides a horizontal homojunction bipolar transistor, which comprises an N-type MoS2Thin film, P-type MoS2Film of MoS2As the carriers, the carrier mobility is high, and the interface state is few, so that the amplification factor of the corresponding horizontal homojunction bipolar transistor is high. In addition, the horizontal homojunction bipolar transistor provided by the invention can set the base region width with extremely small size, and the carrier concentration of the emitter region is far greater than that of the base region, so that the extremely high common emitter amplification factor is realized.
2. In the horizontal homojunction bipolar transistor provided by the invention, N-type MoS2The film is prepared by chemical vapor deposition, and the P-type MoS2 film is prepared by the reaction of N-type MoS2The film is obtained by low-energy ion implantation, and the doping mode of the low-energy ion implantation can realize N-type MoS2The film is effectively, controllably, efficiently and green doped, the doped film is still connected in a covalent bond mode, the carrier mobility is high, and the interface state is few.
3. In the horizontal homojunction bipolar transistor provided by the invention, the electrode layers are two stacked up and downA layer of metal, the lower layer of metal of the electrode layer is Ti, the upper layer of metal of the electrode layer is Au, wherein the Ti metal and the N-type MoS2Thin film and P-type MoS2Ohmic contact is formed on the film, so that contact resistance is reduced; and the Au metal has extremely high conductivity, and simultaneously, the Ti metal is prevented from being oxidized by oxygen in the air, so that the reliability of the device is improved.
4. The horizontal homojunction bipolar transistor provided by the invention has few material types, and avoids the problem of lattice adaptation of different materials; the bipolar transistor adopting the heterojunction stacking structure needs to transfer one material to another material in a directional manner, the transfer process is complex, the efficiency is low, the damage to the material is large, the carrier mobility is reduced, and meanwhile, the situation of material lattice mismatch can be generated, so that the common emitter amplification factor is reduced. The mobility of carriers can be seriously reduced by adopting the vertical homojunction bipolar transistor, so that the common emitter amplification factor is greatly reduced, and meanwhile, the contact position of materials can generate certain wrinkles, which can seriously affect the performance of the device.
5. The invention provides a preparation method of a horizontal homojunction bipolar transistor, which adopts a low-energy ion implantation method, selectively shields a specific region through photoresist, controllably and selectively dopes a MoS2 thin film, selectively dopes N-type MoS2 into P-type MoS2, and the obtained horizontal homojunction bipolar transistor has high carrier mobility, few interface states and high common emitter amplification factor.
6. According to the preparation method of the horizontal homojunction bipolar transistor, the width of the base region with extremely small size can be set by changing related photoetching parameters, so that the width of the base region is far smaller than the diffusion length of minority carriers of the base region, and the composition of the current of an emitting electrode in the base region is greatly reduced; the invention can make the carrier concentration of the emitter region far larger than that of the base region by changing the injection parameters of low-energy ions, and make the forward injection current of the emitter region to the base region far larger than the reverse injection current from the base region to the emitter region, thereby realizing extremely high common emitter amplification factor.
7. The invention provides a preparation method of a horizontal homojunction bipolar transistorBy chemical vapor deposition on SiO2Preparation of N-type MoS on oxide layer2Compared with a mechanical stripping method, the film prepared by the method has larger size, and is more beneficial to the construction of related microelectronic devices.
8. The preparation method of the horizontal homojunction bipolar transistor adopts low-energy ion implantation, has better controllability, more flexible selectivity, greener and more environment-friendly property, has better compatibility with a CMOS (complementary metal oxide semiconductor) process, has less damage to a two-dimensional material and has wide application prospect in the field of microelectronics compared with chemical doping.
9. The preparation method of the horizontal homojunction bipolar transistor provided by the invention adopts an electron beam evaporation method to prepare the contact electrode of the device. Compared with a thermal evaporation method, the prepared electrode layer is more compact, is more closely contacted with the MoS2 material, and is beneficial to improving the amplification factor.
10. According to the preparation method of the horizontal homojunction bipolar transistor, the electrode pattern and the specific shielding region are prepared by adopting an ultraviolet photoetching process, and compared with an electron beam etching process, the preparation method is more economical, higher in preparation efficiency and more beneficial to batch operation.
Drawings
Fig. 1 is a schematic structural diagram of a horizontal homojunction bipolar transistor according to a first aspect of the present invention;
fig. 2 is a process flow chart corresponding to a method for manufacturing a horizontal homojunction bipolar transistor according to a second aspect of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In order to achieve the above object, in a first aspect, the present invention proposes a levelA homojunction bipolar transistor, as shown in fig. 1, includes: p-type doped monocrystalline silicon 1, SiO2Oxide layer 2, N type MoS2Film 3, P-type MoS2A membrane 4 and an electrode layer 5;
wherein, SiO2The oxide layer 2 is positioned on the upper surface of the P-type doped monocrystalline silicon 1; n type MoS2Film 3 and P-type MoS2The thin films 4 are all located on SiO2Upper surface of oxide layer 2, and N-type MoS2Film 3 and P-type MoS2The film 4 is connected transversely; wherein, P type MoS2The film is two-section, N-type MoS2The film is positioned at two sections of P-type MoS2The middle of the film; n type MoS2Film 3 and P-type MoS2Film 4 is coated with SiO2The upper surface of the oxide layer 2; n type MoS2Thin film and P-type MoS2The films are connected through covalent bonds; the electrode layers 5 are respectively positioned in the N-type MoS2Film 3 and P-type MoS2The electrode layers are not connected to each other on the upper surface of the film 4.
Preferably, the electrode layer comprises two layers of metal stacked one on top of the other. The lower layer metal 51 of the electrode layer is Ti, and the thickness is 5nm-15 nm; the upper metal 52 of the electrode layer is Au, and the thickness is 60-100 nm. Specifically, the electrode layers are respectively a Ti/Au emitter electrode, a Ti/Au base electrode and a Ti/Au collector electrode; wherein, the Ti/Au emitter electrode is positioned at one section of P-type MoS2The upper surface of the film and the Ti/Au collecting electrode are positioned at the other section of the P-type MoS2An upper surface of the film; Ti/Au base electrode positioned in N-type MoS2An upper surface of the film; and the Ti/Au emitter electrode, the Ti/Au base electrode and the Ti/Au collector electrode are not in contact with each other.
Preferably, SiO2The thickness of the oxide layer is 50nm-100 nm; the thickness of the P-type doped monocrystalline silicon is 350-550 mu m; n type MoS2Thin film and P-type MoS2The thickness of the film is 0.65nm-10 nm. In particular, an N-type MoS2The film can be prepared by adopting a chemical vapor deposition method; p type MoS2The film can be prepared by adopting a low-energy ion implantation doping method.
In a second aspect, the present invention provides a method for manufacturing the above-mentioned horizontal homojunction bipolar transistor, and a corresponding process flow diagram is shown in fig. 2, and includes the following steps:
s1, selecting SiO on the upper surface2P-type doped monocrystalline silicon of oxide layer as substrate on SiO2Preparation of N-type MoS on oxide layer2Film, obtaining a first sample;
specifically, in this embodiment, the surface has SiO2P-type doped monocrystalline silicon (thickness of 350 μm) with an oxide layer (thickness of 50nm) as a substrate was subjected to ultrasonic treatment with acetone for 5min to remove organic impurities on the surface. And then ultrasonically treating the mixture for 5min by using ethanol to remove the acetone on the surface of the mixture. Then, the mixture is subjected to ultrasonic treatment for 5min by using deionized water, and ethanol on the surface of the mixture is removed. And finally, removing the deionized water on the surface of the glass by using a nitrogen gun. Wherein the size of the monocrystalline silicon is 20mm × 30 mm. And additionally cutting a molybdenum sheet with the size of (8-12) mm multiplied by 30 mm. And (4) polishing the surface of the steel plate by using water-grinding abrasive paper to remove an oxide layer on the surface of the steel plate. The surface of the glass is ultrasonically treated for 5min by using acetone, and organic impurities on the surface of the glass are removed. And then ultrasonically treating the mixture for 5min by using ethanol to remove the acetone on the surface of the mixture. Then, the mixture is subjected to ultrasonic treatment for 5min by using deionized water, and ethanol on the surface of the mixture is removed. And finally, removing the deionized water on the surface of the glass by using a nitrogen gun. Then, chemical vapor deposition is adopted to deposit on SiO2Preparation of N-type MoS on oxide layer2The film specifically comprises: two identical quartz boats are sequentially cleaned and dried by acetone, ethanol and deionized water, and are respectively numbered as a first quartz boat and a second quartz boat, and the inner diameters of the quartz boats are 33 mm. High-purity sulfur powder with a certain length is laid in the first quartz boat, the treated molybdenum sheet is placed in the second quartz boat, and high-purity MoO is uniformly laid on the molybdenum sheet3And (4) powder, and inversing the P-type doped monocrystalline silicon on the molybdenum sheet. The tube furnace used by the chemical vapor deposition method is provided with two temperature areas with controllable temperature rising curves in front of and behind, wherein the front temperature area is close to the air inlet, and the rear temperature area is close to the air outlet. The first quartz boat is placed in the front temperature area, and the second quartz boat is placed in the rear temperature area. And continuously introducing Ar gas with a fixed flow rate into the tubular furnace to ensure that the tubular furnace is in Ar gas atmosphere. Setting a temperature curve to ensure that when the front temperature zone reaches 130-170 ℃, the rear temperature zone reaches 790-830 ℃, maintaining the respective temperature for 5-30 min, naturally cooling to room temperature, and growing N-type MoS on the inverted silicon wafer2Film(s)And obtaining a first sample, as shown in the step (r) in fig. 2. Wherein the Ar gas flow rate is 40-80 sccm; the mass of the MoO3 is 2-6 mg, and the mass of the sulfur powder is 300-1100 mg.
S2, carrying out first ultraviolet photoetching on the surface of the first sample, and developing to obtain partial N-type MoS2The film is exposed, and part of the N-type MoS2A second sample having a film covered with a photoresist;
specifically, the ultraviolet lithography includes: spin-coating photoresist, and performing pre-baking, pre-exposure, post-baking and post-exposure operations; in the ultraviolet photoetching process, a spin coater is adopted to rotate at 1500r/min for 10-20 s and then at 4000r/min for 25-35 s, and then photoresist is coated in a spinning mode; the pre-exposure time is 1.4 s-2 s; the pre-drying temperature is 90-100 ℃; the post-baking temperature is 110-120 ℃; the post-exposure time is 14 s-20 s. In the developing operation, the ratio of the developing solution to the water is 1: 4; the treatment time is 40-50 s, and then the cleaning is carried out in water for 10-20 s.
In this embodiment, the first sample obtained by the chemical vapor deposition is placed on a spin coater, and the spin speed of the spin coater is set to 1500r/min for 15s, and 4000r/min for 30 s. Then placed on a hot plate and heated at 97 ℃ for 2 min. And photoetching the silicon wafer by using an MA-8 photoetching machine for 1.5s, then placing the silicon wafer on a hot plate, heating the silicon wafer at 115 ℃ for 2min, and then carrying out exposure again for 15 s. Placing the exposed silicon wafer in a mixed solution of a developing solution and water in a ratio of 1:4, placing for 45s, then placing in clear water for cleaning for 15s, finally blowing and drying by using a nitrogen gun, and partially blowing N-type MoS2The film is exposed, and part of the N-type MoS2The second sample, with the film covered by photoresist, is shown in step 2.
S3, doping the obtained second sample by adopting a low-energy ion implantation method, and removing the photoresist to obtain a third sample;
specifically, the doping gas may be O2Or N2. In the present embodiment, the doping gas is preferably O2The pressure is 3-7 Pa, the doping radio frequency power is 3-10W, and the doping time is 20-40 s. In particular, the second sample is doped using low energy ion implantation. Under high vacuum, 60sccm oxygen gas is introduced and the pressure is set to 5pa, turning on a radio frequency power supply, quickly adjusting the power to a set power after glow starting, placing the low-energy ions into an acetone and isopropanol solution after doping for a certain time, removing the photoresist, finally cleaning the photoresist by using deionized water and blowing the deionized water by using a nitrogen gun to obtain a third sample, wherein the third sample is shown in the step III in the figure 2.
S4, carrying out second ultraviolet photoetching on the surface of the third sample, and developing to obtain the MoS with the partial area of N type2The film and partial area are P-type MoS2A fourth sample of film;
specifically, like step S2, the uv lithography includes: spin-coating photoresist, and performing pre-baking, pre-exposure, post-baking and post-exposure operations; in the ultraviolet photoetching process, a spin coater is adopted to rotate at 1500r/min for 10-20 s and then at 4000r/min for 25-35 s, and then photoresist is coated in a spinning mode; the pre-exposure time is 1.4 s-2 s; the pre-drying temperature is 90-100 ℃; the post-baking temperature is 110-120 ℃; the post-exposure time is 14 s-20 s.
In the embodiment, the third sample is placed on the spin coater, and the rotation speed of the spin coater is set to be 1500r/min for 15s, and 4000r/min for 30 s. Then placed on a hot plate and heated at 97 ℃ for 2 min. And photoetching the silicon wafer by using an MA-8 photoetching machine for 1.5s, then placing the silicon wafer on a hot plate, heating the silicon wafer at 115 ℃ for 2min, and then carrying out exposure again for 15 s. Placing the exposed silicon wafer in a mixed solution of a developing solution and water in a ratio of 1:4, placing for 45s, then placing in clear water for cleaning for 15s, and finally drying by using a nitrogen gun to obtain N-type MoS with partial area2The film and partial area are P-type MoS2The fourth sample of film, as shown by step (c) in fig. 2.
And S5, evaporating metal on the surface of the obtained fourth sample to obtain an electrode layer, and removing the photoresist to obtain the horizontal homojunction bipolar transistor.
Specifically, a Ti/Au electrode is evaporated on the fourth sample by using electron beam evaporation; in this embodiment, the thickness of Ti is 10nm, the thickness of Au is 80nm, as shown in step (sixty) in fig. 2, the obtained sample is placed in acetone and isopropanol solution in sequence, the photoresist is removed, and finally, deionized water is washed by deionized water and blown away by a nitrogen gun to obtain a horizontal homojunction bipolar transistor, as shown in step (seventy) in fig. 2.
Thus, the fabrication of the horizontal homojunction bipolar transistor is completed.
The technology for fabricating the horizontal homojunction bipolar transistor provided by the present invention will now be described in further detail with the help of specific examples:
examples 1,
A preparation method of a horizontal homojunction bipolar transistor comprises the following steps:
s1, selecting SiO on the upper surface2P-type doped monocrystalline silicon of oxide layer as substrate on SiO2Preparation of N-type MoS on oxide layer2Film, obtaining a first sample;
s2, carrying out first ultraviolet photoetching on the surface of the first sample, and developing to obtain partial N-type MoS2The film is exposed, and part of the N-type MoS2A second sample having a film covered with a photoresist;
s3, doping the obtained second sample by adopting a low-energy ion implantation method, and removing the photoresist to obtain a third sample;
s4, carrying out second ultraviolet photoetching on the surface of the third sample, and developing to obtain the MoS with the partial area of N type2The film and partial area are P-type MoS2A fourth sample of film;
and S5, evaporating metal on the surface of the obtained fourth sample to obtain an electrode layer, and removing the photoresist to obtain the horizontal homojunction bipolar transistor.
The specific operation process of this embodiment is similar to the specific operation process of the method for preparing a horizontal homojunction bipolar transistor provided in the second aspect (the same parts are not described in detail), except that the embodiment adopts a chemical vapor deposition method to form a SiO layer on the silicon oxide layer2Preparation of N-type MoS on oxide layer2When in film forming, a molybdenum sheet with the size of 10mm multiplied by 30mm is adopted; setting a temperature curve, so that when the front temperature zone reaches 170 ℃, the rear temperature zone reaches 830 ℃, maintaining the respective temperatures for 15min, naturally cooling to room temperature, and growing an N-type MoS2 film on the inverted silicon wafer to obtain a first sample, wherein the Ar gas flow rate is 60 sccm; MoO3Mass of6mg, the mass of the sulfur powder is 800 mg. In addition, when the second sample is doped by using a low-energy ion implantation method, in this embodiment, under high vacuum, oxygen is introduced and the pressure is set to 5pa, the radio frequency power supply is turned on, the power is rapidly adjusted to 3W after starting, and the low-energy ion implantation is performed for doping for 30 s.
Examples 2,
A preparation method of a horizontal homojunction bipolar transistor comprises the following steps:
s1, selecting SiO on the upper surface2P-type doped monocrystalline silicon of oxide layer as substrate on SiO2Preparation of N-type MoS on oxide layer2Film, obtaining a first sample;
s2, carrying out first ultraviolet photoetching on the surface of the first sample, and developing to obtain partial N-type MoS2The film is exposed, and part of the N-type MoS2A second sample having a film covered with a photoresist;
s3, doping the obtained second sample by adopting a low-energy ion implantation method, and removing the photoresist to obtain a third sample;
s4, carrying out second ultraviolet photoetching on the surface of the third sample, and developing to obtain the MoS with the partial area of N type2The film and partial area are P-type MoS2A fourth sample of film;
and S5, evaporating metal on the surface of the obtained fourth sample to obtain an electrode layer, and removing the photoresist to obtain the horizontal homojunction bipolar transistor.
The specific operation process of this embodiment is similar to the specific operation process of the method for preparing a horizontal homojunction bipolar transistor provided in the second aspect (the same parts are not described in detail), except that the embodiment adopts a chemical vapor deposition method to form a SiO layer on the silicon oxide layer2Preparation of N-type MoS on oxide layer2When in film forming, a molybdenum sheet with the size of 12mm multiplied by 30mm is adopted; setting a temperature curve, so that when the front temperature zone reaches 170 ℃, the rear temperature zone reaches 830 ℃, maintaining the respective temperatures for 15min, naturally cooling to room temperature, and growing an N-type MoS2 film on the inverted silicon wafer to obtain a first sample, wherein the Ar gas flow rate is 60 sccm; MoO3The mass of (2) is 6mg, and the mass of sulfur powder is 800 mg. In addition, adoptWhen the second sample is doped by the low-energy ion implantation method, in this embodiment, under high vacuum, oxygen is introduced and the pressure is set to 5pa, the radio frequency power supply is turned on, and after starting, the power is rapidly adjusted to 3W, and the doping is performed for 30 s.
Since the steps of manufacturing the horizontal homojunction bipolar transistor are the same, the difference between the respective embodiments is only that of the respective parameters, and the above examples only give parameters in individual embodiments; specific examples are shown in table 1 below, where table 1 lists examples of methods for fabricating a horizontal homojunction bipolar transistor, and it should be noted that numbers 1 and 2 in table 1 correspond to example 1 and example 2, respectively.
TABLE 1
In summary, the invention discloses a horizontal homojunction bipolar transistor and a method for manufacturing the same, which adopts a low-energy ion implantation method to controllably and selectively dope MoS2Film of N-type MoS2Selectively doped to P-type MoS2The horizontal homojunction bipolar transistor has the advantages of high carrier mobility, few interface states, high common emitter amplification coefficient, simple, green and controllable preparation process, compatibility with the traditional CMOS (complementary metal oxide semiconductor) process, small damage to two-dimensional materials and wide application prospect in the field of microelectronics.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A horizontal homojunction bipolar transistor, comprising: p-type doped sheetCrystalline silicon, SiO2Oxide layer, N-type MoS2Thin film, P-type MoS2A film and an electrode layer;
the SiO2The oxide layer is positioned on the upper surface of the P-type doped monocrystalline silicon; the N type MoS2Thin film and the P-type MoS2The thin films are all positioned on the SiO2Upper surface of oxide layer, and the N-type MoS2Thin film and the P-type MoS2The films are transversely connected; the electrode layers are respectively positioned on the N-type MoS2Thin film and the P-type MoS2And on the upper surface of the thin film, the electrode layers are not connected with each other.
2. The horizontal homojunction bipolar transistor of claim 1, comprising: the SiO2The thickness of the oxide layer is 50nm-100 nm; the thickness of the P-type doped monocrystalline silicon is 350-550 μm; the N type MoS2Thin film and the P-type MoS2The thickness of the film is 0.65nm-10 nm.
3. The horizontal homojunction bipolar transistor of claim 1, wherein said N-type MoS is a bipolar transistor2Thin film and the P-type MoS2The films are connected through covalent bonds.
4. The horizontal homojunction bipolar transistor of claim 1, wherein said N-type MoS is a bipolar transistor2The film is prepared by adopting a chemical vapor deposition method; the P-type MoS2The film is prepared by adopting a low-energy ion implantation doping method.
5. The horizontal homojunction bipolar transistor of any of claims 1-4, wherein said electrode layer comprises two layers of metal stacked one on top of the other.
6. The bipolar transistor of claim 5, wherein the lower metal of the electrode layer is Ti and has a thickness of 5nm to 15 nm; the upper layer metal of the electrode layer is Au, and the thickness of the upper layer metal is 60-100 nm.
7. A method of fabricating a horizontal homojunction bipolar transistor according to any of claims 1 to 6, comprising the steps of:
s1, selecting SiO on the upper surface2P-type doped monocrystalline silicon of oxide layer as substrate on the SiO2Preparation of N-type MoS on oxide layer2Film, obtaining a first sample;
s2, carrying out first ultraviolet photoetching on the surface of the first sample, and developing to obtain partial N-type MoS2The film is exposed, and part of the N-type MoS2A second sample having a film covered with a photoresist;
s3, doping the second sample by adopting a low-energy ion implantation method, and removing the photoresist to obtain a third sample;
s4, carrying out second ultraviolet photoetching on the surface of the third sample, and developing to obtain the MoS with a partial area of N type2The film and partial area are P-type MoS2A fourth sample of film;
and S5, evaporating metal on the surface of the fourth sample to obtain an electrode layer, and removing the photoresist to obtain the horizontal homojunction bipolar transistor.
8. The method as claimed in claim 7, wherein in step S1, the SiO is deposited by chemical vapor deposition2Preparation of N-type MoS on oxide layer2A film.
9. The method of claim 7, wherein the UV lithography comprises: spin-coating photoresist, and performing pre-baking, pre-exposure, post-baking and post-exposure operations; in the ultraviolet photoetching process, a photoresist spin-coating machine is adopted to rotate for 10-20 s at 1500r/min and then rotate for 25-35 s at 4000r/min, and then photoresist is spin-coated; the pre-exposure time is 1.4 s-2 s; the pre-drying temperature is 90-100 ℃; the post-baking temperature is 110-120 ℃; the post-exposure time is 14 s-20 s.
10. The method as claimed in claim 7, wherein in step S3, the doping gas is O during the doping process of the second sample by low-energy ion implantation2The pressure is 3-7 Pa, the doping radio frequency power is 3-10W, and the doping time is 20-40 s.
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