CN117438376B - Complementary field effect transistor based on two-dimensional material and preparation method thereof - Google Patents

Complementary field effect transistor based on two-dimensional material and preparation method thereof Download PDF

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CN117438376B
CN117438376B CN202311756443.9A CN202311756443A CN117438376B CN 117438376 B CN117438376 B CN 117438376B CN 202311756443 A CN202311756443 A CN 202311756443A CN 117438376 B CN117438376 B CN 117438376B
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field effect
effect transistor
preparing
complementary field
gate dielectric
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CN117438376A (en
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李学飞
李佳康
高婷婷
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Huazhong University of Science and Technology
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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Abstract

The invention relates to the technical field of semiconductors, and discloses a preparation method of a complementary field effect transistor based on a two-dimensional semiconductor material, which comprises the following steps: cleaning the substrate; preparing a marking layer on the substrate; preparing a first channel material; preparing a first source electrode and a first drain electrode on the surface of a first channel material; oxygen doping is carried out on the first channel material; depositing a first gate dielectric on the surfaces of the first source electrode, the first drain electrode and the first channel material, and preparing a gate electrode on the first gate dielectric so as to prepare a bottom field effect transistor; preparing a back gate, and depositing a second gate dielectric on the bottom field effect transistor; forming a second channel material on the surface of the second gate dielectric; and preparing a second source-drain electrode on the second channel material to obtain a top field effect transistor, and then completing the preparation of the CFET. The first channel material and the second channel material in the CFET prepared by the invention are the same two-dimensional material, and compared with CFET based on different channel materials, the CFET prepared by the invention has higher cost benefit and lower preparation difficulty.

Description

Complementary field effect transistor based on two-dimensional material and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a complementary field effect transistor based on a two-dimensional material and a preparation method thereof.
Background
In Semiconductor devices, as feature sizes of silicon transistors continue to shrink, it becomes increasingly difficult to further increase integration due to short channel effects of Complementary Metal Oxide Semiconductor (CMOS) devices based on conventional planar structures. Therefore, a new three-dimensional device architecture is proposed, such as complementary field effect transistors (Complementary Field-EffectTransistor, CFET), wherein the CFET is formed by vertically stacking NMOS and PMOS transistors, and the two transistors share the same gate, so that the area of the chip unit can be reduced by nearly half, and higher integration level can be realized. At the same time it is advantageous in terms of power consumption and performance, so CFET offers a great prospect of continuing moore's law towards smaller technology nodes.
Complementary field effect transistors based on conventional bulk semiconductor materials (e.g., silicon, germanium, etc.), performance tends to degrade as channel length and channel thickness decrease due to short channel effects, which makes the device's scaling potential limited. The two-dimensional semiconductor material has atomic-level thickness and a surface without dangling bonds, so that the two-dimensional semiconductor material can effectively immunity the influence of short channel effect, and is expected to replace traditional semiconductor materials such as silicon and the like to be applied to next-generation electronic and optoelectronic devices. Therefore, the complementary field effect transistor based on the two-dimensional semiconductor material can further improve the integration level of the device.
The existing complementary field effect transistor based on the two-dimensional semiconductor material adopts different channel materials, and as different two-dimensional materials have different requirements and reaction mechanisms in the preparation process, a corresponding preparation process needs to be developed aiming at a specific growth mechanism, and for device preparation, the steps of a process flow are increased, so that the cost control and the efficiency improvement are not facilitated.
Disclosure of Invention
The invention aims to provide a preparation method of a complementary field effect transistor based on a two-dimensional semiconductor material, which uses the same two-dimensional semiconductor material as channel materials of a bottom transistor and a top transistor, can simplify the preparation flow of a device and has higher cost benefit.
In order to achieve the above object, the present invention provides a method for manufacturing a complementary field effect transistor based on a two-dimensional semiconductor material, comprising:
s1: preparing a clean substrate;
s2: preparing a marking layer on the substrate;
s3: transferring a two-dimensional material film to the surface of the substrate to serve as a first channel material of the complementary field effect transistor;
s4: preparing a first source electrode and a drain electrode on the surface of the channel material by adopting an electron beam lithography and electron beam evaporation process;
s5: oxygen doping the channel material by annealing in an oxygen atmosphere;
s6: depositing a first gate dielectric on the surfaces of the first source electrode, the first drain electrode and the first channel material, and preparing a gate electrode on the first gate dielectric through an electron beam evaporation process, so that a bottom field effect transistor is prepared;
s7: preparing a back gate, and depositing a second gate dielectric on the bottom field effect transistor;
s8: selectively etching the medium on the first source-drain electrode area by using a plasma etching process to obtain a through hole;
s9: transferring a two-dimensional material film to the surface of the second gate dielectric to be used as a second channel material of the complementary field effect transistor;
s10: and preparing a second source-drain electrode on the second channel material through electron beam lithography and electron beam evaporation processes, so that a top field effect transistor is obtained, and the preparation of the complementary field effect transistor is completed.
According to one embodiment of the invention, the substrate is a silicon dioxide substrate or a silicon substrate.
According to one embodiment of the present invention, in step S2, the method for preparing the marking layer comprises: and spin-coating photoresist on the surface of the substrate, completing pattern transfer of the marking layer by using electron beam lithography, preparing a physical mark on the pattern by electron beam evaporation, and using the physical mark as a positioning mark of a transferred two-dimensional material and an alignment mark between different layers of a layout.
According to one embodiment of the present invention, the two-dimensional material used in step S3 and S9 is the same, the two-dimensional material being molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten disulfide, tungsten diselenide, rhenium diselenide, tin diselenide, indium diselenide or gallium telluride.
According to one embodiment of the present invention, in the step S5, the oxygen atmosphere annealing condition is that the flow ratio of argon to oxygen is 8:1-10:1, and the annealing temperature is 200-220 ℃.
According to one embodiment of the invention, the first gate dielectric and the second gate dielectric are obtained by atomic layer deposition of a hafnium dioxide film, and precursors of the first gate dielectric are tetra (ethylmethyl amine) hafnium and ozone.
According to one embodiment of the invention, the hafnium oxide thin film has a thickness of 5-20 nm.
According to one embodiment of the present invention, the metal used for the first and second source-drain electrodes is one or more of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt, or iron.
According to one embodiment of the present invention, the via in step S8 is used for the interconnection between the first source-drain electrode and the second source-drain electrode.
According to another aspect of the present invention, there is also provided a complementary field effect transistor based on a two-dimensional semiconductor material prepared by the above method.
In general, compared with the prior art, the above technical solution conceived by the present invention mainly has the following technical advantages:
(1) According to the preparation method of the semiconductor device, disclosed by the invention, the channel material, the gate medium, the gate electrode and the source drain contact metal are stacked layer by layer in a transfer or direct deposition mode to obtain the CFET device, and compared with the CFET preparation technology taking selective etching, channel release, conformal deposition, isolation layer formation and the like as key processes, the preparation method of the semiconductor device provided by the invention simplifies the process flow and has higher cost benefits.
(2) In the preparation method of the semiconductor device, the two-dimensional semiconductor material is used to replace the traditional semiconductor material, and the two-dimensional semiconductor material has the characteristics of atomic-level thickness and surface without dangling bonds, so that the high-quality crystal lattice and good mobility can be maintained under the condition of nanometer thickness. In addition, the CFET architecture with the PMOS and the NMOS vertically stacked together gives up the traditional side-by-side PMOS and NMOS arrangement and can break through the bottleneck of n-p spacing, so that the advanced architecture for stacking the two-dimensional semiconductor material transistors provided by the invention can further reduce semiconductor technology nodes, thereby being beneficial to further miniaturization of future semiconductor devices.
(3) The field effect transistors at the bottom and the top of the CFET device prepared by the method adopt the same two-dimensional semiconductor material as a channel material, so that the integration of an N-type transistor and a P-type transistor with homogeneous channels in the CFET device is realized.
Drawings
Fig. 1 is a flow chart of a preparation method of a CFET based on a two-dimensional semiconductor material according to an embodiment of the present invention.
Fig. 2 to 9 are schematic diagrams showing structural changes in a CFET preparation process based on a two-dimensional semiconductor material according to an embodiment of the present invention.
Reference numerals: 11 is a silicon substrate, 112 is silicon dioxide, 111 is silicon, 211 is a molybdenum ditelluride film (a), 212 is a source-drain contact metal of 10 nm platinum and 30 nm gold, 213 is a first gate dielectric, 214 is a first gate electrode, 311 is a second gate dielectric, 312 is a molybdenum ditelluride film (b), 313 is a source-drain contact metal of 20 nm nickel and 40 nm gold.
Detailed Description
In order to make the preparation method of the present invention more clear, the present invention will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
The complementary field effect transistor device (Complementary Field Effect Transistor, abbreviated as CFET) includes an N-Metal-Oxide-Semiconductor (NMOS) transistor and a P-Metal-Oxide-Semiconductor (PMOS) transistor stacked vertically to increase the integration density of the CMOS device.
In general, the invention prepares the complementary field effect transistor based on two-dimensional semiconductor material molybdenum ditelluride, uses atomic layer deposition equipment to grow gate dielectric film, electron beam evaporation equipment to deposit metal, and electron beam lithography equipment to realize pattern transfer, and the channel material of the field effect transistor is molybdenum ditelluride, and has bipolar transmission characteristic. Besides molybdenum telluride, the metal contact can be made of nickel and other metals, and channel materials and contact metals can be selected according to requirements.
In order to better illustrate the preparation method of the CFET device based on the two-dimensional semiconductor material molybdenum ditelluride, the following examples are used for further illustration.
Example 1
The preparation method of the CFET device based on the two-dimensional material molybdenum ditelluride, the flow of which is shown in figure 1, specifically comprises the following steps:
s1, cleaning a substrate: as shown in fig. 2, silicon 111 and silicon dioxide 112 are used together as a silicon substrate 11, in order to remove particles and impurities on the surface, the silicon substrate is required to be cleaned, deionized water is prepared, ammonia water=5:1 solution, wherein the deionized water is 150 milliliters, the solution is poured into a beaker, heated to 70 ℃ on a hot plate, hydrogen peroxide is added, the solution is heated to 110 ℃, after the solution is bubbled, a silicon wafer is put in, after 10 minutes of heating, the silicon wafer is taken out, the surface of the silicon wafer is cleaned by using deionized water, and then the silicon wafer is dried by using a nitrogen gun.
S2, preparing a marking layer: the cleaned silicon substrate 11 has no reference object which can be used for marking, and a marking layer is required to be prepared on the silicon substrate 11 in order to conveniently perform position calibration on the two-dimensional material which is subsequently transferred onto the silicon substrate 11. Dropping polymethyl methacrylate electron beam photoresist (PMMA A4) on the cleaned silicon substrate 11, covering two-thirds area of the surface of the silicon substrate 11, spin-coating the photoresist by using a spin coater, wherein the rotating speed is 3000 revolutions per minute, and the time is 60 seconds; the glue is baked on a hot plate, the temperature is 180 ℃, and the time is 90 seconds; exposing by using electron beam lithography equipment with the mark layer as a layout; the developing solution is a mixed solution of methyl isobutyl ketone (MIBK) and isopropyl alcohol (IPA) with the mass ratio of 1 to 3, the silicon substrate 11 is immersed in the solution for 50 seconds, taken out, cleaned for 30 seconds by IPA and dried by a nitrogen gun; depositing metal by using an electron beam evaporation device, wherein the deposited metal is 20 nanometers of nickel and 40 nanometers of gold; the substrate was immersed in an acetone solution at 50 degrees celsius for 20 minutes, then the photoresist and metal were stripped off in the unexposed areas using a syringe rinse, and after stripping, cleaned with IPA and blow-dried using a nitrogen gun.
S3, mechanically stripping and transferring the first channel material: sticking the blocky molybdenum ditelluride material on hard glue with the size of 3 multiplied by 3 cm, tearing another hard glue with the hard glue stuck with the material, and repeating for 4 to 8 times to ensure that the thickness of the material reaches a proper thickness; transferring the material on the hard adhesive to the soft adhesive by using the soft adhesive with stronger viscosity, wherein the process is to adhere the soft adhesive on the hard adhesive, wait for 10-20 minutes, and then tear the soft adhesive slowly at an angle of 45 degrees; then as shown in fig. 3, transferring a molybdenum ditelluride film (a) 211 on the soft adhesive to the silicon substrate 11 prepared in the step S2, wherein the specific process is that firstly, the soft adhesive is slowly attached to the silicon substrate 11 from one side of the silicon substrate 11, and after waiting for 20-30 minutes, the soft adhesive is slowly torn at an angle of 45 degrees; the silicon substrate 11 was immersed in an acetone solution for 12 hours, then rinsed with isopropyl alcohol, and dried with a nitrogen gun.
S4, preparing a first source-drain electrode on the first channel material: spin-coating PMMA A4 electron beam photoresist, baking, electron beam lithography, development, electron beam evaporation deposition, stripping and other process flows are consistent with those of S2 for preparing the marking layer, except that the patterns used in the electron beam lithography step are different, and the patterns used in the step S4 are the patterns of the first source-drain contact layer; another difference is that the electron beam evaporated metal is 10 nm platinum and 30 nm gold, which constitute the 10 nm platinum and 30 nm gold source drain contact metal 212, as shown in fig. 4.
S5, oxygen annealing doping: and (3) annealing the device prepared in the step (S4) by using a quartz tube furnace, and introducing mixed gas of argon and oxygen with the flow rate of 10 to 1 during annealing, wherein the flow rate of the argon is 100 standard cubic meters per minute (sccm), the temperature is 200 ℃ and the time is 3 hours.
S6, preparing a first gate electrode: using atomic layer deposition equipment to grow hafnium oxide as a first gate dielectric 213, as shown in fig. 5, the precursors are tetra (ethylmethylamine) hafnium and ozone, the reaction temperature is set to 90 degrees celsius, the thickness is increased by about 0.1 nanometers per growth cycle, the total growth cycle is 100 times, and the thickness of the finally grown hafnium oxide dielectric is 10 nanometers; the first gate electrode 214 is deposited by using an electron beam evaporation device, as shown in fig. 6, where the deposited metal is 10 nm of platinum and 30 nm of gold, and the specific process flows such as spin coating, baking, electron beam lithography, development, electron beam deposition, stripping, etc. are consistent with those of the mark layer prepared in S2, except that the layout of the electron beam lithography is the first gate layer. Thus, the preparation of the bottom transistor is completed, and the bottom transistor is in a top gate structure on the device type.
S7, preparing a second gate electrode: since the transistors at the bottom and the top in the CFET structure share one gate electrode, the preparation of the second gate electrode of the transistor with the back gate structure at the top only needs to deposit one layer of gate dielectric, and the atomic layer deposition equipment is used to deposit hafnium oxide as the second gate dielectric 311, as shown in fig. 7, the process details are consistent with those in the preparation of the first gate dielectric at S6.
S8, forming interconnection through holes: since the first gate electrode and the second gate electrode are covered by the gate dielectric in the steps S6 and S7, in order to implement interconnection of the source or drain electrodes of the bottom field effect transistor and the top field effect transistor, the gate dielectric on the first source/drain electrode region needs to be selectively etched to form a via hole. Dripping AR-P617 electron beam photoresist on the surface of the device prepared in the step S7, uniformly coating at the speed of 4000 revolutions per minute for 60 seconds, and then drying for 60 seconds on a hot plate at 150 ℃; exposing the through hole area layout by using electron beam exposure equipment; etching by using a Reactive Ion Etching (RIE) device, wherein the power is 3 watts; immersing in N-methyl pyrrolidone (NMP) solution for 12 hours to remove the photoresist, immersing in isopropanol for cleaning, and drying by a nitrogen gun.
S9, directional transfer of the second channel material: tearing and thinning the molybdenum ditelluride material to a proper thickness through a hard adhesive pair, and then transferring to a soft adhesive, wherein the process details of stripping and transferring are consistent with those in the step S3; the directional transfer was performed using an optical microscope for determining the molybdenum ditelluride film to be transferred and a three-dimensional micro-manipulation system as an auxiliary tool, and the molybdenum ditelluride film (b) 312 to be transferred was transferred to the target region using the three-dimensional micro-manipulation system, as shown in fig. 8, such that the second channel material at the top was in the vertical direction of the first channel material at the bottom.
S10, preparing a second source-drain electrode on a second channel material: the process flows of spin-coating PMMA A4 electron beam photoresist, baking photoresist, electron beam lithography, developing, electron beam evaporation deposition, stripping and the like are identical to those of the S2 preparation of the marking layer, except that the layout used in the electron beam lithography step is different, the layout design of the second source drain layer is used here, the electron beam evaporated metal is 20 nm nickel and 40 nm gold, and the source drain contact metal 313 of 20 nm nickel and 40 nm gold is formed by the two, as shown in fig. 9, so that the preparation of the CFET device is completed.
According to the two-dimensional material-based CFET device manufacturing method provided by the invention, molybdenum ditelluride is obtained by using a mechanical stripping and transferring mode to serve as a channel material, atomic layer deposited hafnium dioxide serves as a gate medium, and an electron beam is used for evaporating and depositing a metal electrode.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (9)

1. A method for fabricating a two-dimensional material based complementary field effect transistor, comprising:
s1: preparing a clean substrate;
s2: preparing a marking layer on the substrate;
s3: transferring a two-dimensional material film to the surface of the substrate to serve as a first channel material of the complementary field effect transistor;
s4: preparing a first source electrode and a drain electrode on the surface of the channel material by adopting an electron beam lithography and electron beam evaporation process;
s5: oxygen doping the channel material by annealing in an oxygen atmosphere;
s6: depositing a first gate dielectric on the surfaces of the first source electrode, the first drain electrode and the first channel material, and preparing a gate electrode on the first gate dielectric through an electron beam evaporation process, so that a bottom field effect transistor is prepared;
s7: preparing a back gate, and depositing a second gate dielectric on the bottom field effect transistor;
s8: selectively etching the medium on the first source-drain electrode area by using a plasma etching process to obtain a through hole;
s9: transferring a two-dimensional material film to the surface of the second gate dielectric to be used as a second channel material of the complementary field effect transistor;
s10: preparing a second source-drain on the second channel material by electron beam lithography and electron beam evaporation
The pole, thus has obtained the top field effect transistor, has finished the preparation of the said complementary field effect transistor;
the two-dimensional materials adopted in the step S3 and the step S9 are the same, and the two-dimensional materials are molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten disulfide, tungsten diselenide, rhenium diselenide, tin diselenide, indium diselenide or gallium telluride.
2. The method for manufacturing a two-dimensional material-based complementary field effect transistor according to claim 1, wherein the substrate is a silicon dioxide substrate or a silicon substrate.
3. The method for manufacturing a two-dimensional material-based complementary field effect transistor according to claim 1, wherein in step S2, the method for manufacturing the marker layer is as follows: and spin-coating photoresist on the surface of the substrate, completing pattern transfer of the marking layer by using electron beam lithography, preparing a physical mark on the pattern by electron beam evaporation, and using the physical mark as a positioning mark of a transferred two-dimensional material and an alignment mark between different layers of a layout.
4. The method for manufacturing a two-dimensional material-based complementary field effect transistor according to claim 1, wherein in the step S5, the oxygen atmosphere annealing condition is that the flow ratio of argon to oxygen is 8:1-10:1, and the annealing temperature is 200-220 ℃.
5. The method for manufacturing the two-dimensional material-based complementary field effect transistor according to claim 1, wherein the first gate dielectric and the second gate dielectric are obtained by atomic layer deposition of a hafnium oxide film, and precursors of the first gate dielectric are tetra (ethylmethylamine) hafnium and ozone.
6. The method for manufacturing a two-dimensional material-based complementary field effect transistor according to claim 5, wherein the thickness of the hafnium oxide thin film is 5-20 nm.
7. The method for manufacturing a two-dimensional material-based complementary field effect transistor according to claim 1, wherein the metal used for the first source drain electrode and the second source drain electrode is one or more of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt or iron.
8. The method of manufacturing a two-dimensional material based complementary field effect transistor according to claim 1, wherein the via in step S8 is used for the interconnection between the first source drain electrode and the second source drain electrode.
9. A two-dimensional material based complementary field effect transistor prepared by the method of any one of claims 1-8.
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