CN112687319B - Method and device for calibrating MRAM memory chip - Google Patents
Method and device for calibrating MRAM memory chip Download PDFInfo
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Abstract
The invention provides a calibration method and a device of an MRAM memory chip, comprising the following steps: writing one part of all storage bit positions of each storage module of the storage chip into 1 and the other part of all storage bit positions of each storage module of the storage chip into 0, and acquiring respective reading passing rates of the storage modules when different reference voltages are input to obtain a first V-RPR curve between the reading passing rates and the reference voltages; respectively calculating corresponding first optimal reference voltages of the storage modules when the reading passing rate is highest according to respective first V-RPR curves of the storage modules, and averaging all the obtained first optimal reference voltages to obtain first optimal average voltages; and comparing the first optimal reference voltage and the first optimal average voltage of each memory module, and if the voltage difference between the first optimal reference voltage and the first optimal average voltage of the memory modules is greater than a set threshold value, adjusting the variable reference resistance of the reading circuit of the memory module. The invention can improve the reading passing rate of the memory chip.
Description
Technical Field
The present invention relates to the field of MRAM memory technologies, and in particular, to a method and an apparatus for calibrating an MRAM memory chip.
Background
MRAM memory chips are typically designed to include a plurality of memory modules, each of which is independent, each of which includes a memory array and read circuitry, each of which performs read and write operations via respective Data (DQ) lines.
Taking a memory module as an example, fig. 1 shows a connection relationship between any one memory bit and a reading circuit in a memory array of the memory module, mij and MTJij represent any one memory bit and are connected to a transistor M1, the resistance of M1 can be adjusted by changing a gate voltage Vclamp of M1, and then the size of Imtj is adjusted, a reference circuit is formed by a reference resistor RINT and a transistor M2, switching on and off of the reference resistor is controlled by an instruction, so that series-parallel relationship of the reference resistor is changed, the reference resistor can be adjusted, the resistance of M2 can be adjusted by changing a reference voltage Vref input by a gate of M2, and then a reference circuit current Iref is controlled, a sense amplifier SA outputs a reading result according to the sizes of Imtj and Iref, when Imtj > Iref, SA outputs 0, and otherwise 1.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:
due to process limitations, MTJ resistance values and performances of different memory modules in a memory chip may be affected by wafer positions to cause deviations, and resistance values of reference resistors RINT of reading circuits of different memory modules also have certain differences, so that the memory chip has a high Read Error Rate (RER) when reading data.
Disclosure of Invention
In order to solve the above problems, the present invention provides a calibration method and apparatus for an MRAM memory chip, which can improve the read throughput of the memory chip.
In a first aspect, the present invention provides a calibration method for an MRAM memory chip, where the MRAM memory chip includes a plurality of memory modules, each of the memory modules includes a plurality of memory bits distributed in an array and a reading circuit, and the reading circuit of each of the memory modules is configured to read data of the memory bits, and the method includes:
writing one part of all storage bit elements of each storage module into 1 and the other part of all storage bit elements of each storage module into 0, and acquiring the respective read passing rate of each storage module when different reference voltages are input into the respective read circuits to obtain a first V-RPR curve between the read passing rate of each storage module and the reference voltages;
respectively calculating corresponding first optimal reference voltages of the storage modules when the reading passing rate is highest according to respective first V-RPR curves of the storage modules, and averaging all the obtained first optimal reference voltages to obtain first optimal average voltages;
and comparing the first optimal reference voltage and the first optimal average voltage of each memory module, and if the voltage difference between the first optimal reference voltage and the first optimal average voltage of the memory modules is greater than a set threshold, adjusting a variable reference resistance of a reading circuit of the memory modules, so that the voltage difference between the first optimal reference voltage and the first optimal average voltage of the memory modules after adjustment is smaller than or equal to the set threshold.
Optionally, the adjusting the variable reference resistance of the reading circuit of the memory module includes:
taking the first optimal average voltage as a reference voltage input into the storage module, and if the first optimal reference voltage of the storage module is smaller than the first optimal average voltage, sending a control instruction to increase the reference resistance of a reading circuit of the storage module;
if the first optimal reference voltage of the memory module is greater than the first optimal average voltage, a control command is sent to reduce the reference resistance of a reading circuit of the memory module.
Optionally, the method further comprises:
the data of all storage bit positions of each storage module are all inverted, the respective reading passing rate of each storage module when different reference voltages are input into the respective reading circuit is obtained, and a second V-RPR curve between the reading passing rate of each storage module and the reference voltages is obtained;
respectively calculating corresponding second optimal reference voltages of the storage modules when the reading passing rate is highest according to respective second V-RPR curves of the storage modules, and averaging all the obtained second optimal reference voltages to obtain a second optimal average voltage;
and comparing the second optimal reference voltage and the second optimal average voltage of each memory module, and if the voltage difference between the second optimal reference voltage and the second optimal average voltage of each memory module is smaller than a set threshold, finishing calibration, otherwise, needing recalibration.
In a second aspect, the present invention provides a calibration method for an MRAM memory chip, where the MRAM memory chip includes a plurality of memory modules, each of the memory modules includes a plurality of memory bits distributed in an array and a reading circuit, and the reading circuit of each of the memory modules is configured to read data of the memory bits, and the method includes:
writing all storage bit elements of each storage module into all 1 or all 0, acquiring corresponding reference voltages of all storage bit elements of each storage module when the reading result changes, and calculating the average value and the standard deviation of all reference voltages of each storage module;
the data of all storage bit elements of each storage module are all inverted, the corresponding reference voltage of all storage bit elements of each storage module when the reading result changes is obtained, and the average value and the standard deviation of all reference voltages of each storage module are calculated;
respectively calculating the reference voltage window of each memory module:
window∈[μ ap +nσ ap ,μ p -nσ p ]wherein, mu ap And σ ap When all the memory bits of each memory module are written with all 1, the average value and standard deviation mu of all the reference voltages p And σ p Respectively writing all the storage bits of each storage module as all 0, wherein n is a constant, and the average value and the standard deviation of all the reference voltages are obtained;
and judging whether all the reference voltage windows have overlapping intervals, and if all the reference voltage windows do not have overlapping intervals, adjusting the variable reference resistance of the reading circuit of each memory module to ensure that all the adjusted reference voltage windows have overlapping intervals.
Optionally, the adjusting the variable reference resistance of the reading circuit of each memory module includes:
taking the average value of the median voltages of all the reference voltage windows as the reference voltage input into each memory module, and if the first optimal reference voltage of the memory module is smaller than the first optimal average voltage, sending a control instruction to increase the reference resistance of a reading circuit of the memory module;
and if the first optimal reference voltage of the storage module is greater than the first optimal average voltage, sending a control command to reduce the reference resistance of a reading circuit of the storage module.
In a third aspect, the present invention provides a calibration apparatus for an MRAM memory chip, where the MRAM memory chip includes a plurality of memory modules, each of the memory modules includes a plurality of memory bits distributed in an array and a reading circuit, and the reading circuit of each of the memory modules is configured to read data of the memory bits, and the apparatus includes:
the first V-RPR curve calculation module is used for writing one part of all storage bit elements of each storage module into 1 and the other part into 0, acquiring the respective read passing rate of each storage module when different reference voltages are input into the respective read circuits of each storage module, and obtaining a first V-RPR curve between the read passing rate of each storage module and the reference voltage;
the first optimal average voltage calculation module is used for respectively calculating corresponding first optimal reference voltages of the storage modules when the reading passing rate is highest according to respective first V-RPR curves of the storage modules, and averaging all the obtained first optimal reference voltages to obtain first optimal average voltages;
the first comparison module is used for comparing the first optimal reference voltage of each memory module with the first optimal average voltage;
the first reference resistance adjusting module is configured to adjust a variable reference resistance of a read circuit of the memory module when a voltage difference between a first optimal reference voltage of the memory module and the first optimal average voltage is greater than a set threshold, so that the adjusted voltage difference between the first optimal reference voltage of the memory module and the first optimal average voltage is less than or equal to the set threshold.
Optionally, the first reference resistance adjusting module is configured to use the first optimal average voltage as a reference voltage input to the storage module, and send a control instruction to increase a reference resistance of a read circuit of the storage module if the first optimal reference voltage of the storage module is smaller than the first optimal average voltage;
and if the first optimal reference voltage of the storage module is greater than the first optimal average voltage, sending a control command to reduce the reference resistance of a reading circuit of the storage module.
Optionally, the apparatus further comprises:
the second V-RPR curve calculation module is used for inverting all the data of all the storage bits of each storage module, acquiring the respective read passing rate of each storage module when different reference voltages are input into the respective read circuit, and obtaining a second V-RPR curve between the read passing rate of each storage module and the reference voltage;
the second optimal average voltage calculation module is used for respectively calculating second optimal reference voltages corresponding to the storage modules when the reading passing rate is highest according to respective second V-RPR curves of the storage modules, and averaging all the obtained second optimal reference voltages to obtain second optimal average voltages;
and the second comparison module is used for comparing the second optimal reference voltage and the second optimal average voltage of each memory module, and if the voltage difference between the second optimal reference voltage and the second optimal average voltage of each memory module is smaller than a set threshold, the calibration is finished, otherwise, the recalibration is needed.
In a fourth aspect, the present invention provides a calibration apparatus for an MRAM memory chip, where the MRAM memory chip includes a plurality of memory modules, each of the memory modules includes a plurality of memory bits distributed in an array and a reading circuit, and the reading circuit of each of the memory modules is configured to read data of the memory bits, the apparatus includes:
the first reference voltage calculation module is used for writing all storage bit elements of each storage module into all 1 or all 0, acquiring corresponding reference voltages of all storage bit elements of each storage module when the reading result changes, and calculating the average value and the standard deviation of all reference voltages of each storage module;
the second reference voltage calculation module is used for inverting all data of all storage bit elements of each storage module, acquiring corresponding reference voltages of all storage bit elements of each storage module when the reading result changes, and calculating the average value and the standard deviation of all reference voltages of each storage module;
a reference voltage window calculation module, configured to calculate a reference voltage window of each of the memory modules:
window∈[μ ap +nσ ap ,μ p -nσ p ]wherein, mu ap And σ ap When all the memory bits of each memory module are written with all 1, the average value and standard deviation mu of all the reference voltages p And σ p Respectively writing all the storage bits of each storage module as all 0, wherein n is a constant, and the average value and the standard deviation of all the reference voltages are obtained;
the first judgment module is used for judging whether all the reference voltage windows have overlapping intervals or not;
and the second reference resistance adjusting module is used for adjusting the variable reference resistance of the reading circuit of each memory module when all the reference voltage windows have no overlapping interval, so that all the adjusted reference voltage windows have overlapping intervals.
Optionally, the second reference resistance adjusting module is configured to use an average value of median voltages of all the reference voltage windows as a reference voltage input to each of the memory modules, and send a control instruction to increase a reference resistance of a read circuit of the memory module if a first optimal reference voltage of the memory module is smaller than the first optimal average voltage;
if the first optimal reference voltage of the memory module is greater than the first optimal average voltage, a control command is sent to reduce the reference resistance of a reading circuit of the memory module.
According to the calibration method and device for the MRAM memory chip, the reference voltages of different memory modules are calibrated to keep the reference voltages of the reading circuits of the memory modules consistent, and then the variable reference resistance RINT of the reading circuits of the memory modules is calibrated to enable the optimal Vref of each memory module to be close to or equal to each other, so that the lowest RER is obtained.
Drawings
FIG. 1 is a schematic diagram of a memory module of an MRAM memory chip;
FIG. 2 is a flow chart illustrating a method for calibrating an MRAM memory chip according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a V-RPR curve of a memory module DQ0 obtained in an embodiment of the invention;
FIG. 4 is a schematic diagram of a V-RPR curve of each DQ and a reference voltage Vop at the highest RPR according to an embodiment of the present invention;
FIG. 5 is a V-RPR curve for each DQ after calibration in an embodiment of the invention;
FIG. 6 is a flow chart illustrating a method for calibrating an MRAM memory chip according to an embodiment of the invention;
FIG. 7 is a diagram illustrating a reference voltage distribution curve of DQ0 when all MTJs are in the AP state according to an embodiment of the invention;
FIG. 8 is a diagram illustrating a reference voltage distribution curve of DQ0 when all MTJs are in the P state according to an embodiment of the invention;
FIG. 9 is a schematic diagram illustrating non-overlapping reference voltage windows of DQs according to an embodiment of the invention;
FIG. 10 is a window of reference voltages for each DQ after calibration in an embodiment of the invention;
FIG. 11 is a diagram illustrating an apparatus for calibrating an MRAM memory chip according to an embodiment of the invention;
FIG. 12 is a diagram illustrating an apparatus for calibrating an MRAM memory chip according to an embodiment of the invention;
FIG. 13 is a diagram illustrating an apparatus for calibrating an MRAM memory chip according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a calibration method for an MRAM memory chip, where the MRAM memory chip includes a plurality of memory modules, each of the memory modules includes a plurality of memory bits and a reading circuit distributed in an array, and the reading circuit of each of the memory modules is configured to read data of the memory bits, as shown in fig. 2, the method includes:
s201, writing one part of all storage bit positions of each storage module into 1 and the other part of all storage bit positions of each storage module into 0, and acquiring the respective read passing rate of each storage module when different reference voltages are input into the respective read circuits of each storage module to obtain a first V-RPR curve between the read passing rate of each storage module and the reference voltages;
s202, respectively calculating first optimal reference voltages corresponding to the memory modules when the read passing rate is highest according to respective first V-RPR curves of the memory modules, and averaging all the obtained first optimal reference voltages to obtain first optimal average voltages;
s203, comparing the first optimal reference voltage and the first optimal average voltage of each of the memory modules, and if a voltage difference between the first optimal reference voltage and the first optimal average voltage of the memory module is greater than a set threshold, adjusting a variable reference resistance of a read circuit of the memory module, so that the adjusted voltage difference between the first optimal reference voltage and the first optimal average voltage of the memory module is less than or equal to the set threshold.
In this embodiment, before starting step S201, a part of data of all memory bits of each memory module of the MRAM memory chip is written to be 1, and another part is written to be 0, for example, the memory bits are written to include but not limited to 10101 \8230 \ 8230, etc. 1 and 0 each occupy a certain proportion, and the MTJ can be written to be a p-state or an ap-state by using an electric field, a magnetic field or other stimuli, where the p-state represents 0 and the ap-state represents 1.
In step S201, taking a memory module as an example, an MTJ is gated, and a fixed voltage in the linear region of the transistor is applied to the gate of the transistor M1 connected to the MTJ and remains unchanged. Correspondingly, the RPR (Read Pass Rate) of the memory module under each reference voltage is obtained by reducing or increasing the reference voltage Vref input by the memory module at a certain speed by being high enough or low enough, and then a dependence curve between the RPR of the memory module and the reference voltage Vref, namely a V-RPR curve, is obtained; in this embodiment, referring to the read circuit shown in fig. 1, DQ0 is tested first, the reference voltage Vref is gradually increased from 0.5V to 0.8V, and 0.025V is adjusted each time, in this process, the RPR of DQ0 under each Vref is obtained respectively, so as to obtain a V-RPR curve of DQ0, and the V-RPR curve of DQ0 can refer to fig. 3. By adopting the same method, DQ1, \8230;, V-RPR curves of DQn are obtained in sequence, and the obtained V-RPR curves of different memory modules can be referred to FIG. 4.
In step S202, with reference to fig. 4, according to the V-RPR curves of the memory modules, first optimal reference voltages corresponding to the memory modules when the read pass rate of each memory module is highest are respectively calculated, and are respectively denoted as Vop0, vop1, \8230 \ 8230:vopn, i.e. Vop0, vop1, \8230:, vopn is respectively the highest point of the V-RPR curve of each memory module, and the obtained Vop0, vop1, \8230:, vopn is averaged to obtain a first optimal average voltage Vop _ mean, in this embodiment, vop _ mean =0.6485V.
In step S203, vop0, vop1, \8230;, whether the voltage difference between Vopn and Vop _ mean is less than or equal to a set threshold value, i.e., whether Vop0, vop1, \8230;, 8230;, whether Vopn is all close to or equal to Vop _ mean, are sequentially compared. Taking DQ0 as an example, if the difference between Vop0 and Vop _ mean is less than or equal to the set threshold, DQ0 does not need to be adjusted, and the reference resistance in the DQ0 reading circuit is kept; if the difference between Vop0 and Vop _ mean is greater than the set threshold, then Vop _ mean is used as the reference voltage of DQ0, and the reference resistance in the DQ0 reading circuit is adjusted, the specific adjustment method is as follows: and if Vop0 of DQ0 is smaller than Vop _ mean, sending a control command to increase the reference resistance of DQ0, and if Vop0 of DQ0 is larger than Vop _ mean, sending a control command to decrease the reference resistance of DQ0, so that the difference between the adjusted Vop0 and Vop _ mean is smaller than or equal to the set threshold. Other memory modules DQ1, \ 8230 \ 8230;, DQn may be analogized in the same way. Finally, each DQ Vop is approximated to Vop mean by adjusting the value of each DQ reference resistance RINT. FIG. 5 shows a V-RPR curve for each memory block of a memory chip after calibration, with the Vop of each DQ being close to Vop mean.
By the calibration method, the variable reference resistance of the reading circuit of the memory module is calibrated, the optimal reference voltage of each memory module approaches to the first optimal average voltage Vop _ mean, and the first optimal average voltage Vop _ mean is used as the reference voltage input by each memory module during subsequent tests, so that each memory module has the optimal reading passing rate.
Further, after the above calibration procedure, the method further comprises:
s204, all the data of all the storage bit positions of each storage module are inverted, the respective reading passing rate of each storage module when different reference voltages are input into the respective reading circuit is obtained, and a second V-RPR curve between the reading passing rate of each storage module and the reference voltages is obtained;
s205, respectively calculating second optimal reference voltages corresponding to the storage modules when the reading passing rate is highest according to respective second V-RPR curves of the storage modules, and averaging all the obtained second optimal reference voltages to obtain second optimal average voltages;
s206, comparing the second optimal reference voltage and the second optimal average voltage of each memory module, if the voltage difference between the second optimal reference voltage and the second optimal average voltage of each memory module is smaller than a set threshold, finishing calibration, otherwise, needing recalibration.
Through steps S204 to S206, the calibration effect of the MRAM memory chip can be verified, and subsequent reading is performed using the calibrated variable reference resistance and the first optimal average voltage of the reading circuit of each memory module, thereby improving the RPR.
In addition, the RINT and the Vref in the above embodiments can be adjusted by TM and stored in E-fuse for modification. When Vop of the read circuits of each memory array is close to or equal to Vop _ mean, eFUSE is written with Vref and each DQ RINT modified value.
Another embodiment of the present invention provides a calibration method for an MRAM memory chip, where the MRAM memory chip includes a plurality of memory modules, each of the memory modules includes a plurality of memory bits and a reading circuit distributed in an array, and the reading circuit of each of the memory modules is configured to read data of the memory bits, as shown in fig. 6, the method includes:
s601, writing all storage bit elements of each storage module into all 1 or all 0, acquiring corresponding reference voltages of all storage bit elements of each storage module when the reading result changes, and calculating the average value and the standard deviation of all reference voltages of each storage module;
s602, all data of all storage bits of each storage module are inverted, corresponding reference voltages of all storage bits of each storage module when the reading result changes are obtained, and the average value and the standard deviation of all reference voltages of each storage module are calculated;
s603, respectively calculating a reference voltage window of each memory module:
window∈[μ ap +nσ ap ,μ p -nσ p ]wherein, mu ap And σ ap When all the memory bits of each memory module are written with all 1, the average value and standard deviation mu of all the reference voltages p And σ p Respectively writing all the storage bits of each storage module as all 0, wherein n is a constant, and the average value and the standard deviation of all the reference voltages are obtained;
s604, judging whether all the reference voltage windows have overlapping intervals, and if all the reference voltage windows do not have overlapping intervals, adjusting the variable reference resistance of the reading circuit of each memory module to enable all the adjusted reference voltage windows to have overlapping intervals.
In this embodiment, in step S601, all memory bits of each memory module of the memory chip are first written to 1, taking DQ0 as an example, each MTJ in DQ0 is sequentially gated, then Vref voltage of DQ0 is decreased or increased at a certain rate from high enough or low enough to SA output jump, at this time, iref1= Imtj1 is considered, a reference voltage corresponding to each MTJ when read result (SA output) jump occurs is obtained, a series of discrete Vref values are obtained, and then an average value μ of all Vref values is calculated ap And standard deviation σ ap ，μ ap ＝0.6106，σ ap =0.005969, other memory modules DQ1, \8230 \ 8230;, DQn, and so on. Optionally, for each memory module, a discrete overall Vref is fitted, including but not limited to a normal distribution curve, a skewed distribution curve, and the like.
For example, a normal fitting is performed according to equation (1) to obtain a reference voltage distribution curve when all the memory modules write 1, where equation (1) is as follows:
wherein, mu ap ，σ ap Respectively writing all the storage bits of each storage module as all 1, and then averaging and standard deviation of all the reference voltages; FIG. 7 shows distribution curve 1 after DQ0 all writes 1 fits.
In step S602, all the storage bit data of each memory module of the memory chip is inverted, that is, all the storage bit data are written to 0, taking DQ0 as an example, each MTJ in DQ0 is gated in sequence, then the reference voltage input by DQ0 is changed, the reference voltage corresponding to each MTJ when the read result (SA output) jumps is obtained, a series of discrete Vref values are obtained, and then the average value μ of all the Vref values is calculated p And standard deviation σ p Other memory modules DQ1, \8230; \ 8230;, DQn may be analogized in the same way. Optionally, for each memory module, a discrete overall Vref is fitted, including but not limited to a normal distribution curve, a skewed distribution curve, and the like.
For example, a normal fitting is performed according to equation (2) to obtain a reference voltage distribution curve when all the memory modules write 0, where equation (2) is as follows:
wherein, mu p ，σ p All reference voltages when all memory bits of each of the memory modules are written to all 0Mean and standard deviation; FIG. 8 shows distribution curve 2 after DQ0 all writes 0 fits.
In step S603, n =6 is selected, and window ∈ [ μ ∈ in ap +6σ ap ,μ p -6σ p ]Calculating a reference voltage window of each DQ, the obtained reference voltage window of each DQ being shown in fig. 9;
in step S604, based on fig. 9, it is determined whether all the reference voltage windows have an overlapping section, and if all the reference voltage windows have an overlapping section, the median voltage of the overlapping section is used as the reference voltage input to each of the memory modules, and the variable reference resistance of the read circuit of each of the memory modules is kept unchanged; and if all the reference voltage windows have no overlapping interval, fixing the reference voltage input by each memory module to the average value of the median voltage of each reference voltage window, and adjusting the variable reference resistance of the reading circuit of each memory module so that all the adjusted reference voltage windows have overlapping intervals. The specific adjusting method comprises the following steps: taking DQ0 as an example, if Vm0 of DQ0 is smaller than Vm _ mean, a control command is sent to increase the reference resistance of DQ0, and conversely, if Vm0 of DQ0 is larger than Vm _ mean, a control command is sent to decrease the reference resistance of DQ0, so as to calibrate the reference voltage window of each memory module. Fig. 10 shows a window of reference voltages for each DQ after calibration, with an overlap interval.
It should be noted that, after the above calibration procedure, the above test is repeated, and when there is an overlap interval in each DQ Vref window, vref = Vm _ mean =0.6485V and a modified value of each DQ RINT are written into the eFUSE.
By the calibration method, by adjusting Vref and changing RINT resistance of each DQ, read error rate caused by MTJ resistance distribution among DQs, reference resistance and difference between other reference circuits and memory circuits can be reduced. Drift relationships between all MTJs among different DQs and the entire reference circuit can also be obtained, reducing the effect of differences among individual MTJs.
An embodiment of the present invention further provides a calibration apparatus for an MRAM memory chip, where the MRAM memory chip includes a plurality of memory modules, each of the memory modules includes a plurality of memory bits and a reading circuit distributed in an array, and the reading circuit of each of the memory modules is configured to read data of the memory bits, as shown in fig. 11, the apparatus includes:
a first V-RPR curve calculation module 1101, configured to write a part of all storage bits of each storage module as 1 and another part as 0, obtain respective read passing rates of the storage modules when different reference voltages are input to respective read circuits, and obtain a first V-RPR curve between the read passing rate of each storage module and the reference voltage;
a first optimal average voltage calculation module 1102, configured to calculate, according to the respective first V-RPR curves of each of the memory modules, a corresponding first optimal reference voltage of each of the memory modules when the read pass rate is highest, and average all the obtained first optimal reference voltages to obtain a first optimal average voltage;
a first comparing module 1103, configured to compare the first optimal reference voltage of each of the memory modules with the first optimal average voltage;
a first reference resistance adjusting module 1104, configured to adjust a variable reference resistance of a read circuit of the memory module when a voltage difference between a first optimal reference voltage of the memory module and the first optimal average voltage is greater than a set threshold, so that the adjusted voltage difference between the first optimal reference voltage of the memory module and the first optimal average voltage is less than or equal to the set threshold.
Optionally, the first reference resistance adjusting module 1104 is configured to use the first optimal average voltage as a reference voltage input to the memory module, and send a control instruction to increase a reference resistance of a read circuit of the memory module if the first optimal reference voltage of the memory module is smaller than the first optimal average voltage;
if the first optimal reference voltage of the memory module is greater than the first optimal average voltage, a control command is sent to reduce the reference resistance of a reading circuit of the memory module.
Optionally, as shown in fig. 12, the apparatus further includes:
a second V-RPR curve calculation module 1105, configured to invert all data of all storage bits of each of the storage modules, obtain respective read passing rates of the storage modules when different reference voltages are input to respective read circuits, and obtain a second V-RPR curve between the read passing rate of each of the storage modules and the reference voltage;
a second optimal average voltage calculation module 1106, configured to calculate, according to the respective second V-RPR curves of each of the memory modules, a second optimal reference voltage corresponding to each of the memory modules when the read pass rate is highest, and average all the obtained second optimal reference voltages to obtain a second optimal average voltage;
a second comparing module 1107, configured to compare the second optimal reference voltage and the second optimal average voltage of each memory module, if all voltage differences between the second optimal reference voltage and the second optimal average voltage of each memory module are smaller than a set threshold, the calibration is finished, otherwise, the calibration needs to be performed again.
Another embodiment of the present invention further provides a calibration apparatus for an MRAM memory chip, where the MRAM memory chip includes a plurality of memory modules, each of the memory modules includes a plurality of memory bits distributed in an array and a reading circuit, and the reading circuit of each of the memory modules is configured to read data of the memory bits, as shown in fig. 13, the apparatus includes:
a first reference voltage calculation module 1301, configured to write all the storage bits of each storage module to be all 1 s or all 0 s, obtain a reference voltage corresponding to all the storage bits of each storage module when a read result changes, and calculate an average value and a standard deviation of all the reference voltages of each storage module;
a second reference voltage calculating module 1302, configured to invert all data of all storage bits of each storage module, obtain a corresponding reference voltage when a reading result of all storage bits of each storage module changes, and calculate an average value and a standard deviation of all reference voltages of each storage module;
a reference voltage window calculating module 1303, configured to calculate a reference voltage window of each of the memory modules:
window∈[μ ap +nσ ap ,μ p -nσ p ]wherein, mu ap And σ ap When all the memory bits of each memory module are written with all 1, the average value and standard deviation mu of all the reference voltages p And σ p Respectively writing all the storage bits of each storage module as all 0, wherein n is a constant, and the average value and the standard deviation of all the reference voltages are obtained;
a first determining module 1304, configured to determine whether all the reference voltage windows have an overlapping interval;
a second reference resistance adjusting module 1305, configured to, when all the reference voltage windows have no overlapping interval, adjust a variable reference resistance of a reading circuit of each of the memory modules, so that all the adjusted reference voltage windows have an overlapping interval.
Optionally, the second reference resistance adjusting module 1305 is configured to use an average value of median voltages of all the reference voltage windows as a reference voltage input to each of the memory modules, and send a control instruction to increase the reference resistance of the read circuit of the memory module if the first optimal reference voltage of the memory module is smaller than the first optimal average voltage;
if the first optimal reference voltage of the memory module is greater than the first optimal average voltage, a control command is sent to reduce the reference resistance of a reading circuit of the memory module.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by a computer program, which may be stored in a computer readable storage medium and executed by a computer to implement the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. A method for calibrating an MRAM memory chip, the MRAM memory chip comprising a plurality of memory modules, each of the memory modules comprising a plurality of memory bits distributed in an array and a read circuit, the read circuit of each of the memory modules being configured to read data of the memory bits, the method comprising:
writing all storage bit elements of each storage module into all 1 or all 0, acquiring corresponding reference voltages of all storage bit elements of each storage module when the reading result changes, and calculating the average value and the standard deviation of all reference voltages of each storage module;
the data of all storage bit elements of each storage module are all inverted, the corresponding reference voltage of all storage bit elements of each storage module when the reading result changes is obtained, and the average value and the standard deviation of all reference voltages of each storage module are calculated;
respectively calculating the reference voltage window of each memory module:
window∈[μ ap +nσ ap ,μ p -nσ p ]wherein, mu ap And σ ap When all the memory bits of each memory module are written with all 1, the average value and standard deviation mu of all the reference voltages p And σ p Respectively writing all the storage bits of each storage module as all 0, wherein n is a constant, and the average value and the standard deviation of all the reference voltages are obtained;
and judging whether all the reference voltage windows have overlapping intervals, and if all the reference voltage windows do not have overlapping intervals, adjusting the variable reference resistance of the reading circuit of each memory module to ensure that all the adjusted reference voltage windows have overlapping intervals.
2. The method of claim 1, wherein said adjusting a variable reference resistance of a read circuit of each of said memory modules comprises:
taking the average value of the median voltages of all the reference voltage windows as the reference voltage input into each memory module, and if the median voltage of the reference voltage windows of the memory modules is smaller than the average value of the median voltages of all the reference voltage windows, sending a control instruction to increase the reference resistance of a reading circuit of the memory module;
and if the median voltage of the reference voltage window of the storage module is larger than the average value of the median voltages of all the reference voltage windows, sending a control instruction to reduce the reference resistance of a reading circuit of the storage module.
3. An apparatus for calibrating an MRAM memory chip, the MRAM memory chip comprising a plurality of memory modules, each of the memory modules comprising a plurality of memory bits distributed in an array and a read circuit, the read circuit of each of the memory modules being configured to read data of the memory bits, the apparatus comprising:
the first reference voltage calculation module is used for writing all the storage bits of each storage module into all 1 s or all 0 s, acquiring the corresponding reference voltages of all the storage bits of each storage module when the reading result changes, and calculating the average value and the standard deviation of all the reference voltages of each storage module;
the second reference voltage calculation module is used for inverting all data of all storage bit elements of each storage module, acquiring corresponding reference voltages of all storage bit elements of each storage module when the reading result changes, and calculating the average value and the standard deviation of all reference voltages of each storage module;
a reference voltage window calculation module, configured to calculate a reference voltage window of each of the memory modules:
window∈[μ ap +nσ ap ,μ p -nσ p ]wherein, mu ap And σ ap When all the memory bits of each memory module are written with all 1, the average value and standard deviation mu of all the reference voltages p And σ p Respectively writing all the storage bits of each storage module as all 0, wherein n is a constant, and the average value and the standard deviation of all the reference voltages are obtained;
the judging module is used for judging whether all the reference voltage windows have overlapping intervals or not;
and the reference resistance adjusting module is used for adjusting the variable reference resistance of the reading circuit of each memory module when all the reference voltage windows have no overlapping interval, so that all the adjusted reference voltage windows have overlapping intervals.
4. The apparatus of claim 3, wherein the reference resistance adjusting module is configured to use an average value of median voltages of all the reference voltage windows as the reference voltage input to each of the memory modules, and send a control command to increase the reference resistance of the read circuit of the memory module if the median voltage of the reference voltage window of the memory module is smaller than the average value of the median voltages of all the reference voltage windows;
and if the median voltage of the reference voltage window of the storage module is larger than the average value of the median voltages of all the reference voltage windows, sending a control instruction to reduce the reference resistance of a reading circuit of the storage module.
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| CN107731259A (en) * | 2016-08-10 | 2018-02-23 | 爱思开海力士有限公司 | The optimal accumulator system and its operating method for reading reference voltage |
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