CN112670197B - Method for detecting micro-size etching depth and uniformity of ICP process - Google Patents
Method for detecting micro-size etching depth and uniformity of ICP process Download PDFInfo
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Abstract
A method for detecting micro-size etching depth and uniformity of an ICP process relates to a method for detecting micro-size etching depth and uniformity of an ICP process. The method solves the problems that the existing method for detecting the depth and uniformity of etching micro-sized silicon microstructures by the ICP technology has large measurement error, is inconvenient to continuously etch, and wastes time and labor. The method comprises the steps of determining the corrosion depth of the back surface of the wafer; etching the back surface of each unit of the wafer by adopting an anisotropic wet method to form a slope structure with an angle of 54.74 degrees according to the determined etching depth; aligning the region to be etched with the slope structure by a double-sided photoetching alignment technology; and (3) etching the fixed line width structure in the area to be etched of the wafer by adopting an ICP process, wherein no new etching structure is generated, calculating the maximum depth of the ICP process in the etching width by utilizing the etching depth corresponding to the etching structure appearing last, and calculating the etching uniformity of the ICP process in the width. The invention is suitable for detecting the etching depth and uniformity of the micro-size of the ICP process.
Description
Technical Field
The invention relates to a method for detecting micro-size etching depth and uniformity by an ICP process.
Background
With the development of integrated technology and micro-nano system technology, the feature size and volume of devices are smaller and smaller, such as resonant sensors, comb-tooth structure capacitance sensors and the like, and the micro-structure processing technology with high aspect ratio (the ratio of the groove depth to the groove width) is a key means for manufacturing the sensors. The advent of the silicon deep etch technique-ICP (inductively coupled plasma) technology has enabled this technology to be used for very fine, complex MEMS structure processing. By adjusting the technological parameters such as the technological air pressure, the air flow, the bias power, the etching time and the like, the high structure body-to-width ratio (more than 20:1) can be obtained. However, due to the principle of the technology, there is a "lag effect", that is, as the aspect ratio increases, the etching rate decreases, and the reason for this effect is that the transportation of the etching example to the etched surface, the products escaping from the etched surface, and the like is difficult; shielding of ions and neutral ions; the distribution of the electric field on the etched surface changes; difficulty in surface diffusion, and the like. For observing the etching depth of a micro-sized (< 5 μm) structure, it is now common practice to scribe the microstructure at the etched place using a scribing tool, and then observe and measure it under SEM (scanning electron microscope). Because the microstructure has small mechanical rigidity, the scribing method has the problems of difficult operation, difficult positioning, structural damage and incapability of continuing etching after scribing, so that the method has large measurement error and is inconvenient for continuously carrying out process tests of etching, observing and re-etching. The etching depth uniformity under the condition can only adopt a mode of repeatedly dividing and measuring by taking multiple measuring points, and the method is time-consuming and labor-consuming.
Disclosure of Invention
The invention aims to solve the problems that the existing method for detecting the depth and uniformity of an etching micro-size silicon microstructure by an ICP process has large measurement error, is inconvenient to continuously etch and wastes time and labor, and provides a method for detecting the etching depth and uniformity of the micro-size silicon microstructure by the ICP process.
The invention relates to a method for detecting micro-size etching depth and uniformity of an ICP process, which comprises the following specific steps:
step one, determining the etching depth of the back surface of a wafer according to the depth-to-width ratio rule of etching lines and the width of the pattern lines to be etched by an ICP process;
etching the back surface of each unit of the wafer by an anisotropic wet method to form a slope structure with an angle of 54.74 degrees according to the etching depth determined in the first step;
aligning the region to be etched with the slope structure through a double-sided photoetching alignment technology;
step four, etching a fixed line width structure in a region to be etched of the wafer by adopting an ICP process, after etching is completed, observing whether the slope structure on the back of the wafer has etched transparent lines, if so, executing step five, otherwise, continuing etching until the etched transparent structure is generated, and executing step five;
and fifthly, after the etching time T is continued, judging whether a new etching structure is generated, if so, continuing to etch the time T, judging whether a new etching structure is generated again, until no new etching structure is generated after the time T, and calculating the maximum depth of the ICP process in the etching width by utilizing the etching depth corresponding to the etching structure which finally appears.
And step six, calculating the etching uniformity of the ICP process in the width by using the etching depths of the different wafer unit lines.
Further, in the first step, the method for determining the etching depth of the back surface of the wafer according to the aspect ratio rule of the etching line of the ICP process comprises the following steps:
and estimating the shortest distance of the etching depth of the line to be detected according to the depth-to-width ratio rule of the etching line of the ICP process, so that the etching depth of the back surface of the wafer=the thickness of the wafer-the estimated shortest distance of the etching depth of the line to be detected.
Further, in the fifth step, the method for calculating the maximum depth of the ICP process in the etching width by using the etching depth corresponding to the last etched-through structure includes:
wherein N is the number of lines from the line corresponding to the bottom angle position of the inclined plane to the last etched line in the region to be etched, L Line(s) For the width of the line L Spacing of For line spacing, H Etching Depth of etching H Sheet thickness Is the wafer thickness.
Further, in the step six, the etching depth of different wafer unit lines is utilized, and the uniformity method of the ICP process in the aspect ratio etching is calculated as follows:
finally etching the line A and the line B by using different units of the wafer, and etching the depth difference H AB And (3) performing calculation:
wherein H is AB Is the depth difference of etching between the line A and the line B, H A For the etching depth of A lines, H B Is the etching depth of the line B; when etching depth difference H AB The uniformity was best at 0.
The invention can simply and conveniently measure the maximum depth value and the etching depth uniformity which can be achieved by adopting the ICP technology to process the micro-sized silicon microstructure. The process scheme is simple and the operation is easy. Meanwhile, the method provides possibility for automatic test of wafer level etching depth uniformity measurement, namely, if the number of the whole immediate through structure can be scanned and extracted, the automatic test of the etching depth of the whole wafer can be realized, the wafer does not need to be cut, and the detection of the depth can be realized while etching is performed.
Drawings
FIG. 1 is a schematic view of a 54.74 degree ramp structure etched from the back of a wafer in accordance with the present invention;
FIG. 2 is a schematic diagram of a region to be etched;
FIG. 3 is a schematic diagram of an ICP etched wafer without etching through;
FIG. 4 is a schematic diagram of a line etch through occurring during ICP etching of a wafer;
FIG. 5 is a schematic diagram of two lines in the ICP etching process;
FIG. 6 is a schematic illustration of the sizing of an ICP etched wafer;
fig. 7 is a schematic diagram of etching a wafer using the method of the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The first embodiment is as follows: the following describes a method for detecting micro-dimension etching depth and uniformity of an ICP process according to the present embodiment with reference to fig. 1 to 6, wherein the method comprises the following steps:
step one, determining the etching depth of the back surface of a wafer according to the depth-to-width ratio rule of etching lines and the width of the pattern lines to be etched by an ICP process;
etching the back surface of each unit of the wafer by an anisotropic wet method to form a slope structure with an angle of 54.74 degrees according to the etching depth determined in the first step;
aligning the region to be etched with the slope structure through a double-sided photoetching alignment technology;
step four, etching a fixed line width structure in a region to be etched of the wafer by adopting an ICP process, after etching is completed, observing whether the slope structure on the back of the wafer has etched transparent lines, if so, executing step five, otherwise, continuing etching until the etched transparent structure is generated, and executing step five;
and fifthly, after the etching time T is continued, judging whether a new etching structure is generated, if so, continuing to etch the time T, judging whether a new etching structure is generated again, until no new etching structure is generated after the time T, and calculating the maximum depth of the ICP process in the etching width by utilizing the etching depth corresponding to the etching structure which finally appears.
And step six, calculating the etching uniformity of the ICP process in the width by using the etching depths of the different wafer unit lines.
The invention can be used for placing a 4-inch wafer with the thickness of 400 mu m, wherein the front surface of the wafer can be used for placing a pattern with the size of 282 mu m (thickness/sqrt (2)), and at least 28 units (considering the space and the structure equal width to be 5 mu m) can be placed for a micro-size structure (less than 5 mu m), and the etching depth step is about 7 mu m (5 times sqrt (2)), so that the requirement of etching observation can be met. The pattern to be etched is aligned to the ramp structure by double sided alignment lithography (see fig. 2). Then carrying out ICP process on the micro-sized pattern to process the micro-structure (as shown in figure 3), taking out the wafer after the process is finished, observing the condition of the etching observation surface to see whether the etched structure is generated or not, and continuing etching until the etched structure is generated if the etched structure is not generated; if there is (as in fig. 4), continuing etching until there is no new etched-through structure (as in fig. 5) after a sufficient time (obtained by multiplying the step value and the etching rate of the etching depth by 2 times), the etching depth corresponding to the etched-through structure appearing last is the maximum depth that can be achieved by the process under the line size. The etch depth uniformity may be calculated by observing the number of etched-through structures produced at different locations on the wafer.
Further, in the first step, the method for determining the etching depth of the back surface of the wafer according to the aspect ratio rule of the etching line of the ICP process comprises the following steps:
and estimating the shortest distance of the etching depth of the line to be detected according to the depth-to-width ratio rule of the etching line of the ICP process, so that the etching depth of the back surface of the wafer=the thickness of the wafer-the estimated shortest distance of the etching depth of the line to be detected.
In the embodiment, the other angle slope surface of the monocrystalline silicon material has a very low KOH wet etching rate, and the included angle formed between crystal faces is 54.74 degrees, so that the observation rate can be accelerated by adopting the slope with the angle of 54.74 degrees as the observation slope.
Further, in the fifth step, the method for calculating the maximum depth of the ICP process in the etching width by using the etching depth corresponding to the last etched-through structure includes:
wherein N is the number of lines from the line corresponding to the bottom angle position of the inclined plane to the last etched line in the region to be etched, L Line(s) For the width of the line L Spacing of For line spacing, H Etching Depth of etching H Sheet thickness Is the wafer thickness.
Further, in the step six, the etching depth of different wafer unit lines is utilized, and the uniformity method of the ICP process in the aspect ratio etching is calculated as follows:
finally etching the line A and the line B by using different units of the wafer, and etching the depth difference H AB And (3) performing calculation:
wherein H is AB Is the depth difference of etching between the line A and the line B, H A For the etching depth of A lines, H B Is the etching depth of the line B; when etching depth difference H AB The uniformity was best at 0.
The line a and the line B in this embodiment are the last etched lines of different wafer units, respectively.
Specific examples: the present embodiment is described with reference to fig. 7;
selecting 400 mu m thick monocrystalline silicon (100) material, oxidizing, LPCVD growing SiO2/SiN, back single-sided photoetching, forming anisotropic etching patterns, removing back SiO2/SiN by RIE, KOH anisotropic wet etching, double-sided alignment photoetching, forming micro-size etching patterns on the front side, carrying out ICP etching process on the front side by using photoresist as a mask, observing whether an etching-through structure is generated or not by using a microscope in the etching process, judging and calculating according to the above, and finally obtaining etching depth and uniformity.
The specific manufacturing steps are as follows:
1. oxidizing: an oxidation furnace of the type L4514-3/QXG was used to oxidize a thickness of 360nm.
LPCVD: silicon nitride was 600nm thick using type TS6303 LPCVD.
3. Photoetching: single-sided photolithography was performed using an EVG-620 type photolithography machine, photoresist AZ1500.
Rie: and etching the silicon by using a PHATOM II type etching machine to remove SiO2/SiN.
Wet etching with koh: a39% wt KOH solution was used and heated to 80℃and a depth of corrosion of 360 to 370. Mu.m.
6. Photoetching: double-sided alignment lithography was performed using an EVG-620 type lithography machine, photoresist AZ1500.
7. Back ICP etching: using AZ1500 photoresist as a mask, processing was performed using an Alcatel 601E type ICP etcher.
8. Checking: STM-6OLYMPUS measurement microscope was used to simultaneously turn on the front and back light sources to see if there was structure penetration.
9. The etch depth and uniformity were calculated according to the method described above.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the different dependent claims and the features described herein may be combined in ways other than as described in the original claims. It is also to be understood that features described in connection with separate embodiments may be used in other described embodiments.
Claims (3)
1. A method for detecting micro-size etching depth and uniformity of an ICP process is characterized by comprising the following specific steps:
step one, determining the etching depth of the back surface of a wafer according to the depth-to-width ratio rule of etching lines and the width of the pattern lines to be etched by an ICP process;
etching the back surface of each unit of the wafer to form an inclined surface with an angle of 54.74 degrees by adopting an anisotropic wet method according to the etching depth determined in the first step;
step three, the region to be etched corresponds to the inclined plane through a double-sided photoetching alignment technology;
step four, etching a fixed line width structure in a region to be etched of the wafer by adopting an ICP process, after etching is finished, observing whether an inclined plane on the back of the wafer has an etched transparent line, if so, executing step five, otherwise, continuing etching until the etched transparent structure is generated, and executing step five;
step five, after continuing etching time T, judging whether a new etching structure is generated, if so, continuing etching time T, judging whether a new etching structure is generated again, until no new etching structure is generated after time T, and calculating the maximum depth of the ICP process in the etching width by utilizing the etching depth corresponding to the etching structure appearing last;
the method for calculating the maximum depth of the ICP process in the etching width by utilizing the etching depth corresponding to the finally-appearing etched-through structure comprises the following steps:
wherein N is the number of lines from the line corresponding to the bottom angle position of the inclined plane to the last etched line in the region to be etched, L Line(s) For the width of the line L Spacing of For line spacing, H Etching To etch depth H Sheet thickness Is the thickness of the wafer;
and step six, calculating the etching uniformity of the ICP process in the width by using the etching depths of the different wafer unit lines.
2. The method for detecting micro-scale etching depth and uniformity of an ICP process according to claim 1, wherein in the first step, the method for determining the etching depth of the back surface of the wafer according to the aspect ratio rule of the etching line of the ICP process comprises:
and estimating the shortest distance of the etching depth of the line to be detected according to the depth-to-width ratio rule of the etching line of the ICP process, so that the etching depth of the back surface of the wafer=the thickness of the wafer-the estimated shortest distance of the etching depth of the line to be detected.
3. The method for detecting micro-scale etching depth and uniformity of an ICP process according to claim 2, wherein in step six, the etching depth of different wafer unit lines is used to calculate the uniformity of the ICP process in the aspect ratio etching process by:
finally etching the line A and the line B by using different units of the wafer, and etching the depth difference H AB Meter for measuringAnd (3) calculating:
wherein H is AB Is the depth difference of etching between the line A and the line B, H A For the etching depth of A lines, H B Is the etching depth of the line B; when etching depth difference H AB The uniformity was best at 0.
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| CN102446749A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Method for achieving accurate graphic positioning during observation using scanning electron microscope |
| CN105304514A (en) * | 2014-07-18 | 2016-02-03 | 中国科学院微电子研究所 | Process monitoring method after semiconductor deep hole etching |
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| CN102446749A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Method for achieving accurate graphic positioning during observation using scanning electron microscope |
| CN105304514A (en) * | 2014-07-18 | 2016-02-03 | 中国科学院微电子研究所 | Process monitoring method after semiconductor deep hole etching |
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