CN112667535A - STBUS cascade communication method and communication system - Google Patents
STBUS cascade communication method and communication system Download PDFInfo
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Abstract
The application discloses an STBUS cascade communication method and a communication system, which can realize data transmission interaction capacity and real-time performance of STBUS cascade communication among a plurality of chassis. The method comprises the following steps: when a target function board card of a target 3U case detects clock synchronization information through an STBUS bus, acquiring a board card mark of the target function board card; judging whether a terminal exists in the target 3U case or not according to the board card mark; if the target 3U case has a terminal, sending data according to clock synchronization information generated by the target 3U case; and if the target 3U case does not have the terminal, sending data according to the clock synchronization information of the STBUS cascade case received by the target 3U case, wherein the STBUS cascade case is the 3U case with the terminal.
Description
Technical Field
The invention relates to the field of communication, in particular to an STBUS cascade communication method and a communication system.
Background
Currently, communication schemes are an indispensable key part in various fields. The communication schemes are various in types and functions, and when a communication operation is performed once, a plurality of communication devices (for example, various types of boards in a 3U chassis) are often required to be matched with each other to complete the communication operation. Various boards to be matched with each other may not be in the same chassis, but may be distributed in three or four chassis, and an efficient and stable communication cascade scheme between 3U chassis is necessary. U is a Unit indicating the external size of the server, and is an abbreviation of Unit, and the detailed size is determined by the american Electronic Industries Association (EIA) which is a group in the industry. Height 1U-1.75 inch-4.445 cm; the width is 4.826cm for 19 inches, and 3U is a multiple of 1U. With more and more use scenes, more communication function boards are put into the 3U case for use.
The existing Serial communication BUS (STBUS) communication scheme in the 3U chassis is only suitable for communication among all boards in a single chassis, and is difficult to realize when a plurality of chassis need to communicate with each other in real time.
Disclosure of Invention
The invention aims to provide an STBUS cascade communication method and a communication system, which can realize the data transmission interaction capacity and the real-time performance of the STBUS cascade communication among a plurality of chassis.
The first aspect of the present invention provides an STBUS cascade communication method, which is applied to an STBUS cascade communication system, wherein the STBUS cascade communication system comprises at least two 3U cabinets, the 3U cabinets are cascaded through the STBUS, each 3U cabinet comprises at least one functional board card, and the method comprises:
when a target function board card of a target 3U case detects clock synchronization information through an STBUS bus, acquiring a board card mark of the target function board card;
judging whether a terminal exists in the target 3U case or not according to the board card mark;
if the target 3U case has a terminal, sending data according to clock synchronization information generated by the target 3U case;
and if the target 3U case does not have the terminal, sending data according to the clock synchronization information of the STBUS cascade case received by the target 3U case, wherein the STBUS cascade case is the 3U case with the terminal.
Further, the method also comprises the following steps:
acquiring an input clock input from the outside;
generating an STBUS clock and a synchronous signal according to a preset protocol and an input clock;
and generating clock synchronization information according to the STBUS clock and the synchronization signal, and sending the clock synchronization information to the STBUS.
Further, acquiring the board card mark of the target function board card includes:
a function board card capable of detecting clock synchronization information through an STBUS in a target 3U case is used as a target function board card, so that the target function board card sends data and board card marks to a corresponding STBUS data line;
and acquiring the board card mark of the target function board card through the STBUS data line.
Further, sending data according to the clock synchronization information generated by the target 3U chassis includes:
obtaining an STBUS clock according to clock synchronization information generated by the target 3U case;
sampling data on the STBUS data line according to the STBUS clock to obtain sampled data;
and according to a preset time slot distribution protocol, retransmitting the sampling data to the STBUS data line.
Further, the data transmission according to the clock synchronization information of the STBUS cascade connection chassis received by the target 3U chassis includes:
receiving clock synchronization information of the STBUS cascade case through the target 3U case, wherein the STBUS cascade case is a 3U case with a terminal machine;
obtaining an STBUS clock according to clock synchronization information of the STBUS cascade case;
sampling data on the STBUS data line according to the STBUS clock to obtain sampled data;
and according to a preset time slot distribution protocol, retransmitting the sampling data to the STBUS data line.
Furthermore, each 3U case comprises at least two sets of STBUS buses,
the method further comprises the following steps:
detecting whether a preset continuous number of time slots exist on a data line of a first set of STBUS buses by a functional board card in a target 3U case and detecting signals;
if the time slots with the preset continuous number have detection signals, determining that the first set of STBUS buses are normal;
if the time slots with the preset continuous number do not have detection signals, determining that the first set of STBUS is abnormal, and switching the first set of STBUS into any one set of STBUS;
when the first set of STBUS returns to normal, any one set of STBUS is switched back to the first set of STBUS.
A second aspect of the present invention provides an STBUS cascade communication system, including:
the system comprises at least two 3U cabinets, wherein the 3U cabinets are cascaded through an STBUS (standard test bus), and each 3U cabinet comprises at least one function board card and an FPGA (field programmable gate array) board;
the FPGA board is used for acquiring a board card mark of a target function board card when the target function board card of the target 3U case detects clock synchronization information through the STBUS bus;
the FPGA board is also used for judging whether the terminal exists in the target 3U case according to the board card mark;
the FPGA board is also used for sending data according to the clock synchronization information generated by the target 3U case if the target 3U case has a terminal machine;
and the FPGA board is also used for sending data according to the clock synchronization information of the STBUS cascade case received by the target 3U case if the target 3U case has no terminal, and the STBUS cascade case is the 3U case with the terminal.
Further, in the above-mentioned case,
the FPGA board is also used for acquiring an input clock input from the outside;
the FPGA board is also used for generating an STBUS clock and a synchronous signal according to a preset protocol and an input clock;
and the FPGA board is also used for generating clock synchronization information according to the STBUS clock and the synchronization signal and sending the clock synchronization information to the STBUS.
Further, in the above-mentioned case,
the FPGA board is also used for taking a function board card which can detect clock synchronization information through the STBUS bus in the target 3U case as a target function board card, so that the target function board card sends data and board card marks to a corresponding STBUS data line;
and the FPGA board is also used for acquiring the board card mark of the target function board card through the STBUS data line.
Further, in the above-mentioned case,
the FPGA board is also used for obtaining an STBUS clock according to clock synchronization information generated by the target 3U case, sampling data on the STBUS data line according to the STBUS clock to obtain sampling data, and retransmitting the sampling data to the STBUS data line according to a preset time slot distribution protocol;
or the like, or, alternatively,
the FPGA board is further used for receiving clock synchronization information of the STBUS cascade case through the target 3U case, the STBUS cascade case is the 3U case with the terminal, the STBUS clock is obtained according to the clock synchronization information of the STBUS cascade case, data on the STBUS data line are sampled according to the STBUS clock, sampled data are obtained, and the sampled data are sent to the STBUS data line again according to a preset time slot distribution protocol.
Therefore, in the STBUS cascade communication method, when the target function board card of the target 3U case detects the clock synchronization information through the STBUS bus, the board card mark of the target function board card is obtained, whether the terminal exists in the target 3U case is judged according to the board card mark, and if the terminal exists in the target 3U case, data are sent according to the clock synchronization information generated by the target 3U case; and if the target 3U case does not have the terminal, sending data according to the clock synchronization information of the STBUS cascade case received by the target 3U case, wherein the STBUS cascade case is the 3U case with the terminal. Compared with the prior art, the data transmission interaction capability and the real-time performance of the STBUS cascade communication among the multiple chassis can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart illustrating an embodiment of an STBUS cascade communication method provided by the present invention;
fig. 2 is a schematic structural diagram of an embodiment of the STBUS cascade communication system provided in the present invention.
Detailed Description
The application discloses an STBUS cascade communication method and a communication system, which can realize data transmission interaction capacity and real-time performance of STBUS cascade communication among a plurality of chassis.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In addition, the technical solutions in the embodiments of the present invention may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination of technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, an embodiment of the present invention provides an STBUS cascade communication method, including:
101. when a target function board card of a target 3U case detects clock synchronization information through an STBUS bus, acquiring a board card mark of the target function board card;
in this embodiment, the STBUS cascade communication system includes at least two 3U chassis, the 3U chassis are cascaded through the STBUS, each 3U chassis includes at least one functional board, and each functional board is connected to an FPGA (field Programmable Gate array) board, and the FPGA is a further developed product based on Programmable devices such as PAL, GAL, and the like. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited. Taking 13 functional board slots as an example, each interface of the FPGA and its function are shown in table 1 below. Typically, the STBUS bus has a rate of 8.192Mbps with a frame rate of 8K, 128 slots per frame, with 8 bits of data being transmitted per slot.
TABLE 1 FPGA INTERFACE AND ITS FUNCTIONS
When a target function board of the target 3U case detects clock synchronization information through the STBUS bus, the FPGA board can acquire a board mark ID of the target function board through each st _ in interface, and the board mark uniquely indicates one function board.
102. Judging whether a terminal exists in the target 3U case according to the board card mark, and if so, executing step 103; if not, go to step 104;
in this embodiment, whether an end machine exists in the target 3U chassis is determined according to the board card identifier, the detection time is generally within 30 seconds after the FPGA board starts working, and if an end machine exists, step 103 is executed; if no terminal exists, go to step 104. The terminal corresponds to a radio station, the general terminal occupies the most time slots to transmit data to a plurality of radio stations, and each radio station occupies a specific time slot to transmit data to the terminal, so that communication between the terminal and each radio station is formed.
103. Sending data according to clock synchronization information generated by a target 3U case;
in this embodiment, if the target 3U enclosure has an end machine, the clock synchronization information generated by the target 3U enclosure is used as the clock and synchronization information of the STBUS, and data is transmitted using the clock and synchronization information.
104. And sending data according to the clock synchronization information of the STBUS cascade case received by the target 3U case, wherein the STBUS cascade case is the 3U case with the terminal machine.
In this embodiment, if the terminal does not exist in the target 3U chassis, the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis is used as the clock and synchronization information of the STBUS to send data, and the STBUS cascade chassis is the 3U chassis in which the terminal exists.
In the embodiment of the invention, when a target function board card of a target 3U case detects clock synchronization information through an STBUS bus, a board card mark of the target function board card is obtained, whether an end machine exists in the target 3U case is judged according to the board card mark, and if the end machine exists in the target 3U case, data are sent according to the clock synchronization information generated by the target 3U case; and if the target 3U case does not have the terminal, sending data according to the clock synchronization information of the STBUS cascade case received by the target 3U case, wherein the STBUS cascade case is the 3U case with the terminal. Compared with the prior art, the data transmission interaction capability and the real-time performance of the STBUS cascade communication among the multiple chassis can be realized.
Optionally, in combination with the embodiment shown in fig. 1, in some embodiments of the present invention, further including:
acquiring an input clock input from the outside;
generating an STBUS clock and a synchronous signal according to a preset protocol and an input clock;
and generating clock synchronization information according to the STBUS clock and the synchronization signal, and sending the clock synchronization information to the STBUS.
In the embodiment of the invention, an input clock 49.152MHz input from the outside is obtained by combining the interface shown in the table 1 of the FPGA board and the function table thereof, an STBUS clock 8.192MHz and a synchronous signal are generated according to a preset protocol and the input clock, clock synchronization information is generated according to the STBUS clock and the synchronous signal, and the clock synchronization information is sent to the STBUS.
Optionally, with reference to the embodiment shown in fig. 1, in some embodiments of the present invention, acquiring the board card identifier of the target function board card includes:
a function board card capable of detecting clock synchronization information through an STBUS in a target 3U case is used as a target function board card, so that the target function board card sends data and board card marks to a corresponding STBUS data line;
and acquiring the board card mark of the target function board card through the STBUS data line.
In the embodiment of the invention, a function board card which can detect clock synchronization information through an STBUS in a target 3U case is used as a target function board card, namely the target function board card can be an end machine or a radio station, when the target function board card detects the clock synchronization information of the STBUS, data to be sent and a board card mark of the target function board card are sent to a corresponding STBUS data line, and the FPGA board obtains the board card mark of the target function board card through the STBUS data line.
Optionally, with reference to the embodiment shown in fig. 1, in some embodiments of the present invention, sending data according to clock synchronization information generated by a target 3U chassis includes:
obtaining an STBUS clock according to clock synchronization information generated by the target 3U case;
sampling data on the STBUS data line according to the STBUS clock to obtain sampled data;
and according to a preset time slot distribution protocol, retransmitting the sampling data to the STBUS data line.
In the embodiment of the invention, the clock synchronization information comprises an STBUS clock and a synchronization signal, the STBUS clock is used for distributing data transmission time slots, and the synchronization signal is used for data transmission synchronization, so that when an end machine exists in a target 3U case, the STBUS clock is obtained according to the clock synchronization information generated by the target 3U case, and data on an STBUS data line is sampled according to the STBUS clock to obtain sampled data; and according to a preset time slot distribution protocol, retransmitting the sampling data to the STBUS data line.
Optionally, with reference to the embodiment shown in fig. 1, in some embodiments of the present invention, sending data according to clock synchronization information of the STBUS cascaded chassis received by the target 3U chassis includes:
receiving clock synchronization information of the STBUS cascade case through the target 3U case, wherein the STBUS cascade case is a 3U case with a terminal machine;
obtaining an STBUS clock according to clock synchronization information of the STBUS cascade case;
sampling data on the STBUS data line according to the STBUS clock to obtain sampled data;
and according to a preset time slot distribution protocol, retransmitting the sampling data to the STBUS data line.
In the embodiment of the invention, the clock synchronization information comprises an STBUS clock and a synchronization signal, the STBUS clock is used for distributing data transmission time slots, and the synchronization signal is used for data transmission synchronization, so that when no terminal exists in a target 3U case, the clock synchronization information of the STBUS cascade case is received by the target 3U case, the STBUS cascade case is the 3U case with the terminal, the STBUS clock is obtained according to the clock synchronization information of the STBUS cascade case, data on an STBUS data line is sampled according to the STBUS clock to obtain sampled data, and the sampled data is sent to the STBUS data line again according to a preset time slot distribution protocol.
Optionally, in some embodiments of the present invention, in combination with the above embodiments, each 3U chassis includes at least two STBUS buses,
the method further comprises the following steps:
detecting whether a preset continuous number of time slots exist on a data line of a first set of STBUS buses by a functional board card in a target 3U case and detecting signals;
if the time slots with the preset continuous number have detection signals, determining that the first set of STBUS buses are normal;
if the time slots with the preset continuous number do not have detection signals, determining that the first set of STBUS is abnormal, and switching the first set of STBUS into any one set of STBUS;
when the first set of STBUS returns to normal, any one set of STBUS is switched back to the first set of STBUS.
In the embodiment of the invention, the STBUS in the 3U case has a redundancy function and comprises at least two sets of STBUS, each functional board detects the 126 th time slot on the data line of the first set of STBUS, the bus is normal if 0xAA is detected on the time slot for 3 times continuously, the bus is abnormal if 0xAA is not detected for 3 times continuously, so that the second set of STBUS is used and the first set of bus is detected simultaneously, and the first set of STBUS is switched back for use if 0xAA is detected on the time slot for 3 times continuously.
Referring to fig. 2, an embodiment of the present invention provides an STBUS cascade communication system, including:
at least two 3U cabinets 201, the 3U cabinets 201 are cascaded through an STBUS, and each 3U cabinet 201 comprises at least one functional board card 202 and an FPGA board 203;
the FPGA board 203 is configured to obtain a board identifier of the target function board 202 when the target function board 202 of the target 3U chassis 201 detects clock synchronization information through the STBUS;
the FPGA board 203 is further used for judging whether the terminal exists in the target 3U case 201 according to the board card mark;
the FPGA board 203 is further configured to send data according to the clock synchronization information generated by the target 3U enclosure 201 if the target 3U enclosure 201 has an end machine;
the FPGA board 203 is further configured to send data according to the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis 201 if the target 3U chassis 201 does not have an end machine, where the STBUS cascade chassis is the 3U chassis 201 with the end machine.
In the embodiment of the invention, when a target function board card of a target 3U case detects clock synchronization information through an STBUS bus, the FPGA board 203 acquires a board card mark of the target function board card, judges whether an end machine exists in the target 3U case according to the board card mark, and sends data according to the clock synchronization information generated by the target 3U case if the end machine exists in the target 3U case; and if the target 3U case does not have the terminal, sending data according to the clock synchronization information of the STBUS cascade case received by the target 3U case, wherein the STBUS cascade case is the 3U case with the terminal. Compared with the prior art, the data transmission interaction capability and the real-time performance of the STBUS cascade communication among the multiple chassis can be realized.
It should be noted that only 2 3U chassis are shown in fig. 2, and in practical application, for example, cascade connection of 4 3U chassis is taken as an example, each 3U chassis has cascade input and cascade output, for example, the cascade output of the No. 1 3U chassis is connected to the cascade input of the No. 2 3U chassis, the cascade output of the No. 2 3U chassis is connected to the cascade input of the No. 3U chassis, the cascade output of the No. 3U chassis is connected to the cascade input of the No. 4 3U chassis, and the cascade output of the No. 4 3U chassis is connected to the cascade input of the No. 1 3U chassis, so as to form a cascade closed loop.
Alternatively, in conjunction with the embodiment shown in fig. 2, in some embodiments of the invention,
the FPGA board 203 is also used for acquiring an input clock input from the outside;
the FPGA board 203 is also used for generating an STBUS clock and a synchronous signal according to a preset protocol and an input clock;
the FPGA board 203 is further configured to generate clock synchronization information according to the STBUS clock and the synchronization signal, and send the clock synchronization information to the STBUS.
In the embodiment of the invention, an input clock 49.152MHz input from the outside is obtained by combining the interface shown in the table 1 of the FPGA board and the function table thereof, an STBUS clock 8.192MHz and a synchronous signal are generated according to a preset protocol and the input clock, clock synchronization information is generated according to the STBUS clock and the synchronous signal, and the clock synchronization information is sent to the STBUS.
Alternatively, in conjunction with the embodiment shown in fig. 2, in some embodiments of the invention,
the FPGA board 203 is also used for taking a function board card which can detect clock synchronization information through an STBUS bus in the target 3U case as a target function board card, so that the target function board card sends data and board card marks to a corresponding STBUS data line;
the FPGA board 203 is further configured to obtain a board card mark of the target function board card through the STBUS data line.
In the embodiment of the invention, a function board card which can detect clock synchronization information through an STBUS in a target 3U case is used as a target function board card, namely the target function board card can be an end machine or a radio station, when the target function board card detects the clock synchronization information of the STBUS, data to be sent and a board card mark of the target function board card are sent to a corresponding STBUS data line, and the FPGA board obtains the board card mark of the target function board card through the STBUS data line.
Alternatively, in conjunction with the embodiment shown in fig. 2, in some embodiments of the invention,
the FPGA board 203 is further used for obtaining an STBUS clock according to clock synchronization information generated by the target 3U case, sampling data on the STBUS data line according to the STBUS clock to obtain sampling data, and retransmitting the sampling data to the STBUS data line according to a preset time slot distribution protocol;
or the like, or, alternatively,
the FPGA board 203 is further used for receiving clock synchronization information of the STBUS cascade case through the target 3U case, the STBUS cascade case is the 3U case with the terminal, the STBUS clock is obtained according to the clock synchronization information of the STBUS cascade case, data on the STBUS data line are sampled according to the STBUS clock, sampled data are obtained, and the sampled data are sent to the STBUS data line again according to a preset time slot distribution protocol.
In the embodiment of the invention, the clock synchronization information comprises an STBUS clock and a synchronization signal, the STBUS clock is used for distributing data transmission time slots, and the synchronization signal is used for data transmission synchronization, so that when an end machine exists in a target 3U case, the STBUS clock is obtained according to the clock synchronization information generated by the target 3U case, and data on an STBUS data line is sampled according to the STBUS clock to obtain sampled data; according to a preset time slot distribution protocol, the sampled data is sent to the STBUS data line again; or, the clock synchronization information includes an STBUS clock and a synchronization signal, the STBUS clock is used for distributing data transmission time slots, and the synchronization signal is used for data transmission synchronization, so when no terminal exists in the target 3U case, the clock synchronization information of the STBUS cascade case is received by the target 3U case, the STBUS cascade case is the 3U case with the terminal, the STBUS clock is obtained according to the clock synchronization information of the STBUS cascade case, the data on the STBUS data line is sampled according to the STBUS clock to obtain sampled data, and the sampled data is sent to the STBUS data line again according to a preset time slot distribution protocol.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The STBUS cascade communication method is applied to an STBUS cascade communication system, the STBUS cascade communication system comprises at least two 3U cases, the 3U cases are cascaded through the STBUS, each 3U case comprises at least one functional board card, and the method comprises the following steps:
when a target function board card of a target 3U case detects clock synchronization information through an STBUS bus, acquiring a board card mark of the target function board card;
judging whether the target 3U case has an end machine or not according to the board card mark;
if the target 3U case has a terminal, sending data according to clock synchronization information generated by the target 3U case;
and if the target 3U case does not have the terminal, sending data according to the clock synchronization information of the STBUS cascade case received by the target 3U case, wherein the STBUS cascade case is the 3U case with the terminal.
2. The method of claim 1, further comprising:
acquiring an input clock input from the outside;
generating an STBUS clock and a synchronous signal according to a preset protocol and the input clock;
and generating clock synchronization information according to the STBUS clock and the synchronization signal, and sending the clock synchronization information to the STBUS.
3. The method according to claim 2, wherein the obtaining of the board identifier of the target function board comprises:
taking a function board card which can detect the clock synchronization information through the STBUS bus in the target 3U case as a target function board card, and enabling the target function board card to send data and board card marks to a corresponding STBUS data line;
and acquiring the board card mark of the target function board card through the STBUS data line.
4. The method of claim 3, wherein the sending data according to the clock synchronization information generated by the target 3U chassis comprises:
obtaining an STBUS clock according to the clock synchronization information generated by the target 3U case;
sampling data on the STBUS data line according to the STBUS clock to obtain sampled data;
and according to a preset time slot distribution protocol, retransmitting the sampling data to the STBUS data line.
5. The method of claim 3, wherein the sending data according to the clock synchronization information of the STBUS cascaded chassis received by the target 3U chassis comprises:
receiving clock synchronization information of an STBUS cascade case through the target 3U case, wherein the STBUS cascade case is a 3U case with a terminal machine;
obtaining an STBUS clock according to the clock synchronization information of the STBUS cascade case;
sampling data on the STBUS data line according to the STBUS clock to obtain sampled data;
and according to a preset time slot distribution protocol, retransmitting the sampling data to the STBUS data line.
6. The method of any of claims 1-5, comprising at least two sets of STBUS buses within each 3U chassis,
the method further comprises the following steps:
the function board card in the target 3U chassis detects whether a preset continuous number of time slots with detection signals exist on the data line of the first set of STBUS;
if the time slots with the preset continuous number have detection signals, determining that the first set of STBUS buses are normal;
if the time slots with the preset continuous number do not have detection signals, determining that the first set of STBUS is abnormal, and switching the first set of STBUS into any one set of STBUS;
and when the first set of STBUS returns to normal, switching any one set of STBUS back to the first set of STBUS.
7. An STBUS cascade communication system, comprising:
the system comprises at least two 3U cabinets, wherein the 3U cabinets are cascaded through an STBUS (standard test bus), and each 3U cabinet comprises at least one function board card and an FPGA (field programmable gate array) board;
the FPGA board is used for acquiring a board card mark of a target function board card when the target function board card of the target 3U case detects clock synchronization information through an STBUS bus;
the FPGA board is also used for judging whether the terminal exists in the target 3U case according to the board card mark;
the FPGA board is further used for sending data according to clock synchronization information generated by the target 3U case if the target 3U case has a terminal machine;
the FPGA board is further used for sending data according to clock synchronization information of the STBUS cascade case received by the target 3U case if the target 3U case has no terminal, and the STBUS cascade case is a 3U case with a terminal.
8. The system of claim 7,
the FPGA board is also used for acquiring an input clock input from the outside;
the FPGA board is also used for generating an STBUS clock and a synchronous signal according to a preset protocol and the input clock;
and the FPGA board is also used for generating clock synchronization information according to the STBUS clock and the synchronization signal and sending the clock synchronization information to the STBUS.
9. The system of claim 8,
the FPGA board is also used for taking a function board card which can detect the clock synchronization information through the STBUS bus in the target 3U case as a target function board card, so that the target function board card sends data and board card marks to a corresponding STBUS data line;
the FPGA board is further used for obtaining the board card mark of the target function board card through the STBUS data line.
10. The system of claim 9,
the FPGA board is further used for obtaining an STBUS clock according to clock synchronization information generated by the target 3U case, sampling data on the STBUS data line according to the STBUS clock to obtain sampling data, and retransmitting the sampling data to the STBUS data line according to a preset time slot distribution protocol;
or the like, or, alternatively,
the FPGA board is further used for receiving clock synchronization information of the STBUS cascade case through the target 3U case, the STBUS cascade case is a 3U case with a terminal, an STBUS clock is obtained according to the clock synchronization information of the STBUS cascade case, data on the STBUS data line are sampled according to the STBUS clock, sampled data are obtained, and the sampled data are sent to the STBUS data line again according to a preset time slot distribution protocol.
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