CN112653471B - Digital second-order integral modulator for capacitance detection - Google Patents
Digital second-order integral modulator for capacitance detection Download PDFInfo
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Abstract
The invention relates to a digital second-order integral modulator for capacitance detection, comprising: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator; the first-stage integral modulation module receives the capacitance signal, performs mismatch adjustment on the capacitance signal, then performs conversion from the capacitance signal to the voltage signal, forms a voltage signal, and sends the voltage signal to the second-stage integral modulation module; the second-stage integral modulation module integrates the signal output by the first-stage integral modulation module to obtain an integrated voltage signal, the integrated voltage signal is sent to the comparator, the comparator compares the integrated voltage signal with a reference signal, a comparison result is output, a 1-bit digital code stream is formed, and the 1-bit digital code stream is used as the output of the digital second-order integral modulator circuit for capacitance detection, so that high-precision capacitance-to-digital signal conversion is realized.
Description
Technical Field
The invention relates to a digital second-order integral modulator for capacitance detection, belonging to the technical field of integrated circuits.
Background
The capacitance sensor is widely applied to measurement scenes such as acceleration, pressure, position and the like, the capacitance value to be measured is generally in the pF magnitude or even smaller fF magnitude, and in many cases, the signal capacitance is much smaller than the parasitic capacitance value in a measurement circuit, so that the capacitance value reading circuit has higher requirements.
The conventional CMOS process has difficulty in realizing very high signal processing precision, and the parameter values of on-chip elements such as resistors, capacitors and the like still have deviation of 10% or even more, so that the high-precision circuit design is very challenging, and the circuit design may need very special processes and technologies such as laser correction, automatic circuit correction and the like. In addition, as the feature size of the process is reduced, the short channel effect and carrier mobility saturation equivalent of the CMOS field effect transistor are increasingly developed, so that the intrinsic gain of the transistor is deteriorated, and more noise is generated than in the case of a long channel. The reduction of the supply voltage also increases the design difficulty of the analog circuit, so that classical circuits, such as a structure that increases the gain of the op-amp through transistor cascading, cannot be used in a low voltage environment. A new circuit structure must be adopted, and this structure can meet the requirements of low voltage, large signal amplitude, low noise, and the like.
Disclosure of Invention
The technical problems solved by the invention are as follows: the capacitor to be tested is used as an input capacitance value of the modulator, and the capacitance is directly converted into digital code stream, so that high-precision capacitance-to-digital signal conversion is realized.
The technical scheme of the invention is as follows: a digitized second order integral modulator for capacitive detection, comprising: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator;
the first-stage integral modulation module receives the capacitance signal, performs mismatch adjustment on the capacitance signal, then performs conversion from the capacitance signal to the voltage signal, forms a voltage signal, and sends the voltage signal to the second-stage integral modulation module; the second-stage integral modulation module integrates the signal output by the first-stage integral modulation module to obtain an integrated voltage signal, the integrated voltage signal is sent to the comparator, the comparator compares the integrated voltage signal with a reference signal, a comparison result is output to form a 1-bit digital code stream, and the 1-bit digital code stream is used as the output of the digital second-stage integral modulator circuit for capacitance detection and is fed back to the first-stage integral modulation module for sigma-delta modulation.
Preferably, the first-stage integral modulation module adopts a switched capacitor charge conservation principle to realize CV (capacitance voltage) conversion. Compared with the traditional CV conversion circuit, the CV conversion circuit adopting the principle of conservation of switched capacitor charge does not need a high-precision low-noise high-performance operational amplifier circuit to convert charge into voltage, and the sigma-delta modulator is adopted to realize high-precision capacitance conversion on the low-frequency noise shaping characteristic, so that the weak capacitance signal detection performance is greatly improved in a low-power consumption working mode.
Preferably, the first-stage integral modulation module uses a non-overlapping two-phase clock and a switched capacitor chopping technology to realize extrapolation of low-frequency noise of a circuit to high frequency, so that design difficulty of a front-end charge-to-voltage processing analog circuit is simplified, circuit noise processing performance is improved, and high integration of the analog circuit and a digital denoising filter circuit is facilitated.
Preferably, a 7-bit wide switched capacitor DAC is integrated in the first-stage integral modulation module, and the matching of the offset capacitance of the external sensor to be detected is realized by sharing an integrator operational amplifier and combining an in-chip high-precision capacitance network. The register is used for controlling the DAC input value to realize the capacitor offset matching from 157fF to 20pF, so that the adaptability of the capacitor detection circuit is enlarged, and the capacitance range of capacitor detection is improved.
Compared with the prior art, the invention has the advantages that:
(1) In order to meet the circuit requirement and furthest overcome the influence of the CMOS technology on the circuit performance, the invention adopts a Sigma-Delta modulation capacitance detection technology, which is a good choice. The invention adopts a second-order Sigma-Delta modulator structure as a capacitance reading circuit, and a capacitor to be measured is used as an input capacitance value of the modulator to directly convert capacitance into digital streams, thereby realizing high-precision capacitance-to-digital signal conversion.
(2) The invention belongs to the field of integrated circuits, relates to the design of a digital signal processing circuit of a capacitive sensor, and particularly relates to a processing method for picking up low-noise micro signals and improving the adaptability of the signal processing circuit and a capacitive sensor gauge head by converting capacitance change physical quantity into voltage physical quantity.
(3) The circuit of the invention provides a digital second-order integral modulator circuit for capacitance detection and a processing mode of offset capacitance adjustment of an interface part of the digital second-order integral modulator circuit and a capacitive sensor, the circuit is realized by adopting a general CMOS (complementary metal oxide semiconductor) process, and the circuit has the functional characteristics of a second-order integrator, 1bit quantization and capacitance offset correction, and realizes the purposes of low-frequency noise shaping and wide-range capacitance matching of the sensor.
Drawings
FIG. 1 is a block diagram of the structure of the present invention;
FIG. 2 is a preferred circuit diagram of a first-stage integral modulation module of the present invention;
FIG. 3 is a preferred circuit diagram of a second-stage integral modulation module of the present invention; the method comprises the steps of carrying out a first treatment on the surface of the
FIG. 4 is a preferred circuit diagram of the comparator of the present invention;
FIG. 5 is a schematic diagram of the overall preferred circuit of the present invention;
fig. 6 is a schematic diagram of a first-stage integrating modulation module capacitive offset cancellation sampling stage of the present invention.
Fig. 7 is a schematic diagram of a first-stage integral modulation module capacitance offset cancellation calculation stage according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific embodiments.
The invention relates to a digital second-order integral modulator for capacitance detection, comprising: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator; the first-stage integral modulation module receives the capacitance signal, performs mismatch adjustment on the capacitance signal, then performs conversion from the capacitance signal to the voltage signal, forms a voltage signal, and sends the voltage signal to the second-stage integral modulation module; the second-stage integral modulation module integrates the signal output by the first-stage integral modulation module to obtain an integrated voltage signal, the integrated voltage signal is sent to the comparator, the comparator compares the integrated voltage signal with a reference signal, and a comparison result is output to form a 1-bit digital code stream which is used as the output of the digital second-order integral modulator circuit for capacitance detection.
The invention discloses a second-order integral modulator circuit for CDC (capacitance-to-digital conversion) and a method for adjusting and processing offset capacitance of an interface part of the second-order integral modulator circuit and a capacitance sensor. The high oversampling rate sigma-delta modulator is adopted to realize the movement of low-frequency noise of the circuit, so that the key problem of improving the resolution of capacitance measurement is solved, and the jitter of output noise of capacitance measurement is reduced; the adaptive matching of the same circuit to the heads of different capacitive sensors is realized through the offset elimination capacitive array, and the problem of yield reduction caused by the non-uniformity of the capacitive sensor process is solved. Compared with the traditional discrete component capacitance detection circuit, the circuit has the advantages of high precision, small volume, low power consumption, easy use and the like.
The invention relates to a digital second-order integral modulator for capacitance detection, which comprises the following components as shown in figure 1: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator;
the first-stage integral modulation module receives the capacitance signal, performs mismatch adjustment on the capacitance signal, then performs conversion from the capacitance signal to the voltage signal, forms a voltage signal, and sends the voltage signal to the second-stage integral modulation module; the second-stage integral modulation module integrates the signal output by the first-stage integral modulation module to obtain an integrated voltage signal, the integrated voltage signal is sent to the comparator, the comparator compares the integrated voltage signal with a reference signal, and a comparison result is output to form a 1-bit digital code stream which is used as the output of the digital second-order integral modulator circuit for capacitance detection.
The first-stage integral modulation module is preferably implemented in detail in fig. 2. The module is composed of input capacitors CINP and CINN to be detected; reference voltage source input capacitances CP1, CP2, CP3, CP4, CN1, CN2, CN3, CN4; mismatch capacitance calibration capacitances CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6, and CDB0, CDB1, CDB2, CDB3, CDB4, CDB5, CDB6; process non-ideality repair capacitors CP5, CP6, CP7, CP8, CN5, CN6, CN7, CN8, first-stage integrator coefficient capacitors CP9, CN9; switches K0, K1, K0', K1', k0_00, k00_0, k00_1, k1_00, KDA0, KDA1, KDA2, KDA3, KDA4, KDA5, KDA6, KDA7 and KDB0, KDB1, KDB2, KDB3, KDB4, KDB5, KDB6, KDB7; an integrator operational amplifier AMP1; COM terminal high level signal VIH, low level signal VIL, chip common mode signal VI, etc.
The left end of the capacitor CINP is respectively connected with a K1 'switch and a K0' switch, and the right end of the capacitor CINP is respectively connected with the K1 switch and the K0 switch; the left end of the capacitor CINN is respectively connected with the K1 'switch and the K0' switch, and the right end of the capacitor CINN is respectively connected with the K1 switch and the K0 switch.
The left end of the capacitor CP1 is respectively connected with a K1 'switch and a K0' switch, and the right end is respectively connected with a K1_00 switch, a K00_1 switch and a K0 switch; the upper end of the capacitor CP2 is respectively connected with K1_00, K00_1 and K0 switches, and the lower end is connected with a VI common mode signal. The left end of the capacitor CP3 is respectively connected with a K1 'switch and a K0' switch, and the right end is respectively connected with a K0_00 switch, a K00_0 switch and a K1 switch; the upper end of the capacitor CP4 is respectively connected with K0_00, K00_0 and K1 switches, and the lower end is connected with a VI common mode signal. The left end of the capacitor CN1 is respectively connected with a K1 'switch and a K0' switch, and the right end is respectively connected with a K1_00 switch, a K00_1 switch and a K0 switch; the upper end of the capacitor CN2 is connected with a VI common mode signal, and the lower end of the capacitor CN2 is respectively connected with K1_00, K00_1 and K0 switches. The left end of the capacitor CN3 is respectively connected with a K1 'switch and a K0' switch, and the right end is respectively connected with a K0_00 switch, a K00_0 switch and a K1 switch; the upper end VI of the capacitor CN4 is in common mode signal, and the lower end is respectively connected with K0_00, K00_0 and K1 switches.
The left end of the capacitor CDA0 is connected with the K0', K1' switches, and the right end is connected with the KDA0 switch; the left end of the CDA1 is connected with K0', K1' switches, and the right end is connected with the KDA1 switch; the left end of the CDA2 is connected with K0', K1' switches, and the right end is connected with a KDA2 switch; the left end of the CDA3 is connected with K0', K1' switches, and the right end is connected with a KDA3 switch; the left end of the CDA4 is connected with K0', K1' switches, and the right end is connected with a KDA4 switch; the left end of the CDA5 is connected with K0', K1' switches, and the right end is connected with a KDA5 switch; the left end of the CDA6 is connected with K0', K1' switches, and the right end is connected with a KDA6 switch; the left end of the capacitor CDB0 is connected with the K0', K1' switches, and the right end is connected with the KDB0 switch; the left end of CDB1 is connected with K0', K1' switches, and the right end is connected with KDB1 switch; the left end of the CDB2 is connected with K0', K1' switches, and the right end is connected with a KDB2 switch; the left end of CDB3 is connected with K0', K1' switches, and the right end is connected with KDB3 switch; the left end of CDB4 is connected with K0', K1' switches, and the right end is connected with KDB4 switches; the left end of the CDB5 is connected with K0', K1' switches, and the right end is connected with a KDB5 switch; the left end of CDB6 is connected with K0', K1' switches, and the right end is connected with KDB6 switches.
The left end of the capacitor CP5 is connected with the K0 and K1 switches, and the right end is connected with the K0 'and K1' switches; the left end of the capacitor CP6 is connected with the K0 and K1 switches, and the right end is connected with the K0 'and K1' switches; the upper end of the capacitor CP7 is connected with the K0 and K1 switches, and the lower end is connected with the K0 'and K1' switches; the upper end of the capacitor CP8 is connected with the K0 and K1 switches, and the lower end is connected with the K0 'and K1' switches; the left end of the capacitor CN5 is connected with the K0 and K1 switches, and the right end is connected with the K0 'and K1' switches; the left end of the capacitor CN6 is connected with the K0 and K1 switches, and the right end is connected with the K0 'and K1' switches; the lower end of the capacitor CN7 is connected with the K0 and K1 switches, and the upper end is connected with the K0 'and K1' switches; the lower end of the capacitor CN8 is connected with the K0 and K1 switches, and the upper end is connected with the K0 'and K1' switches.
The left end of the capacitor CP9 is connected with K0, K1, K0', K1', K0_00, K00_0, K1_00 and K00_1 switches, and the right end is connected with K0, K1, K0', K1' switches; the left end of the capacitor CN9 is connected with K0, K1, K0', K1', K0_00, K00_0, K1_00 and K00_1 switches, and the right end is connected with K0, K1, K0', K1' switches;
the operational amplifier AMP1 has its input positive terminal connected to the switches K1', K0', its input negative terminal connected to the switches K1', K0', its output positive terminal connected to the switches K1', K0', and its output negative terminal connected to the switches K1', K0'.
The first-stage integral modulation module shown in fig. 2 is characterized in that the conversion from CIN and CINP capacitance values to be detected to voltage is realized by using a sigma-delta modulation mode according to the principle of conservation of charge at high-resistance input nodes VIP and VIN of a full-differential operational amplifier, CV conversion is not required by a high-precision low-noise high-performance operational amplifier circuit, high-precision capacitance conversion is realized by using a sigma-delta modulator to shape low-frequency noise, and weak capacitance signal detection performance is greatly improved in a low-power consumption working mode; the first-stage integral modulation module is provided with capacitors CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6, CDB0, CDB1, CDB2, CDB3, CDB4, CDB5 and CDB6 for calibrating mismatch capacitance of capacitors CINN and CINP to be detected; the first-stage integral modulation is also provided with chopping switches K0', K1' at the input end and the output end of the operational amplifier AMP1, and the influence of low-frequency noise on CV conversion is reduced by utilizing a chopping effect. In summary, the first-stage integral modulation module completes the first-stage voltage integration while considering CV conversion and input offset capacitance calibration of the chopping function.
The second-stage integral modulation module is preferably shown in fig. 3, and the second-stage integral modulation module consists of second-stage integrator capacitors CP10, CP12, CN10 and CN12; switches K0, K1, K0', K1'; an integrator operational amplifier AMP2; the first-stage integral modulation output signals VON1 and VOP1, the chip common mode signal VI and the like.
The left end of the capacitor CP10 is connected with the K0', K1' switches, and the right end is connected with the K0 and K1 switches; the left end of the capacitor CN10 is connected with the K0', K1' switches, and the right end is connected with the K0 and K1 switches;
the left end of the capacitor CP12 is connected with the K0 and K1 switches and the input positive end of the operational amplifier AMP2, and the right end is connected with the output negative end of the operational amplifier AMP2; the left end of the capacitor CN12 is connected with the K0 and K1 switches and the input negative end of the operational amplifier AMP2, and the right end is connected with the output positive end of the operational amplifier AMP2;
the input positive end of the operational amplifier AMP2 is connected with the left ends of the switches K1 and K0 and the capacitor CP12, and the input negative end is connected with the left ends of the switches K1 and K0 and the capacitor CN12; the negative output terminal is connected with the right end of the capacitor CP12, and the positive output terminal is connected with the right end of the capacitor CN 12.
The second-stage integral modulation circuit samples and integrates signals VON1 and VOP1 output by the first-stage integral modulation to obtain outputs VON2 and VOP2 of the second-stage integral modulation circuit.
The preferred embodiment of the comparator is shown in fig. 4, and the module comprises input capacitors CP11, CP13, CN11, CN13; switches K1, K0', K1'; a 1-bit quantization comparator CMP; signals VON1 and VOP1 output by the first-stage integral modulation, and VON2 and VOP2 output by the second-stage integral modulation, and a chip common mode signal VI.
The left end of the capacitor CP11 is connected with the K0', K1' switches, and the right end of the capacitor CP is connected with the K1 switch and the input positive end of the comparator CMP; the left end of the capacitor CN11 is connected with the K0', K1' switches, and the right end is connected with the K1 switch and the negative input end of the comparator CMP;
the left end of the capacitor CP13 is connected with the K0', K1' switches, and the right end is connected with the K1 switch and the input positive end of the comparator CMP; the left end of the capacitor CN13 is connected with the K0', K1' switches, and the right end is connected with the K1 switch and the negative input end of the comparator CMP;
the comparison sums the output results of the signals VON1 and VOP1 output by the first-stage integral modulation and the output results of the signals VON2 and VOP2 output by the second-stage integral modulation, and the comparison is carried out between the two processes of sampling and calculation and the reference voltage VI to obtain a 1-bit quantized output value, namely a 1BIT DATA_OUT output value of the digital second-stage integral modulator for capacitance detection.
The invention discloses a second-order integral modulator circuit for CDC (capacitance-to-digital conversion) and a method for adjusting and processing offset capacitance of an interface part of the second-order integral modulator circuit and a capacitance sensor. The circuit is realized by integrating a switch capacitor and an adjustment register in the same chip, the movement of low-frequency noise of the circuit is realized by adopting a sigma-delta modulator with high oversampling rate, and the adaptive matching of the same circuit to the heads of different capacitance sensors is realized by controlling a switch capacitor DAC through the register. Compared with the traditional discrete component capacitance detection circuit, the circuit has the advantages of high precision, small volume, low power consumption and the like.
The digital capacitance detection second-order integral modulator circuit disclosed by the invention only needs two fully differential CMOS operational amplifiers, one CMOS comparator and a switch to match with corresponding non-overlapping clocks, realizes CV conversion of capacitance detection and completes integration and modulation of voltage signals, and reduces operational amplifier noise index design requirements by utilizing signal processing characteristics of the modulator, thereby improving capacitance-to-digital conversion accuracy.
The digital capacitance detection second-order integral modulator circuit disclosed by the invention utilizes the built-in capacitance array network to realize the adjustment of the common-mode bias point of the capacitance, eliminates output imbalance of the capacitance sensor caused by processing errors, greatly improves the matching rate of the signal processing circuit and the capacitance sensor, and is beneficial to the engineering of the miniaturized MEMS capacitance sensor.
The invention provides a digital second-order integral modulator circuit for capacitance detection and a processing method for offset capacitance adjustment of an interface part of the digital second-order integral modulator circuit and a capacitive sensor, wherein the circuit is realized by adopting a general CMOS (complementary metal oxide semiconductor) process, and fig. 5 is a general schematic diagram of a preferred scheme of the invention, and the schematic diagram is a cascading sum of fig. 2, 3 and 4, and names of each component in the diagram and the diagram correspond to each other one by one. The circuit has the functional characteristics of a second-order integrator, 1bit quantization and capacitance offset correction, and achieves the purposes of low-frequency noise shaping and wide-range capacitance matching of the sensor.
The invention provides a method for adjusting and processing offset capacitance of a capacitive sensor interface part, as shown in fig. 6 and 7, wherein the two diagrams respectively show the working processes of sampling and calculating stages. Capacitor arrays CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6, CDB0, CDB1, CDB2, CDB3, CDB4, CDB5, CDB6, CP5, CP6, CP7, CP8, CP9, CN5, CN6, CN7, CN8, CN9; operational amplifier AMP1; the switches K0', K1', K0, K1, KDA0, KDA1, KDA2, KDA3, KDA4, KDA5, KDA6, KDA7 and KDB0, KDB1, KDB2, KDB3, KDB4, KDB5, KDB6, KDB7 form a capacitance mismatch adjustment circuit;
referring to fig. 6 and 7, the offset capacitance adjusting circuit of the capacitive sensor interface of the present invention is shown. In the mismatched charge amount sampling phase of fig. 6, both switches K1 and K1' are in the on state. The circuit charges mismatch adjustment capacitors CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6 and CDB0, CDB1, CDB2, CDB3, CDB4, CDB5 and CDB6, the circuit selects a proper number of mismatch adjustment capacitors according to the mismatch amount, and the multiplexing first-stage integrator operational amplifier AMP1 finishes the sampling of the mismatch charges and waits for the clock of the calculation stage.
In the mismatch charge amount calculation stage of fig. 7, both switches K0 and K0' are in an on state at this time. The capacitors CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6 and CDB0, CDB1, CDB2, CDB3, CDB4, CDB5 and CDB6 are respectively connected to VIN and VIP ends, and charges are respectively redistributed on VIN and VIP high-resistance nodes according to conservation principles, so that the conversion quantity of charges to voltages, which is formed due to mismatch, is calculated. The circuit can detect the mismatch quantity of the sensor capacitance when the sensor is matched, and the mismatch quantity value is used for configuring the capacitance network value of the offset capacitance adjuster, so that the function of eliminating the mismatch capacitance of the sensor is achieved, and the matching range of the capacitance digital signal processing circuit to the sensor is widened.
The circuit is matched with a sandwich differential capacitive MEMS accelerometer for testing, the lowest point of the ALLAN variance of the accelerometer is smaller than 2ug, and the zero bias stability of the accelerometer is smaller than 20ug in 1 hour when the accelerometer is 0 g. The test result shows that the circuit has the capacitance resolution of 4aF, and reaches the advanced level in China and the world.
Claims (4)
1. A digitized second order integral modulator for capacitive detection, comprising: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator;
the first-stage integral modulation module receives the capacitance signal, performs mismatch adjustment on the capacitance signal, then performs conversion from the capacitance signal to the voltage signal, forms a voltage signal, and sends the voltage signal to the second-stage integral modulation module; the second-stage integral modulation module integrates the signal output by the first-stage integral modulation module to obtain an integrated voltage signal, the integrated voltage signal is sent to the comparator, the comparator compares the integrated voltage signal with a reference signal, a comparison result is output to form a 1-bit digital code stream, and the 1-bit digital code stream is used as the output of the digital second-stage integral modulator circuit for capacitance detection and is fed back to the first-stage integral modulation module for sigma-delta modulation;
the first-stage integral modulation module comprises input capacitors CINP and CINN to be detected; reference voltage source input capacitances CP1, CP2, CP3, CP4, CN1, CN2, CN3, CN4; mismatch capacitance calibration capacitances CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6, and CDB0, CDB1, CDB2, CDB3, CDB4, CDB5, CDB6; process non-ideality repair capacitors CP5, CP6, CP7, CP8, CN5, CN6, CN7, CN8, first-stage integrator coefficient capacitors CP9, CN9; switches K0, K1, K0', K1', k0_00, k00_0, k00_1, k1_00, KDA0, KDA1, KDA2, KDA3, KDA4, KDA5, KDA6, KDA7 and KDB0, KDB1, KDB2, KDB3, KDB4, KDB5, KDB6, KDB7; an integrator operational amplifier AMP1; COM end high level signal VIH and low level signal VIL and chip common mode signal VI;
the left end of the capacitor CINP is respectively connected with a K1 'switch and a K0' switch, and the right end of the capacitor CINP is respectively connected with the K1 switch and the K0 switch; the left end of the capacitor CINN is respectively connected with a K1 'switch and a K0' switch, and the right end of the capacitor CINN is respectively connected with the K1 switch and the K0 switch;
the left end of the capacitor CP1 is respectively connected with a K1 'switch and a K0' switch, and the right end is respectively connected with a K1_00 switch, a K00_1 switch and a K0 switch; the upper end of the capacitor CP2 is respectively connected with K1_00, K00_1 and K0 switches, and the lower end is connected with a VI common mode signal; the left end of the capacitor CP3 is respectively connected with a K1 'switch and a K0' switch, and the right end is respectively connected with a K0_00 switch, a K00_0 switch and a K1 switch; the upper end of the capacitor CP4 is respectively connected with K0_00, K00_0 and K1 switches, and the lower end is connected with a VI common mode signal; the left end of the capacitor CN1 is respectively connected with a K1 'switch and a K0' switch, and the right end is respectively connected with a K1_00 switch, a K00_1 switch and a K0 switch; the upper end of the capacitor CN2 is connected with a VI common mode signal, and the lower end of the capacitor CN2 is respectively connected with K1_00, K00_1 and K0 switches; the left end of the capacitor CN3 is respectively connected with a K1 'switch and a K0' switch, and the right end is respectively connected with a K0_00 switch, a K00_0 switch and a K1 switch; the upper end VI of the capacitor CN4 is connected with common mode signals, and the lower end is respectively connected with K0_00, K00_0 and K1 switches;
the left end of the capacitor CDA0 is connected with the K0', K1' switches, and the right end is connected with the KDA0 switch; the left end of the CDA1 is connected with K0', K1' switches, and the right end is connected with the KDA1 switch; the left end of the capacitor CDA2 is connected with the K0', K1' switch, and the right end is connected with the KDA2 switch; the left end of the capacitor CDA3 is connected with the K0', K1' switch, and the right end is connected with the KDA3 switch; the left end of the capacitor CDA4 is connected with the K0', K1' switch, and the right end is connected with the KDA4 switch; the left end of the capacitor CDA5 is connected with the K0', K1' switch, and the right end is connected with the KDA5 switch; the left end of the capacitor CDA6 is connected with the K0', K1' switch, and the right end is connected with the KDA6 switch; the left end of the capacitor CDB0 is connected with the K0', K1' switches, and the right end is connected with the KDB0 switch; the left end of the capacitor CDB1 is connected with the K0', K1' switch, and the right end is connected with the KDB1 switch; the left end of the capacitor CDB2 is connected with the K0', K1' switch, and the right end is connected with the KDB2 switch; the left end of the capacitor CDB3 is connected with the K0', K1' switch, and the right end is connected with the KDB3 switch; the left end of the capacitor CDB4 is connected with the K0', K1' switch, and the right end is connected with the KDB4 switch; the left end of the capacitor CDB5 is connected with the K0', K1' switch, and the right end is connected with the KDB5 switch; the left end of the capacitor CDB6 is connected with the K0', K1' switch, and the right end is connected with the KDB6 switch;
the left end of the capacitor CP5 is connected with the K0 and K1 switches, and the right end is connected with the K0 'and K1' switches; the left end of the capacitor CP6 is connected with the K0 and K1 switches, and the right end is connected with the K0 'and K1' switches; the upper end of the capacitor CP7 is connected with the K0 and K1 switches, and the lower end is connected with the K0 'and K1' switches; the upper end of the capacitor CP8 is connected with the K0 and K1 switches, and the lower end is connected with the K0 'and K1' switches; the left end of the capacitor CN5 is connected with the K0 and K1 switches, and the right end is connected with the K0 'and K1' switches; the left end of the capacitor CN6 is connected with the K0 and K1 switches, and the right end is connected with the K0 'and K1' switches; the lower end of the capacitor CN7 is connected with the K0 and K1 switches, and the upper end is connected with the K0 'and K1' switches; the lower end of the capacitor CN8 is connected with the K0 and K1 switches, and the upper end is connected with the K0 'and K1' switches;
the left end of the capacitor CP9 is connected with K0, K1, K0', K1', K0_00, K00_0, K1_00 and K00_1 switches, and the right end is connected with K0, K1, K0', K1' switches; the left end of the capacitor CN9 is connected with K0, K1, K0', K1', K0_00, K00_0, K1_00 and K00_1 switches, and the right end is connected with K0, K1, K0', K1' switches;
the input positive end of the integrator operational amplifier AMP1 is connected with the switches K1 and K0', the input negative end is connected with the switches K1 and K0', the output positive end is connected with the switches K1 and K0', and the output negative end is connected with the switches K1 and K0';
the second-stage integral modulation module comprises second-stage integrator capacitors CP10, CP12, CN10 and CN12; switches K0, K1, K0', K1'; an integrator operational amplifier AMP2; first-stage integral modulation output signals VON1 and VOP1 and a chip common mode signal VI;
the left end of the capacitor CP10 is connected with the K0', K1' switches, and the right end is connected with the K0 and K1 switches; the left end of the capacitor CN10 is connected with the K0', K1' switches, and the right end is connected with the K0 and K1 switches;
the left end of the capacitor CP12 is connected with the K0 and K1 switches and the input positive end of the integrator operational amplifier AMP2, and the right end of the capacitor CP is connected with the output negative end of the operational amplifier AMP2; the left end of the capacitor CN12 is connected with the K0 and K1 switches and the input negative end of the integrator operational amplifier AMP2, and the right end of the capacitor CN is connected with the output positive end of the integrator operational amplifier AMP2;
the input positive end of the integrator operational amplifier AMP2 is connected with the left ends of the switches K1 and K0 and the capacitor CP12, and the input negative end is connected with the left ends of the switches K1 and K0 and the capacitor CN12; the output negative end is connected with the right end of the capacitor CP12, and the output positive end is connected with the right end of the capacitor CN12;
the second-stage integral modulation circuit samples and integrates signals VON1 and VOP1 output by the first-stage integral modulation to obtain outputs VON2 and VOP2 of the second-stage integral modulation circuit;
the comparator comprises input capacitances CP11, CP13, CN11, CN13; switches K1, K0', K1'; a 1-bit quantization comparator CMP; signals VON1 and VOP1 output by the first-stage integral modulation and VON2 and VOP2 output by the second-stage integral modulation are chip common mode signals VI;
the left end of the capacitor CP11 is connected with the K0', K1' switches, and the right end of the capacitor CP is connected with the K1 switch and the input positive end of the comparator CMP; the left end of the capacitor CN11 is connected with the K0', K1' switches, and the right end is connected with the K1 switch and the negative input end of the comparator CMP;
the left end of the capacitor CP13 is connected with the K0', K1' switches, and the right end is connected with the K1 switch and the input positive end of the comparator CMP; the left end of the capacitor CN13 is connected with the K0', K1' switches, and the right end is connected with the K1 switch and the negative input end of the comparator CMP;
and comparing and summing the output results of the signals VON1 and VOP1 output by the first-stage integral modulation and the output results of the signals VON2 and VOP2 output by the second-stage integral modulation, and comparing the two processes with a chip common mode signal VI through sampling and calculation to obtain a 1bit quantized output value.
2. A digitized second order integral modulator circuit for capacitive detection as claimed in claim 1 wherein: the first-stage integral modulation module realizes CV conversion by adopting a switched capacitor charge conservation principle, a CV conversion circuit adopting the switched capacitor charge conservation principle does not need a high-precision low-noise high-performance operational amplifier circuit to convert charge into voltage, a sigma-delta modulator is adopted to realize high-precision capacitance conversion on low-frequency noise shaping characteristics, and weak capacitance signal detection performance is greatly improved in a low-power consumption working mode.
3. A digitized second order integral modulator circuit for capacitive detection as claimed in claim 1 wherein: the first-stage integral modulation module uses a non-overlapping two-phase clock and a switched capacitor chopping technology to realize extrapolation of low-frequency noise of a circuit to high frequency, simplifies design difficulty of a front-end charge-to-voltage processing analog circuit, improves noise processing performance of the circuit, and is beneficial to high integration of the analog circuit and a digital denoising filter circuit.
4. A digitized second order integral modulator circuit for capacitive detection as claimed in claim 1 wherein: 7-bit wide switched capacitor DAC is integrated in the first-stage integral modulation module, and the matching of the offset capacitance of the external sensor is realized by sharing the high-precision capacitance network in the integrator operational amplifier combination chip; the register is used for controlling the DAC input value to realize the capacitor offset matching from 157fF to 20pF, so that the adaptability of the capacitor detection circuit is enlarged, and the capacitance range of capacitor detection is improved.
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| CN108199718A (en) * | 2018-03-30 | 2018-06-22 | 福州大学 | Capacitance sensor detection method based on Sigma-Delta modulation |
| CN109889199A (en) * | 2019-02-20 | 2019-06-14 | 哈尔滨工程大学 | A kind of Σ Δ type with chopped wave stabilizing and SAR type mixed type ADC |
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| CN108199718A (en) * | 2018-03-30 | 2018-06-22 | 福州大学 | Capacitance sensor detection method based on Sigma-Delta modulation |
| CN109889199A (en) * | 2019-02-20 | 2019-06-14 | 哈尔滨工程大学 | A kind of Σ Δ type with chopped wave stabilizing and SAR type mixed type ADC |
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