CN112653471A

CN112653471A - Digital second-order integral modulator for capacitance detection

Info

Publication number: CN112653471A
Application number: CN202011502455.5A
Authority: CN
Inventors: 陈祥发; 佟晓娜; 张奇荣; 邬君
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2020-12-17
Filing date: 2020-12-17
Publication date: 2021-04-13
Anticipated expiration: 2040-12-17
Also published as: CN112653471B

Abstract

The invention relates to a digital second-order integral modulator for capacitance detection, which comprises: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator; the first-stage integral modulation module is used for receiving the capacitance signal, performing mismatch adjustment on the capacitance signal, then converting the capacitance signal into a voltage signal to form a voltage signal, and sending the voltage signal to the second-stage integral modulation module; the second-stage integral modulation module integrates the signal output by the first-stage integral modulation module to obtain an integrated voltage signal, the integrated voltage signal is sent to the comparator, the comparator compares the integrated voltage signal with a reference signal, a comparison result is output, a 1-bit digital code stream is formed and serves as the output of the digital second-stage integral modulator circuit for capacitance detection, and high-precision capacitance-to-digital signal conversion is achieved.

Description

Digital second-order integral modulator for capacitance detection

Technical Field

The invention relates to a digital second-order integral modulator for capacitance detection, belonging to the technical field of integrated circuits.

Background

The capacitance sensor is widely applied to measurement scenes such as acceleration, pressure and position, the capacitance value to be measured is generally in a pF magnitude order or even a smaller fF magnitude order, and the signal capacitance is much smaller than the parasitic capacitance value in a measurement circuit in many cases, so that the requirement on a capacitance value reading circuit is higher.

The conventional CMOS process is difficult to realize high signal processing accuracy, and the parameter values of on-chip elements such as resistors and capacitors still have a deviation of 10% or more, so that the high-precision circuit design is very challenging, and the circuit design may require very special processes and techniques such as laser correction and automatic circuit correction. In addition, as the process feature size decreases, the short channel effect, carrier mobility saturation, and the like of the CMOS field effect transistor should increasingly appear, so that the intrinsic gain of the transistor becomes worse while generating more noise than in the case of a long channel. The reduction of the power supply voltage also increases the design difficulty of the analog circuit, so that the classical circuit, such as a structure for increasing the gain of the operational amplifier through transistor cascade, cannot be used in a low-voltage environment. A new circuit structure must be adopted which can simultaneously satisfy the requirements of low voltage, large signal amplitude, low noise and the like.

Disclosure of Invention

The technical problem solved by the invention is as follows: the defects of the prior art are overcome, and the digital second-order integral modulator for capacitance detection is provided.

The technical scheme of the invention is as follows: a digitized second order integrating modulator for capacitance detection, comprising: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator;

the first-stage integral modulation module is used for receiving the capacitance signal, performing mismatch adjustment on the capacitance signal, then converting the capacitance signal into a voltage signal to form a voltage signal, and sending the voltage signal to the second-stage integral modulation module; the second-stage integral modulation module integrates the signal output by the first-stage integral modulation module to obtain an integrated voltage signal, the integrated voltage signal is sent to the comparator, the comparator compares the integrated voltage signal with a reference signal, a comparison result is output, and a 1-bit digital code stream is formed and fed back to the first-stage integral modulation module for sigma-delta modulation while being output by the second-stage integral modulation module for capacitance detection.

Preferably, the first-stage integral modulation module realizes CV (capacitance-voltage) conversion by adopting a charge conservation principle of a switched capacitor. Compared with the traditional CV conversion circuit, the CV conversion circuit adopting the charge conservation principle of the switched capacitor does not need a high-precision low-noise high-performance operational amplifier circuit to convert charges into voltages, and adopts the sigma-delta modulator to realize high-precision capacitance conversion on the low-frequency noise shaping characteristic, so that the weak capacitance signal detection performance is greatly improved in a low-power-consumption working mode.

Preferably, the first-stage integral modulation module realizes the extrapolation of low-frequency noise of the circuit to high frequency by using a non-overlapping two-phase clock and combining a switched capacitor chopping technology, simplifies the design difficulty of a front-end charge-to-voltage processing analog circuit, improves the noise processing performance of the circuit, and is favorable for the high integration of the analog circuit and the digital denoising filter circuit.

Preferably, a 7-bit-wide switch capacitor DAC is integrated in the first-stage integral modulation module, and the matching of the offset capacitance of the external sensor to be detected is realized by combining the operation and the amplification of the shared integrator and the high-precision capacitance network in the chip. The capacitance offset matching from 157fF to 20pF is realized by controlling the DAC input value through the register, the adaptability of the capacitance detection circuit is enlarged, and the capacitance value range of capacitance detection is improved.

Compared with the prior art, the invention has the advantages that:

(1) in order to meet the circuit requirements and overcome the influence of a CMOS process on the circuit performance to the maximum extent, the Sigma-Delta modulation capacitance detection technology is a good choice. The invention adopts a second-order Sigma-Delta modulator structure as a capacitance reading circuit, and a capacitor to be tested is used as an input capacitance value of the modulator, so that capacitance is directly converted into digital code streams, and high-precision capacitance-to-digital signal conversion is realized.

(2) The invention belongs to the field of integrated circuits, relates to the design of a digital signal processing circuit of a capacitive sensor, and particularly relates to a processing method for picking up low-noise tiny signals by converting capacitance change physical quantities into voltage physical quantities and improving the adaptability of the signal processing circuit and a meter head of the capacitive sensor.

(3) The circuit of the invention provides a digital second-order integral modulator circuit for capacitance detection and a processing mode for adjusting offset capacitance of an interface part of the digital second-order integral modulator circuit and a capacitance sensor, the circuit is realized by adopting a general CMOS (complementary metal oxide semiconductor) process, the circuit has the functional characteristics of a second-order integrator, 1bit quantization and capacitance offset correction, and the purposes of low-frequency noise shaping and wide-range capacitance matching of the sensor are realized.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a preferred circuit diagram of a first stage integral modulation module of the present invention;

FIG. 3 is a preferred circuit diagram of the second stage integral modulation module of the present invention; (ii) a

FIG. 4 is a preferred circuit diagram of the comparator of the present invention;

FIG. 5 is a schematic diagram of an overall preferred circuit of the present invention;

fig. 6 is a schematic diagram of the sampling phase of the first stage integral modulation module capacitance offset cancellation of the present invention.

Fig. 7 is a schematic diagram of the first stage integral modulation module capacitance imbalance elimination calculation stage of the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and specific embodiments.

The invention relates to a digital second-order integral modulator for capacitance detection, which comprises: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator; the first-stage integral modulation module is used for receiving the capacitance signal, performing mismatch adjustment on the capacitance signal, then converting the capacitance signal into a voltage signal to form a voltage signal, and sending the voltage signal to the second-stage integral modulation module; the second-stage integral modulation module integrates the signal output by the first-stage integral modulation module to obtain an integrated voltage signal, the integrated voltage signal is sent to the comparator, the comparator compares the integrated voltage signal with a reference signal, and a comparison result is output to form a 1-bit digital code stream which is used as the output of the digital second-stage integral modulator circuit for capacitance detection.

The invention discloses a second-order integral modulator circuit for CDC (capacitance-to-digital conversion) and an offset capacitance adjustment processing method of an interface part of the second-order integral modulator circuit and a capacitance sensor. The sigma-delta modulator with high oversampling rate is adopted to realize the movement of low-frequency noise of the circuit, so that the key problem of improving the resolution of capacitance measurement is solved, and the output noise jitter of the capacitance measurement is reduced; the capacitance array is eliminated through disorder, so that the adaptability matching of the same circuit to different capacitance sensor heads is realized, and the problem of yield reduction caused by the non-uniformity of the capacitance sensor process is solved. Compared with the traditional discrete component capacitance detection circuit, the circuit has the advantages of high precision, small volume, low power consumption, easy use and the like.

The invention relates to a digital second-order integral modulator for capacitance detection, which comprises the following components as shown in figure 1: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator;

the first-stage integral modulation module is used for receiving the capacitance signal, performing mismatch adjustment on the capacitance signal, then converting the capacitance signal into a voltage signal to form a voltage signal, and sending the voltage signal to the second-stage integral modulation module; the second-stage integral modulation module integrates the signal output by the first-stage integral modulation module to obtain an integrated voltage signal, the integrated voltage signal is sent to the comparator, the comparator compares the integrated voltage signal with a reference signal, and a comparison result is output to form a 1-bit digital code stream which is used as the output of the digital second-stage integral modulator circuit for capacitance detection.

The first-stage integral modulation module is shown in a preferred scheme in figure 2. The module consists of input capacitors to be detected CINP and CINN; reference voltage source input capacitances CP1, CP2, CP3, CP4, CN1, CN2, CN3, CN 4; mismatch capacitance calibration capacitances CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6 and CDB0, CDB1, CDB2, CDB3, CDB4, CDB5, CDB 6; technological nonideal repair capacitors CP5, CP6, CP7, CP8, CN5, CN6, CN7 and CN8, first-stage integrator coefficient capacitors CP9 and CN 9; switches K0, K1, K0', K1', K0_00, K00_0, K00_1, K1_00, KDA0, KDA1, KDA2, KDA3, KDA4, KDA5, KDA6, KDA7 and KDB0, KDB1, KDB2, KDB3, KDB4, KDB5, KDB6, KDB 7; an integrator op-AMP 1; and the COM end comprises a high-level signal VIH, a low-level signal VIL, a chip common-mode signal VI and the like.

The left end of the capacitor CINP is respectively connected with switches K1 'and K0', and the right end of the capacitor CINP is respectively connected with switches K1 and K0; the left end of the capacitor CINN is connected with switches K1 'and K0' respectively, and the right end of the capacitor CINN is connected with switches K1 and K0 respectively.

The left end of the capacitor CP1 is respectively connected with switches K1 'and K0', and the right end is respectively connected with switches K1_00, K00_1 and K0; the upper ends of the capacitors CP2 are respectively connected with switches K1_00, K00_1 and K0, and the lower ends are connected with VI common mode signals. The left end of the capacitor CP3 is respectively connected with switches K1 'and K0', and the right end is respectively connected with switches K0_00, K00_0 and K1; the upper ends of the capacitors CP4 are respectively connected with switches K0_00, K00_0 and K1, and the lower ends are connected with VI common mode signals. The left end of the capacitor CN1 is respectively connected with switches K1 'and K0', and the right end is respectively connected with switches K1_00, K00_1 and K0; the upper end of the capacitor CN2 is connected with a VI common mode signal, and the lower end is connected with switches K1_00, K00_1 and K0 respectively. The left end of the capacitor CN3 is respectively connected with switches K1 'and K0', and the right end is respectively connected with switches K0_00, K00_0 and K1; the upper end VI common mode signal of the capacitor CN4, and the lower end thereof are respectively connected with switches K0_00, K00_0 and K1.

The left end of the capacitor CDA0 is connected with a switch K0 'and a switch K1', and the right end is connected with a switch KDA 0; the left end of the CDA1 is connected with a K0 'switch and a K1' switch, and the right end is connected with a KDA1 switch; the left end of the CDA2 is connected with a K0 'switch and a K1' switch, and the right end is connected with a KDA2 switch; the left end of the CDA3 is connected with a K0 'switch and a K1' switch, and the right end is connected with a KDA3 switch; the left end of the CDA4 is connected with a K0 'switch and a K1' switch, and the right end is connected with a KDA4 switch; the left end of the CDA5 is connected with a K0 'switch and a K1' switch, and the right end is connected with a KDA5 switch; the left end of the CDA6 is connected with a K0 'switch and a K1' switch, and the right end is connected with a KDA6 switch; the left end of the capacitor CDB0 is connected with a switch K0 'and a switch K1', and the right end is connected with a switch KDB 0; the left end of CDB1 is connected with K0 'and K1' switches, and the right end is connected with KDB1 switch; the left end of CDB2 is connected with K0 'and K1' switches, and the right end is connected with KDB2 switch; the left end of CDB3 is connected with K0 'and K1' switches, and the right end is connected with KDB3 switch; the left end of CDB4 is connected with K0 'and K1' switches, and the right end is connected with KDB4 switch; the left end of CDB5 is connected with K0 'and K1' switches, and the right end is connected with KDB5 switch; the left end of CDB6 is connected with K0 'and K1' switches, and the right end is connected with KDB6 switch.

The left end of the capacitor CP5 is connected with switches K0 and K1, and the right end thereof is connected with switches K0 'and K1'; the left end of the capacitor CP6 is connected with switches K0 and K1, and the right end thereof is connected with switches K0 'and K1'; the upper end of the capacitor CP7 is connected with switches K0 and K1, and the lower end is connected with switches K0 'and K1'; the upper end of the capacitor CP8 is connected with switches K0 and K1, and the lower end is connected with switches K0 'and K1'; the left end of the capacitor CN5 is connected with switches K0 and K1, and the right end is connected with switches K0 'and K1'; the left end of the capacitor CN6 is connected with switches K0 and K1, and the right end is connected with switches K0 'and K1'; the lower end of the capacitor CN7 is connected with a K0 switch and a K1 switch, and the upper end is connected with a K0 switch and a K1 switch; the lower end of the capacitor CN8 is connected with a switch K0 and a switch K1, and the upper end is connected with a switch K0 'and a switch K1'.

The left end of the capacitor CP9 is connected with switches K0, K1, K0', K1', K0_00, K00_0, K1_00 and K00_1, and the right end is connected with switches K0, K1, K0 'and K1'; the left end of the capacitor CN9 is connected with switches K0, K1, K0', K1', K0_00, K00_0, K1_00 and K00_1, and the right end is connected with switches K0, K1, K0 'and K1';

the operational amplifier AMP1 has its input positive terminal connected to switches K1 'and K0', its input negative terminal connected to switches K1 'and K0', its output positive terminal connected to switches K1 'and K0', and its output negative terminal connected to switches K1 'and K0'.

The first-stage integral modulation module shown in fig. 2 is characterized in that the conversion from the capacitance values of CINN and CINP to be detected to voltage is realized by using the principle of charge conservation at the high-resistance input nodes VIP and VIN of the fully differential operational amplifier in a sigma-delta modulation mode, a high-precision low-noise high-performance operational amplifier circuit is not required to perform CV conversion, a sigma-delta modulator is used for realizing high-precision capacitance conversion on the shaping characteristic of low-frequency noise, and the weak capacitance signal detection performance is greatly improved in a low-power-consumption working mode; the first-stage integral modulation module is simultaneously provided with capacitors CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6, CDB0, CDB1, CDB2, CDB3, CDB4, CDB5 and CDB6 arrays for carrying out mismatch capacitance calibration on to-be-detected capacitors CINN and CINP; the first-stage integral modulation is also provided with chopping switches K0 'and K1' at the input end and the output end of the operational amplifier AMP1, and the influence of low-frequency noise on CV conversion is reduced by utilizing a chopping effect. In conclusion, the first-stage integral modulation module completes the first-stage voltage integration while giving consideration to CV conversion of a chopping function and input offset capacitor calibration.

A second stage integral modulation module, a preferred scheme of which is shown in detail in fig. 3, is composed of second stage integrator capacitors CP10, CP12, CN10 and CN 12; switches K0, K1, K0', K1'; an integrator op-AMP 2; the first-stage integral modulation output signals VON1 and VOP1, the chip common-mode signal VI and the like.

The left end of the capacitor CP10 is connected with a switch K0 'and a switch K1', and the right end is connected with a switch K0 and a switch K1; the left end of the capacitor CN10 is connected with a switch K0 'and a switch K1', and the right end is connected with a switch K0 and a switch K1;

the left end of the capacitor CP12 is connected with input positive terminals of a K0 switch, a K1 switch and an operational amplifier AMP2, and the right end is connected with an output negative terminal of the operational amplifier AMP 2; the left end of the capacitor CN12 is connected with a K0 switch, a K1 switch and the input negative end of the operational amplifier AMP2, and the right end is connected with the output positive end of the operational amplifier AMP 2;

the input positive end of the operational amplifier AMP2 is connected with the left ends of the switches K1 and K0 and the capacitor CP12, and the input negative end is connected with the left ends of the switches K1 and K0 and the capacitor CN 12; the output negative terminal is connected with the right end of the capacitor CP12, and the output positive terminal is connected with the right end of the capacitor CN 12.

The second-stage integral modulation circuit samples and integrates the signals VON1 and VOP1 output by the first-stage integral modulation circuit to obtain the outputs VON2 and VOP2 of the second-stage integral modulation circuit.

The comparator, the preferred scheme is shown in fig. 4 in particular, the module comprises input capacitors CP11, CP13, CN11 and CN 13; switches K1, K0', K1'; a 1-bit quantization comparator CMP; signals VON1 and VOP1 output by the first-stage integral modulation, VON2 and VOP2 output by the second-stage integral modulation, a chip common-mode signal VI and the like.

The left end of the capacitor CP11 is connected with a K0 'switch and a K1' switch, and the right end is connected with a K1 switch and the positive input end of a comparator CMP; the left end of the capacitor CN11 is connected with a K0 'switch, a K1' switch and the right end is connected with a K1 switch and the negative end of the input of the comparator CMP;

the left end of the capacitor CP13 is connected with a K0 'switch and a K1' switch, and the right end is connected with a K1 switch and the positive input end of a comparator CMP; the left end of the capacitor CN13 is connected with a K0 'switch, a K1' switch and the right end is connected with a K1 switch and the negative end of the input of the comparator CMP;

the comparison is carried OUT by summing the output results of the signals VON1 and VOP1 output by the first-stage integral modulation and the output results of the signals VON2 and VOP2 output by the second-stage integral modulation, and comparing the two processes with a reference voltage VI through sampling and calculating to obtain a 1-BIT quantized output value, namely a 1-BIT DATA _ OUT output value of a digital second-order integral modulator for capacitance detection.

The invention discloses a second-order integral modulator circuit for CDC (capacitance-to-digital conversion) and an offset capacitance adjustment processing method of an interface part of the second-order integral modulator circuit and a capacitance sensor. The circuit is realized by integrating a switched capacitor and an adjusting register in the same chip, the low-frequency noise of the circuit is moved by adopting a sigma-delta modulator with a high oversampling rate, and the switch capacitor DAC is controlled by the register to realize the adaptive matching of the same circuit to different capacitance sensor heads. Compared with the traditional discrete component capacitance detection circuit, the circuit has the advantages of high precision, small volume, low power consumption and the like.

The digital capacitance detection second-order integral modulator circuit disclosed by the invention only needs two fully-differential CMOS operational amplifiers, one CMOS comparator and a switch to be matched with corresponding non-overlapping clocks, realizes CV conversion of capacitance detection and completes integration and modulation of voltage signals, reduces design requirements of operational amplifier noise indexes by utilizing signal processing characteristics of the modulator, and improves conversion precision of capacitance to digital.

The digital capacitance detection second-order integral modulator circuit disclosed by the invention utilizes the built-in capacitor array network to realize the adjustment of a capacitance common-mode bias point, eliminates the output offset of the capacitance sensor caused by processing errors, greatly improves the matching rate of a signal processing circuit and the capacitance sensor, and is beneficial to the engineering of a miniaturized MEMS capacitance sensor.

The invention provides a digital second-order integral modulator circuit for capacitance detection and a processing method for adjusting offset capacitance of an interface part of the digital second-order integral modulator circuit and a capacitance sensor, wherein the circuit is realized by adopting a general CMOS (complementary metal oxide semiconductor) process, a general schematic diagram of a preferred scheme of the invention is shown in figure 5, the schematic diagram is the cascade summation of figures 2, 3 and 4, and the name of each component in the diagram corresponds to that in figure 5 one by one. The circuit has the functional characteristics of a second-order integrator, 1bit quantization and capacitance offset correction, and achieves the purposes of low-frequency noise shaping and wide-range capacitance matching of the sensor.

The invention provides a method for adjusting and processing offset capacitance of an interface part of a capacitance sensor, which is shown in fig. 6 and 7, wherein the two figures respectively show the working processes of a sampling stage and a calculating stage. Capacitive arrays CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6, CDB0, CDB1, CDB2, CDB3, CDB4, CDB5, CDB6, CP5, CP6, CP7, CP8, CP9, CN5, CN6, CN7, CN8, CN 9; an operational amplifier AMP 1; switches K0', K1', K0, K1, KDA0, KDA1, KDA2, KDA3, KDA4, KDA5, KDA6, KDA7, KDB0, KDB1, KDB2, KDB3, KDB4, KDB5, KDB6 and KDB7 form a capacitance mismatch adjusting circuit;

referring to fig. 6 and 7, an interface offset capacitance adjusting circuit of a capacitive sensor according to the present invention is shown. During the mismatched charge amount sampling phase of fig. 6, switches K1 and K1' are both in an on state. The circuit charges mismatch adjusting capacitors CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6, CDB0, CDB1, CDB2, CDB3, CDB4, CDB5 and CDB6, the circuit selects an appropriate number of mismatch adjusting capacitors according to the mismatch amount, the first-stage integrator AMP1 is multiplexed to complete sampling of mismatch charges, and the clock of a calculation stage is waited.

In the mismatch charge amount calculation stage of fig. 7, both switches K0 and K0' are in the on state at this time. The capacitors CDA0, CDA1, CDA2, CDA3, CDA4, CDA5, CDA6, CDB0, CDB1, CDB2, CDB3, CDB4, CDB5 and CDB6 are connected to VIN and VIP terminals respectively, charges are redistributed on VIN and VIP high-resistance nodes respectively according to a conservation principle, and the charge-to-voltage conversion amount formed due to mismatch is calculated. The circuit can detect the mismatch of the sensor capacitor when the sensor is matched, and configures the capacitor network value of the offset capacitor adjuster through the value of the mismatch, so that the function of eliminating the mismatch capacitor of the sensor is achieved, and the matching range of the capacitor digital signal processing circuit to the sensor is expanded.

The circuit of the invention is matched with a sandwich differential capacitive MEMS accelerometer for testing, the lowest point of ALLAN variance of the accelerometer is less than 2ug, and the zero offset stability of the accelerometer is less than 20ug in 1 hour at 0 g. The test result shows that the capacitance resolution of the circuit is 4aF, and the advanced level of the circuit in China and the advanced level of the circuit in the international country are achieved.

Claims

1. A digitized second-order integrating modulator for capacitance detection, comprising: the device comprises a first-stage integral modulation module, a second-stage integral modulation module and a comparator;

2. A digitized second order integrating modulator circuit for capacitance detection as claimed in claim 1 wherein: the first-stage integral modulation module realizes CV (capacitance voltage) conversion by adopting a charge conservation principle of a switch capacitor. Compared with the traditional CV conversion circuit, the CV conversion circuit adopting the charge conservation principle of the switched capacitor does not need a high-precision low-noise high-performance operational amplifier circuit to convert charges into voltages, and adopts the sigma-delta modulator to realize high-precision capacitance conversion on the low-frequency noise shaping characteristic, so that the weak capacitance signal detection performance is greatly improved in a low-power-consumption working mode.

3. A digitized second order integrating modulator circuit for capacitance detection as claimed in claim 1 wherein: the first-stage integral modulation module realizes the extrapolation of low-frequency noise of the circuit to high frequency by using a non-overlapping two-phase clock and combining a switched capacitor chopping technology, simplifies the design difficulty of a front-end charge-to-voltage processing analog circuit, improves the noise processing performance of the circuit, and is favorable for the high integration of the analog circuit and a digital denoising filter circuit.

4. A digitized second order integrating modulator circuit for capacitance detection as claimed in claim 1 wherein: a7-bit-wide switch capacitor DAC is integrated in the first-stage integral modulation module, and the matching of the offset capacitance of the external sensor to be detected is realized by combining the operation and the amplification of a shared integrator and an in-chip high-precision capacitance network. The capacitance offset matching from 157fF to 20pF is realized by controlling the DAC input value through the register, the adaptability of the capacitance detection circuit is enlarged, and the capacitance value range of capacitance detection is improved.