CN112634802B

CN112634802B - Gate driving circuit and display panel

Info

Publication number: CN112634802B
Application number: CN201910949746.XA
Authority: CN
Inventors: 詹建廷
Original assignee: Hannstar Display Corp
Current assignee: Hannstar Display Corp
Priority date: 2019-10-08
Filing date: 2019-10-08
Publication date: 2024-06-04
Anticipated expiration: 2039-10-08
Also published as: CN112634802A

Abstract

The invention discloses a gate driving circuit and a display panel. The gate driving circuit includes a plurality of shift registers, a first signal line, and a second signal line. The shift registers respectively provide scanning signals to a plurality of gate lines of the display panel. Each shift register comprises a first transistor and a second transistor, wherein the grid electrode of the first transistor and the grid electrode of the second transistor respectively receive a first signal and a second signal. The first signal line and the second signal line respectively provide a first signal to the gate of the first transistor and a second signal to the gate of the second transistor, wherein the first transistor is partially overlapped with the first signal line, and the second transistor is partially overlapped with the second signal line. The invention has the advantages of at least reducing layout area, prolonging the distance between the signal line and the boundary of the active array substrate, saving production cost and the like.

Description

Gate driving circuit and display panel

Technical Field

The present invention relates to a gate driving circuit and a display panel, and more particularly, to a gate driving circuit and a display panel having the same.

Background

With the continuous progress of thin film transistor (thin film transistor; TFT) liquid crystal display technology, technologies for integrating a driving circuit (e.g., a gate driving circuit) on a display panel, such as a system-integrated glass panel, etc., have been increasingly used in today's display devices to minimize the size of the display device product and to enhance the performance of the display device. For the display panel with integrated gate driver, the gate driver and the pixel unit are disposed on the active array substrate and are located in the peripheral area and the active area of the display panel respectively, so that the layout space of the gate driver needs to be reserved in the peripheral area, which results in an increase in the width of the peripheral area, which is unfavorable for the requirement of a narrow frame of the display panel.

Disclosure of Invention

The present invention is directed to a gate driving circuit and a display panel, which reduce the layout area of a shift register in a peripheral region of the display panel, thereby facilitating the realization of a narrow frame requirement of the display panel, and the distance between the signal line and the boundary of the active array substrate can be lengthened, so that the effect of electrostatic discharge can be further enhanced.

According to the object, the present invention provides a gate driving circuit including a plurality of shift registers, a first signal line, and a second signal line. The shift registers respectively provide scanning signals to a plurality of gate lines of the display panel. Each shift register comprises a first transistor and a second transistor, wherein the grid electrode of the first transistor and the grid electrode of the second transistor respectively receive a first signal and a second signal. The first signal line and the second signal line respectively provide a first signal to the gate of the first transistor and a second signal to the gate of the second transistor, wherein the first transistor is partially overlapped with the first signal line, and the second transistor is partially overlapped with the second signal line.

According to an embodiment of the present invention, a portion of the first signal line simultaneously serves as a gate of the first transistor, and a portion of the second signal line simultaneously serves as a gate of the second transistor.

According to another embodiment of the present invention, the first signal line has a first extension portion and a first protruding portion, the second signal line has a second extension portion and a second protruding portion, the channel layer of the first transistor is at least partially disposed on the first protruding portion, and the channel layer of the second transistor is at least partially disposed on the second protruding portion.

According to a further embodiment of the present invention, a portion and another portion of the channel layer of the first transistor are disposed on the first extension portion and the first protrusion portion, respectively, and a portion and the one portion of the channel layer of the second transistor are disposed on the second extension portion and the second protrusion portion, respectively.

According to still another embodiment of the present invention, the first signal line has a first side and a second side opposite to each other, the second signal line has a third side and a fourth side opposite to each other, the second side of the first signal line and the third side of the second signal line are opposite to each other, and the first transistor, the second transistor, the first protrusion and the second protrusion are located between the first side of the first signal line and the fourth side of the second signal line.

According to another embodiment of the present invention, any one of the gate lines of the display panel extends along a first direction, and a projection of the first protrusion in the first direction overlaps a projection of the second protrusion in the first direction.

According to still another embodiment of the present invention, each shift register further includes a third transistor and a fourth transistor, gates of the third transistor and the fourth transistor respectively receive the first signal and the second signal, the first signal line and the second signal line respectively further have a third protrusion and a fourth protrusion, the third transistor, the fourth transistor, the third protrusion and the fourth protrusion are located between the first side of the first signal line and the fourth side of the second signal line, a channel layer of the third transistor is at least partially disposed on the third protrusion, and a channel layer of the fourth transistor is at least partially disposed on the fourth protrusion.

According to still another embodiment of the present invention, any one of the gate lines of the display panel extends along a first direction, and a projection of at least one of the first and third protrusions in the first direction overlaps a projection of at least one of the second and fourth protrusions in the first direction.

According to another embodiment of the present invention, each shift register further includes a precharge unit, a pull-down unit, and a pull-down unit. The precharge unit is coupled to the first node and outputs a precharge signal from the first node. The pull-up unit is coupled to the first node and the second node, and outputs one of the scan signals to a corresponding one of the gate lines from the second node. The pull-down unit is coupled to the first node and the second node, and comprises the first transistor and the second transistor, and receives the precharge signal, the first signal and the second signal.

According to the above-mentioned objects, the present invention further provides a display panel having an active region and a peripheral region. The display panel comprises a plurality of gate lines and a gate driving circuit. The gate driving circuit is located in the peripheral region and comprises a plurality of shift registers, a first signal line and a second signal line. The shift registers provide a plurality of scanning signals to the gate lines. Each of the shift registers includes a first transistor and a second transistor, and a gate of the first transistor and a gate of the second transistor respectively receive a first signal and a second signal. The first signal line and the second signal line respectively provide a first signal to the gate of the first transistor and a second signal to the gate of the second transistor, wherein the first transistor is partially overlapped with the first signal line, and the second transistor is partially overlapped with the second signal line.

According to an embodiment of the invention, the display panel is a system-integrated glass panel.

The invention has the beneficial effects that the layout area of the shift register in the peripheral area of the display panel can be further reduced by the configuration mode, thereby being beneficial to realizing the narrow frame requirement of the display panel. Because of the reduced layout area of the shift register, the distance between the signal line (including the reference potential signal line, the start signal line, the end signal line, the clock signal line, the pull-down control signal line, etc.) and the boundary of the active array substrate (i.e., the boundary of the display panel) can be lengthened, so that the effect of electrostatic discharge can be further enhanced. In addition, through the configuration mode, the pull-down control signal line is not required to cross another pull-down control signal line in a mode of configuring an additional connecting structure to be electrically connected with different metal layers, so that the pull-down control signal is transmitted to the transistor in the shift register, and the production cost can be saved.

Drawings

For a more complete understanding of the embodiments and advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a gate driving circuit according to an embodiment of the invention;

FIG. 3 is an equivalent circuit diagram of the shift register in the gate driving circuit of FIG. 2;

FIG. 4 is a layout diagram of a shift register and signal lines according to a first embodiment of the present invention;

FIG. 5 is a partial enlarged view of the layout diagram shown in FIG. 4;

FIG. 6A is a schematic layout of the first conductive layer in FIG. 5;

FIG. 6B is a schematic layout of the first conductive layer and the channel layer in FIG. 5;

FIG. 6C is a schematic layout diagram of the first conductive layer, the channel layer and the connection structure in FIG. 5;

FIG. 6D is a schematic layout diagram of the first conductive layer, the channel layer, the connection structure and the second conductive layer in FIG. 5;

FIG. 7 is a layout diagram of a shift register and signal lines according to a second embodiment of the present invention;

FIG. 8A is a partial enlarged view of the layout diagram shown in FIG. 7;

FIG. 8B is a partial enlarged view of the pull-down control signal line shown in FIG. 8A;

FIG. 8C is a partial enlarged view of the pull-down control signal line, the channel layer and the connection structure shown in FIG. 8A;

FIG. 9 is a schematic diagram of a display panel according to an embodiment of the invention;

FIG. 10 is a schematic diagram of a display panel according to an embodiment of the invention;

FIG. 11 shows the pixel cell arrangement and device configuration in the upper left corner region of the display panel of FIG. 9;

FIG. 12 shows a shift register and device configuration in the upper left corner region of the display panel of FIG. 9;

FIG. 13 is an example of a partial layout of shift registers, clock signal lines and pull-down control signal lines in the upper left corner region of the display panel of FIG. 9;

Fig. 14 is another example of a partial layout of a shift register, a clock signal line, and a pull-down control signal line in an upper left corner region of the display panel of fig. 9;

FIG. 15 is a schematic diagram of a display panel according to an embodiment of the invention;

FIG. 16 is a schematic diagram of a gate driving circuit according to an embodiment of the invention;

fig. 17 is a schematic diagram of a gate driving circuit according to an embodiment of the invention.

Detailed Description

Embodiments of the present invention are discussed in detail below. However, it is to be understood that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are merely illustrative and are not intended to limit the scope of the invention.

It will be understood that, although the terms "first," "second," "third," …, etc. may be used herein to describe various elements, components, regions and/or sections, these terms should not be limited to these elements, components, regions and/or sections. These terms are only used to distinguish one element, component, region and/or section from another element, component, region and/or section.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. The singular forms "a," "an," or "the" are intended to mean plural referents unless otherwise limited. Furthermore, spatially relative terms are used to describe different orientations of the elements in use or operation and are not limited to the orientation depicted in the figures. Elements may be otherwise oriented (rotated 90 degrees or in other directions) and the spatially relative descriptions used herein may be read in the same manner.

For simplicity and clarity of illustration, reference numerals and/or letters may be reused herein in the various embodiments, but this is not meant to indicate causal relationships between the various embodiments and/or configurations discussed.

As used herein, the term "coupled" may refer to two or more elements being in physical or electrical contact with each other directly or indirectly, and may also refer to two or more elements being operated or otherwise in physical or electrical contact with each other.

Referring to fig. 1, fig. 1 is a schematic diagram of a display device 100 according to an embodiment of the invention. The display device 100 includes a display panel 110, a source driver 120, and a gate driver 130. The display panel 110 may be, for example, but not limited to, a twisted nematic (TWISTED NEMATIC; TN) type, a horizontal switching (in-PLANE SWITCHING; IPS) type, a Fringe Field Switching (FFS) type, a vertical alignment (VERTICAL ALIGNMENT; VA) type, or an organic light-emitting diode (OLED) display panel. The source driver 120 is electrically connected to the display panel 110, and is used for converting image data into source driving signals and transmitting the source driving signals to the display panel 110. The gate driver 130 is used for generating gate driving signals and transmitting the gate driving signals to the display panel 110. The display panel 110 has an active area AA (also referred to as a display area AA) in which a plurality of data lines DL, a plurality of gate lines SL and a plurality of pixels PX formed on an active array substrate 112 of the display panel 110 are disposed, and the pixels PX are commonly driven by source driving signals and gate driving signals to display images, and a peripheral area PA in which a plurality of wirings (not shown) are disposed, which are respectively coupled to the source driver 120 and the gate driver 130 and are respectively coupled to the plurality of data lines DL and the gate lines SL in the active area AA, to respectively transmit the source driving signals and the gate driving signals to the thin film transistors TFTs on the active array substrate 112 and at the corresponding pixels PX, such that the pixels PX are controlled by the switching of the thin film transistors TFTs to display corresponding gray scales at a specific time.

The display panel 110 of the present invention is a System On Glass (SOG), that is, the gate driver 130 is fabricated in the display panel 110 in the present invention. In this way, the same process can be used to manufacture the electronic components in the display panel 110 and the gate driver 130 simultaneously. For example, the thin film transistor in the gate driver 130 may be fabricated simultaneously with the thin film transistor in the active area AA of the display panel 110 using the same process. In other embodiments, the source driver 120 may also be fabricated in the peripheral area PA of the display panel 110, and the same process may be used to fabricate the electronic components and the wirings in the display panel 110, the source driver 120, and the gate driver 130 at the same time.

Fig. 2 is a schematic diagram of a gate driving circuit 200 according to an embodiment of the invention. The gate driving circuit 200 is suitable for the display device 100 of fig. 1 or other similar display devices. The following description exemplifies a display device 100 for fig. 1, that is, the gate driver 130 of fig. 1 includes a gate driving circuit 200. The gate driving circuit 200 is disposed at the left edge of the display panel 110 and in the peripheral area PA. The gate driving circuit 200 includes a plurality of signal lines including a reference potential signal line VL, a start signal line SL1, an end signal line SL2, clock signal lines L1 to L4, and pull-down control signal lines PL1, PL2, and 1 st to M-th shift registers 210 (1) to 210 (M), each of which transmits a signal to at least one of the 1 st to M-th shift registers 210 (1) to 210 (M), and the 1 st to M-th shift registers 210 (1) to 210 (M) output scan signals OUT (1) to OUT (M) to 1 st to M-th gate lines in the active area AA respectively and sequentially, wherein M is a positive integer greater than or equal to 5. For example, in the same frame period (frame period), the 1 st stage shift register 210 (1) outputs the 1 st stage scan signal OUT (1) to the 1 st gate line, then after the time t, the 2 nd stage shift register 210 (2) outputs the 2 nd stage scan signal OUT (2) to the 2 nd gate line, then after the time t, the 3 rd stage shift register 210 (3) outputs the 3 rd stage scan signal OUT (3) to the 3 rd gate line, and so on until the M stage shift register 210 (M) outputs the M stage scan signal OUT (M) to the M th gate line. In some embodiments, as shown in FIG. 2, M is a multiple of 4, and clock signal line L1 provides clock signal C1 to 1 st stage shift register 210 (1), 5 th stage shift register 210 (5), …, and (M-3) th stage shift register 210 (M-3), clock signal line L2 provides clock signal C2 to 2 nd stage shift register 210 (2), 6 th stage shift register 210 (6), …, and (M-2) th stage shift register 210 (M-2), clock signal line L3 provides clock signal C3 to 3 rd stage shift register 210 (3), 7 th stage shift register 210 (7), …, and (M-1) th stage shift register 210 (M-1), and clock signal line L4 provides clock signal C4 to 4 th stage shift register 210 (4), 8 th stage shift register 210 (8), …, and M-th stage shift register 210 (M). The clock signals C1-C4 are all periodic signals, and the period time lengths are the same, wherein the clock signal C2 is 1/4 period time behind the clock signal C1, the clock signal C3 is 1/4 period time behind the clock signal C2, and the clock signal C4 is 1/4 period time behind the clock signal C3. In addition, the reference potential signal line VL supplies the reference potential signals VGL to the 1 st to M-th shift registers 210 (1) to 210 (M), the start signal line SL1 supplies the start signals STV1 to the 1 st and 2 nd shift registers 210 (1), 210 (2), and the end signal line SL2 supplies the end signals STV2 to the (M-1) -th and M-th shift registers 210 (M-1), 210 (M). The pull-down control signal lines PL1, PL2 supply pull-down control signals GPWL, GPWL2 to the 1 st to M-th shift registers 210 (1) to 210 (M), respectively. The reference potential signal line VL, the start signal line SL1, the end signal line SL2, the clock signal lines L1 to L4, and the pull-down control signal lines PL1, PL2 may be coupled to one or more dies, i.e., the reference potential signal VGL, the clock signals C1 to C4, the start signal STV1, the end signal STV2, and the pull-down control signals GPWL, GPWL may be provided from one or more dies, such as a driving die and/or a timing control die, etc., but not limited thereto. It should be noted that, for simplicity of the drawing, fig. 2 does not show all the signal lines in the present embodiment. For example, the plurality of signal lines of the gate driving circuit 200 may further include a forward signal line FL and a reverse signal line BL, respectively providing the forward input signal FW and the reverse input signal BW to the 1 st to M-th shift registers 210 (1) to 210 (M), but is not limited thereto.

Fig. 3 is an equivalent circuit diagram of the i-th stage shift register 210 (i) in the gate driving circuit 200 according to fig. 2, wherein i is a positive integer from 1 to M. As shown in fig. 3, the ith shift register 210 (i) includes a precharge unit 212, a pull-up unit 214, a first pull-down unit 216 and a second pull-down unit 218, wherein one ends of the precharge unit 212, the pull-up unit 214, the first pull-down unit 216 and the second pull-down unit 218 are coupled to a node X1, the other ends of the pull-up unit 214, the first pull-down unit 216 and the second pull-down unit 218 are coupled to a node X2, and the node X2 is coupled to the ith gate line. The precharge unit 212 outputs the precharge signal PC (i) to the node X1, and the pull-up unit 214 outputs the i-th stage scan signal OUT (i) to the node X2. Herein, the nodes X1 and X2 may also be referred to as a first node X1 and a second node X2, respectively, and the node X2 may also be referred to as an output of the i-th stage shift register 210 (i).

The precharge unit 212 receives the input signals IN1, IN2, and outputs a precharge signal PC (i) to the node X1 according to the input signals IN1, IN 2. The precharge unit 212 includes transistors M1, M2. IN the present embodiment, the gate driving circuit 200 is a bi-directional scanning driving circuit, and IN each of the shift registers 210 (1) to 210 (M), the control terminal of the transistor M1 receives the input signal IN1, the first terminal of the transistor M1 receives the forward input signal FW, and the second terminal of the transistor M1 outputs the precharge signal PC (i). The control terminal of the transistor M2 receives the input signal IN2, the first terminal of the transistor M2 receives the inverted input signal BW, the second terminal of the transistor M2 is coupled to the second terminal of the transistor M1, and the second terminal of the transistor M1 and the second terminal of the transistor M2 are coupled to the node X1. Herein, "control terminal", "first terminal" and "second terminal" of a transistor refer to the gate, source and drain of the transistor, respectively, or refer to the gate, drain and source of the transistor, respectively. In other variations, the gate driving circuit 200 can be a unidirectional scanning driving circuit, that is, the difference from fig. 3 is that the first end of the transistor M1 and the first end of the transistor M2 in each of the shift registers 210 (1) to 210 (M) in the present variation can receive the high voltage and the low voltage respectively or receive the low voltage and the high voltage respectively. For example, the first terminals of the transistors M1 and M2 may receive a gate high voltage (gate high voltage; VGH) and a gate low Voltage (VGL) or a gate low voltage and a gate high voltage, respectively, but are not limited thereto.

If the shift register 210 (i) is a 1 st stage or a 2 nd stage shift register (i.e., i is 1 or 2), the input signal IN1 is the start signal STV1, and the input signal IN2 is the scan signal OUT (i+2) output by the (i+2) th stage shift register 210 (i.e., the 3 rd stage scan signal OUT (3) or the 4 th stage scan signal OUT (4)). If the shift register 210 (i) is any one of the 3 rd to (M-2) th shift registers (i.e., i is any positive integer from 3 to (M-2)), the input signals IN1, IN2 are the (i-2) th stage scan signal OUT (i-2) output by the (i-2) th shift register 210 (i-2) and the (i+2) th stage scan signal OUT (i+2) output by the (i+2) th shift register 210 (i+2), respectively. If the shift register 210 (i) is the (M-1) -th or M-th shift register (i.e., i is the (M-1) or M), the input signal IN1 is the scan signal OUT (i-2) (i.e., the (M-3) -th or (M-2) -th scan signal OUT (M-2)) output by the (i-2) -th shift register 210 (i-2), and the input signal IN2 is the end signal STV2.

The pull-up unit 214 is coupled to the precharge unit 212, and receives the precharge signal PC (i) and the clock signal CN, and outputs the scan signal OUT (i) to the node X2 according to the precharge signal PC (i) and the clock signal CN, wherein the clock signal CN is any one of the clock signals C1 to C4. In an embodiment where M is a multiple of 4, if i is 1, 5, …, (M-3), then clock signal CN is clock signal C1; if i is 2, 6, …, (M-2), then clock signal CN is clock signal C2; if i is 3, 7, …, (M-1), then clock signal CN is clock signal C3; if i is 4, 8, …, M, then clock signal CN is clock signal C4. The pull-up unit 214 includes a transistor M3 and a capacitance Cx. The control terminal of the transistor M3 receives the precharge signal PC (i), the first terminal of the transistor M3 receives the clock signal CN, and the second terminal of the transistor M3 outputs the scan signal OUT (i). The first terminal of the capacitor Cx is coupled to the control terminal of the transistor M3, and the second terminal of the capacitor Cx is coupled to the second terminal of the transistor M3.

The first pull-down unit 216 is coupled to the precharge unit 212 and the pull-up unit 214, receives the precharge signal PC (i) and the pull-down control signals GPWL, GPWL, and controls whether to pull down the scan signal OUT (i) to the reference potential according to the precharge signal PC (i) and the pull-down control signals GPWL1, GPWL. The reference voltage in this embodiment is a gate low Voltage (VGL), but not limited thereto. In frame time, the pull-down control signals GPWL, GPWL2 are inverted with respect to each other, i.e., one of the pull-down control signals GPWL, GPWL is high and the other is low. Herein, the pull-down control signals GPWL, GPWL2 may also be referred to as a first pull-down control signal and a second pull-down control signal, respectively. The first pull-down unit 216 includes transistors M4-M8. The control terminal and the first terminal of the transistor M4 input a pull-down control signal GPWL1. The control terminal of the transistor M5 inputs the pull-down control signal GPWL, the first terminal of the transistor M5 is coupled to the reference voltage VGL, the second terminal of the transistor M5 is coupled to the second terminal of the transistor M4, and the second terminal of the transistor M5 and the second terminal of the transistor M4 are coupled to the node P. The control terminal of the transistor M6 is coupled to the node X1, the first terminal of the transistor M6 is coupled to the reference voltage VGL, and the second terminal of the transistor M6 is coupled to the second terminal of the transistor M4. The control terminal of the transistor M7 is coupled to the second terminal of the transistor M6, the first terminal of the transistor M7 is coupled to the reference voltage VGL, and the second terminal of the transistor M7 is coupled to the node X1. The control terminal of the transistor M8 is coupled to the second terminal of the transistor M6, the first terminal of the transistor M8 is coupled to the reference voltage VGL, and the second terminal of the transistor M8 is coupled to the node X2. After the shift register 210 (i) outputs the scan signal OUT (i) to activate the corresponding pixel row (row), that is, after the scan signal OUT (i) rises to a high level and remains at a low level for a period of time, the node X1 falls from the high level to the low level, and the first pull-down unit 216 starts to operate. When the pull-down control signal GPWL is low and the pull-down control signal GPWL is high, the node P is in a low state, so that the transistors M7 and M8 are turned off; when the pull-down control signal GPWL is high and the pull-down control signal GPWL is low, the node P is in a high state, so that the transistors M7 and M8 are turned on to set the voltages of the nodes X1 and X2 to the reference voltage VGL. In a frame time, when the shift register 210 (i) outputs the scan signal OUT (i) to activate the corresponding pixel row, that is, the scan signal OUT (i) rises to a high level and remains at a low level for a while, if the noise signal is coupled to the node X1 and/or the node X2 to cause the potential of the node X1 and/or the node X2 to ripple, the turned-on transistors M7 and M8 pull down the nodes X1 and X2 to a low level (e.g., the reference potential VGL), that is, pull down and maintain the scan signal OUT (i) to a low level without the scan signal OUT (i) being disturbed by the noise.

The second pull-down unit 218 is coupled to the precharge unit 212 and the pull-up unit 214, receives the precharge signal PC (i) and the pull-down control signals GPWL, GPWL, and controls whether to pull down and maintain the scan signal OUT (i) at the reference potential VGL according to the precharge signal PC (i) and the pull-down control signals GPWL, GPWL2. The second pull-down unit 218 includes transistors M9 to M13. The control terminal and the first terminal of the transistor M9 input a pull-down control signal GPWL2. The control terminal of the transistor M10 inputs the pull-down control signal GPWL, the first terminal of the transistor M10 is coupled to the reference voltage VGL, the second terminal of the transistor M10 is coupled to the second terminal of the transistor M9, and the second terminal of the transistor M9 and the second terminal of the transistor 10 are coupled to the node Q. The control terminal of the transistor M11 is coupled to the node X1, the first terminal of the transistor M11 is coupled to the reference voltage VGL, and the second terminal of the transistor M11 is coupled to the second terminal of the transistor M9. The control terminal of the transistor M12 is coupled to the second terminal of the transistor M11, the first terminal of the transistor M12 is coupled to the reference voltage VGL, and the second terminal of the transistor M12 is coupled to the node X1. The control terminal of the transistor M13 is coupled to the second terminal of the transistor M11, the first terminal of the transistor M13 is coupled to the reference voltage VGL, and the second terminal of the transistor M13 is coupled to the node X2. After the shift register 210 (i) outputs the scan signal OUT (i) to activate the corresponding pixel row, that is, after the scan signal OUT (i) rises to a high level and remains at a low level for a period of time, the node X1 falls from the high level to the low level, and the second pull-down unit 218 starts to operate. When the pull-down control signal GPWL is low and the pull-down control signal GPWL is high, the node Q is in a high state, so that the transistors M12 and M13 are turned on to set the potentials of the nodes X1 and X2 to the reference potential VGL; while when the pull-down control signal GPWL is high and the pull-down control signal GPWL is low, the node Q is in a low state, so that the transistors M12 and M13 are turned off. In a frame time, when the shift register 210 (i) outputs the scan signal OUT (i) to activate the corresponding pixel row, that is, the scan signal OUT (i) rises to a high level and remains at a low level for a period of time, if the noise signal is coupled to the node X1 and/or the node X2, the turned-on transistors M12 and M13 pull down the nodes X1 and X2 to a low level, that is, pull down and maintain the scan signal OUT (i) to a low level, so that the scan signal OUT (i) is not interfered by the noise signal. In summary, since the pull-down control signals GPWL and GPWL2 are inverted, when the node X1 is lowered from the high voltage to the low voltage, one of the first pull-down unit 216 and the second pull-down unit 218 starts to operate, that is, the transistors M7 and M8 are turned on and the transistors M12 and M13 are turned off, or the transistors M12 and M13 are turned on and the transistors M7 and M8 are turned off, so that the turn-on time of some transistors in the first pull-down unit 216 and the second pull-down unit 218 can be greatly reduced compared to the circuit of the shift register having only one pull-down unit, so as to avoid the abnormal gate driving circuit caused by the characteristic shift of the transistors due to long-time turn-on. For example, the pull-down control signals GPWL, GPWL2 are inverted and the signal period of the pull-down control signals GPWL, GPWL2 is 2 seconds, wherein the high and low durations in the signal period are 1 second, so the turn-on time of some transistors in the first and second pull-down units 216, 218 can be reduced by half compared to a circuit having a shift register with only one pull-down unit.

It should be noted that, the gate driving circuit 200 may be changed to sequentially output the scan signals OUT (1) to OUT (M) to the gate lines in the active area AA in the opposite direction. When the gate driving circuit 200 is forward scanning, that is, the forward input signal FW is high and the reverse input signal BW is low, the STV1 is a start signal and the STV2 is an end signal. Conversely, when the gate driving circuit 200 is in the reverse scan, that is, the forward input signal FW is in the low level and the reverse input signal BW is in the high level, the STV2 is the start signal, the STV1 is the end signal, and the clock signals C1 to C4 are changed to: the clock signal C3 is 1/4 cycle time behind the clock signal C4, the clock signal C2 is 1/4 cycle time behind the clock signal C3, and the clock signal C1 is 1/4 cycle time behind the clock signal C2, so that in the same frame period, the M-th stage shift register 210 (M) outputs the M-th stage scan signal OUT (M) to the M-th gate line, then after the time t, the (M-1) -th stage shift register 210 (M-1) outputs the (M-1) -th stage scan signal OUT (M-1) to the (M-1) -th gate line, then after the time t, the (M-2) -th stage shift register 210 (M-2) outputs the (M-2) -th stage scan signal OUT (M-2) -th gate line, and so on until the 1-th stage shift register 210 (1) outputs the 1-th stage scan signal OUT (M-1) -th gate line. In the embodiment herein, the forward scanning is taken as an example, that is, STV1 is the start signal and STV2 is the end signal. The implementation of the reverse scan embodiment can be directly deduced from the above description, and thus is not described here.

The transistors M1-M13 in the shift register 210 (i) may be amorphous silicon (amorphous silicon) thin film transistors, low temperature polysilicon (low temperature polysilicon; LTPS) thin film transistors, indium gallium zinc oxide (Indium Gallium Zinc Oxide; IGZO) thin film transistors, or other suitable thin film transistors. If the amorphous silicon thin film transistor is selected, the production cost of the gate driving circuit 200 can be further reduced.

The layout of the shift register circuits 210 (1) to 210 (M) and the relevant signal lines in the gate driving circuit 200 is as follows, for example. Referring to fig. 4, fig. 4 is a layout diagram of a shift register and signal lines according to a first embodiment of the present invention. For convenience of explanation, fig. 4 only shows the shift register 210 (5) of fig. 3. However, those skilled in the art should directly understand the layout of the remaining shift registers 210 (1) to 210 (4), 210 (6) to 210 (M) from the layout shown in fig. 4 and the contents of fig. 2 and 3. In fig. 4, signal lines such as a reference potential signal line VL, a start signal line SL1, clock signal lines L1 to L4, and pull-down control signal lines PL1, PL2 are located in a region near a boundary 112A of the active array substrate 112 and extend in a direction Y. In addition, the active area AA is located on the right side of the shift register 210 (5), the gate lines in the active area AA may extend along the direction X (not shown), and the shift register 210 (5) outputs the 5 th stage scan signal OUT (5) to the corresponding gate lines. The traces for transmitting the scan signals OUT (3), OUT (4), OUT (6), OUT (7) output from the 3 rd, 4 th, 6 th, and 7 th shift registers 210 (3), 210 (4), 210 (6), and 210 (7), respectively, are located in the area near the active area AA. As shown in fig. 4, the layout area of the 5 th stage shift register circuit 210 (5) includes transistors M1 to M13 and a capacitance Cx, which are located between some signal lines (including the ground line GL, the start signal line SL1, the clock signal lines L1 to L4, and the pull-down control signal lines PL1, PL2, etc.) and the active area AA. In the 5 th stage shift register circuit 210 (5), the pull-down control signal lines PL1, PL2 are arranged between the layout areas of the transistors M1 to M13 and the capacitance Cx and the layout areas of the clock signal lines L1 to L4. Further, as shown in fig. 4, the layout areas of the transistors M4 to M8 of the first pull-down unit 216 and the layout areas of the transistors M9 to M13 of the second pull-down unit 218 are located between the layout areas of the pull-down control signal lines PL1, PL2 and the layout area of the pull-up unit 214 (including the transistor M3 and the capacitance Cx).

Further reference is made to fig. 5, which is an enlarged view of a portion of the layout diagram depicted in fig. 4. As shown in fig. 4 and 5, the pull-down control signal lines PL1, PL2 are located between the clock signal lines L1 to L4 and the transistors M4, M5, M9, M10, and the transistors M4, M5 in the first pull-down unit 216 and the transistors M9, M10 in the second pull-down unit 218 are located in the region between the pull-down control signal lines PL1, PL2 and the transistors M7, M12.

Fig. 5 is a layout diagram of a transistor including a first conductive layer, a channel layer, a connection structure, and a second conductive layer, wherein the first conductive layer includes a gate of the transistor and the second conductive layer includes a source and a drain of the transistor. In the layout of the transistor of the present embodiment, in the top view of fig. 5, the channel layer of the transistor is located above the gate, and the source and the drain (i.e., one of the first end and the second end and the other) are located above the channel layer and are disposed opposite to each other. The first conductor layer and the second conductor layer can be of a single-layer structure or a multi-layer stacked structure. In this embodiment, the first conductive layer and the second conductive layer may be a first metal layer and a second metal layer, but not limited thereto. Referring to fig. 5 and fig. 6A to 6D, fig. 6A is a schematic layout diagram of the first conductive layer in fig. 5, fig. 6B is a schematic layout diagram of the first conductive layer and the channel layer in fig. 5, fig. 6C is a schematic layout diagram of the first conductive layer, the channel layer and the connection structure in fig. 5, and fig. 6D and fig. 5 are schematic layout diagrams including the first conductive layer, the channel layer, the connection structure and the second conductive layer, wherein the difference is that the element marks of fig. 5 and fig. 6D are different, so that the drawing is concise and easy to read. As shown in fig. 6A, the first conductor layer includes a clock signal line L1, pull-down control signal lines PL1, PL2, and gates m4_ C, M5_ C, M7_ C, M9_ C, M10 _10_ C, M12_c of transistors M4, M5, M7, M9, M10, M12. As shown in fig. 6B, in the transistor M4, the channel layer m4_s is located above the gate m4_c, and the first end m4_1 and the second end m4_2 are located above the channel layer m4_s and are disposed opposite to each other. Similarly, the channel layers m5_ S, M7 _7_ S, M9_ S, M10 _10_ S, M12_s, the control end m5_ C, M7_ S, M9_ C, M10_ C, M12_c, the first end m5_1, m7_1, m9_1, m10_1, m12_1, and the second end m5_2, m7_2, m9_2, and m10_2 of the transistors M5, M7, M9, M10, M12 in fig. 5 are the same as those of the transistor M4, and thus the description thereof will be omitted. As shown in fig. 6C and fig. 6D, the connection structure CT is disposed between the first conductive layer and the second conductive layer, and is used for electrically connecting the first conductive layer and the second conductive layer. In this embodiment, at least one insulating layer is disposed between the first conductive layer and the second conductive layer, and the connection structure CT is a through hole of the at least one insulating layer, which exposes a portion of the first conductive layer, so that the second conductive layer can extend into the through hole to contact with the first conductive layer to electrically connect the first conductive layer and the second conductive layer, but the connection structure CT is not limited thereto. In a variation, the connection structure CT may include a connection electrode, a first via and a second via, at least one insulating layer between the first conductor layer and the connection electrode, and the at least one insulating layer has the first via to expose a portion of the first conductor layer, at least one insulating layer between the second conductor layer and the connection electrode, and the at least one insulating layer has the second via to expose a portion of the second conductor layer, and the connection electrode extends into the first via and the second via to contact the first conductor layer and the second conductor layer, respectively, so that the first conductor layer may be electrically connected to the second conductor layer via the connection electrode. For example, the connection electrode may be formed simultaneously with the pixel electrode or the common electrode, that is, the connection electrode may belong to the same transparent conductive layer as the pixel electrode or the common electrode, so as to save process steps. As shown in fig. 6D, in the transistor M4, the first terminal m4_1 and the second terminal m4_2 are located above the channel layer m4_s and are disposed opposite to each other. Similarly, the first ends m5_1, m7_1, m9_1, m10_1, m12_1 and the second ends m5_2, m7_2, m9_2, m10_2, m12_2 of the transistors M5, M7, M9, M10, M12 in fig. 6D are arranged in the same manner as the transistor M4, and the description thereof is omitted. Referring to fig. 5 and fig. 6D, the first end m4_1 of the transistor M4 is electrically connected to the gate m4_c of the transistor M4 through the connection line CL1 and the connection structure CT1, and the first end m4_1 of the transistor M4 is electrically connected to the pull-down control signal line PL1 through the connection lines CL1 and CL2 and the connection structure CT 2. The gate m5_c of the transistor M5 is electrically connected to the pull-down control signal line PL2 via the connection line CL 3. The first end m9_1 of the transistor M9 is electrically connected to the gate m9_c of the transistor M9 via the connection line CL4 and the connection structure CT3, and the gate m9_c of the transistor M9 is electrically connected to the pull-down control signal line PL2 via the connection line CL 5. The gate m10_c of the transistor M10 is electrically connected to the pull-down control signal line PL1 via the connection structure CT4, the connection line CL6 and the connection structure CT 5. In the present embodiment, the connection lines CL3, CL5 are formed by the first conductor layer, and the connection lines CL1, CL2, CL4, CL6 are formed by the second conductor layer.

Referring to fig. 7, fig. 7 is a layout diagram of a shift register and signal lines according to a second embodiment of the present invention. For convenience of explanation, fig. 7 only shows the shift register 210 (5) of fig. 3. However, those skilled in the art should directly understand the layout of the remaining shift registers 210 (1) to 210 (4), 210 (6) to 210 (M) from the layout shown in fig. 7 and the contents of fig. 2 and 3.

As shown in fig. 7, the difference between fig. 7 and fig. 4 is that the pull-down control signal lines PL1, PL2 of fig. 4 are located in the region between the clock signal lines L1 to L4 and the transistors M4 to M13, that is, in the region between the clock signal lines L1 to L4 and the first and second pull-down units 216, 218, and the layout region of the pull-down control signal lines PL1, PL2 of fig. 7 partially overlaps the layout region of the first pull-down unit 216 and the layout region of the second pull-down unit 218 in the plan view direction (i.e., the direction perpendicular to the X-Y plane). In addition, the active area AA is located on the right side of the shift register 210 (5), the gate lines in the active area AA may extend along the direction X (not shown), and the shift register 210 (5) outputs the 5th stage scan signal OUT (5) to the corresponding gate lines.

Referring further to fig. 8A, a partial enlarged view of the layout diagram shown in fig. 7 is shown. Fig. 8A is a layout diagram of a transistor including a first conductive layer, a channel layer, a connection structure, and a second conductive layer, wherein the first conductive layer includes a gate of the transistor and the second conductive layer includes a source and a drain of the transistor. As shown in fig. 8A, the pull-down control signal lines PL1, PL2 are located between the clock signal lines L1 to L4 and the transistors M7, M12. The pull-down control signal line PL1 has a first side PLE1 and a second side PLE2 opposite to each other, wherein the first side PLE1 is closer to a boundary 112A of the active array substrate 112 than the second side PLE2, and the pull-down control signal line PL2 has a third side PLE3 and a fourth side PLE4 opposite to each other, wherein the fourth side PLE4 is closer to the active region AA than the third side PLE3, and the second side PLE2 and the third side PLE3 are opposite to each other. Transistors M4, M5 in the first pull-down unit 216 and transistors M9, M10 in the second pull-down unit 218 are located in the region between the first side PLE1 and the fourth side PLE 4.

As shown in fig. 8A, the pull-down control signal line PL1 overlaps the transistor M4 in the first pull-down unit 216 and the transistor M10 in the second pull-down unit 218, and the pull-down control signal line PL2 overlaps the transistor M5 in the first pull-down unit 216 and the transistor M9 in the second pull-down unit 218. That is, a part and the other part of the pull-down control signal line PL1 serve as a control terminal (gate) m4_c of the transistor M4 and a control terminal (gate) m10_c of the transistor M10, respectively, and a part and the other part of the pull-down control signal line PL2 serve as a control terminal (gate) m5_c of the transistor M5 and a control terminal (gate) m9_c of the transistor M9, respectively. The arrangement of the gates, the channel layers, the first ends and the second ends of the transistors M4, M5, M9, M10 in fig. 8A is the same as that of the first embodiment (fig. 5 to 6D), and will not be repeated here. The control terminal m4_c of the transistor M4 is electrically connected to the first terminal m4_1 of the transistor M4 via the connection structure CT6, and the control terminal m9_c of the transistor M9 is electrically connected to the first terminal m9_1 of the transistor M9 via the connection structure CT 7. The structures of the connection structures CT6 and CT7 are the same as the connection structures CT1 to CT5 in the first embodiment, that is, the connection structures CT6 and CT7 in the present embodiment take the through hole of at least one insulating layer between the first conductor layer and the second conductor layer as an example, but not limited thereto. In a variant embodiment, the structures of the connection structures CT6, CT7 may be the same as the connection structures including the connection electrode, the first via and the second via in the variant embodiment of the first embodiment.

Referring to fig. 8B, a partial enlarged view of the pull-down control signal lines PL1 and PL2 shown in fig. 8A is shown. As shown in fig. 8B, the pull-down control signal line PL1 has an extension portion pl1_l and convex portions pl1_p1, pl1_p2, pl1_p3, and the pull-down control signal line PL2 has an extension portion pl2_l and convex portions pl2_p1, pl2_p2, pl2_p3. The convex portions pl1_p1, pl1_p2, pl1_p3 directly connect with the extension portion pl1_l, and the convex portions pl2_p1, pl2_p2, pl2_p3 directly connect with the extension portion pl2_l. The length of the convex portions pl1_p1, pl1_p3 in the direction X (perpendicular to the direction Y) is W1, the length of the convex portion pl1_p2 in the direction X is W2, the length of the convex portions pl2_p1, pl2_p2 in the direction X is W3, and the length of the convex portion pl2_p3 in the direction X is W4. The length W1 is greater than the length W2, and the length W3 is greater than the length W4, but not limited thereto. In some embodiments, the length W1 may be the same as the length W3, and/or the length W2 may be the same as the length W4, but is not limited thereto. The projections pl1_p1 to pl1_p3 and pl2_p1 to pl2_p3 are staggered in the direction Y. In addition, the projection of the convex portions pl1_p1, pl1_p3 in the direction X may overlap the projection of the convex portions pl2_p1, pl2_p2 in the direction X, so as to further reduce the distance between the first side PLE1 and the fourth side PLE4, and further reduce the layout area of the gate driving circuit 200, so as to achieve the narrow frame requirement of the display panel. For example, the projection of the convex portions pl1_p1, pl1_p3 in the direction X is located between the coordinate a and the coordinate b of the direction X, and the projection of the convex portions pl2_p1, pl2_p2 in the direction X is located between the coordinate c and the coordinate d of the direction X, wherein the interval from the coordinate a to the coordinate b of the direction X and the interval from the coordinate c to the coordinate d are partially overlapped.

Fig. 8C is a partially enlarged view of the pull-down control signal lines PL1, PL2, the channel layer m4_ S, M5_ S, M9_ S, M10_s and the connection structures CT6, CT7 shown in fig. 8A. As shown in fig. 8C, the lengths of the convex portions pl1_p1, pl2_p1, pl2_p2, pl1_p3 in the direction Y are respectively larger than the lengths of the channel layers m4_ S, M5_ S, M9_ S, M10_s in the direction Y, the convex portions pl1_p1, pl1_p3 are directly connected to the extending portion pl1_l, and the convex portions pl2_p1, pl2_p2 are directly connected to the extending portion pl2_l, so the channel layers m4_s are simultaneously disposed on the extending portion pl1_l and the convex portion pl1_p1, the channel layers m5_s are simultaneously disposed on the extending portion pl2_l and the convex portion pl2_p1, the channel layers m9_s are simultaneously disposed on the extending portion pl2_l and the convex portion pl2_p2, and the channel layers m10_s are simultaneously disposed on the extending portion pl1_l and the convex portion pl1_p3. In addition, the lengths of the protruding portions pl1_p2, pl2_p3 in the direction Y are larger than the lengths of the connecting structures CT6, CT7 in the direction Y, respectively, the protruding portion pl1_p2 is directly connected to the extending portion pl1_l, and the pl2_p3 is directly connected to the extending portion pl2_l, so the connecting structure CT6 is disposed on both the extending portion pl1_l and the protruding portion pl1_p2, and the connecting structure CT7 is disposed on both the extending portion pl2_l and the protruding portion pl2_p3. In other embodiments, the channel layer m4_s may be disposed entirely on the projection pl1_p1, the channel layer m5_s may be disposed entirely on the projection pl2_p1, the channel layer m9_s may be disposed entirely on the projection pl2_p2, the channel layer m10_s may be disposed entirely on the projection pl1_p3, the connection structure CT6 may be disposed entirely on the projection pl1_p2, and/or the connection structure CT7 may be disposed entirely on the projection pl2_p3.

In other embodiments, the layout diagram shown in fig. 8A may be changed to have at most only one of the transistors M4 and M10 overlap the pull-down control signal line PL1 and/or at most only one of the transistors M5 and M9 overlap the pull-down control signal line PL2 according to the respective design requirements. In some embodiments, the pull-down control signal line PL1 does not have the convex portions pl1_p1, pl1_p2, pl1_p3, the pull-down control signal line PL2 does not have the convex portions pl2_p1, pl2_p2, pl2_p3, and the transistors M4, M5, M9, M10 are disposed entirely in the space between the second side PLE2 and the third side PLE 3.

In the present embodiment, the control ends of the start signal line SL1, the end signal line SL2, the clock signal lines L1 to L4, the pull-down control signal lines PL1, PL2, and the transistors M1 to M13 belong to a first conductor layer (e.g., a first metal layer) in the display panel 110, and the reference potential signal line VL, the first ends and the second ends of the transistors M1 to M13 belong to a second conductor layer (e.g., a second metal layer) in the display panel 110. The start signal line SL1, the end signal line SL2, the clock signal lines L1 to L4, the pull-down control signal lines PL1, PL2, and the control terminals of the transistors M1 to M13 may be formed via the same process, and the reference potential signal line VL, the first terminals of the transistors M1 to M13, and the second terminals may be formed via the same process.

It should be noted that, the equivalent circuit diagram of the i-th stage shift register 210 (i) in the gate driving circuit 200 of the present invention is not limited to fig. 3. In other words, in other embodiments, the circuitry of the precharge unit, the pull-up unit, the first pull-down unit, and the second pull-down unit in the ith stage shift register 210 (i) may be at least partially different from the circuitry of the precharge unit 212, the pull-up unit 214, the first pull-down unit 216, and the second pull-down unit 218 of fig. 3. Furthermore, in some embodiments, the number of pull-down units in the ith stage of shift register 210 (i) may be one or greater than two. In various embodiments of the shift register circuit, if two signal lines in the gate driving circuit 200 respectively provide the first signal to the gate of at least one transistor in the ith stage of shift register 210 (i) and the second signal to the gate of another at least one transistor in the ith stage of shift register 210 (i), the circuit layout similar to that in fig. 7 to 8C can be adopted to reduce the layout area of the gate driving circuit 200, thereby realizing the narrow frame requirement of the display panel.

In summary, the gate driving circuit 200 includes a plurality of signal lines and 1 st to M-th shift registers 210 (1) to 210 (M), the plurality of signal lines include adjacent first and second signal lines, respectively providing the first and second signals to the 1 st to M-th shift registers 210 (1) to 210 (M), each of the shift registers 210 (i) includes a first transistor and a second transistor, and control terminals (gates) of the first and second transistors respectively receive the first and second signals, so that in the layout of the gate driving circuit 200, a portion of the first signal lines can be simultaneously used as the control terminals (gates) of the first transistors, and a portion of the second signal line can be used as a control terminal (gate) of the second transistor at the same time, that is, the first transistor overlaps the first signal line partially, and the second transistor overlaps the second signal line partially, so as to reduce the layout area of the gate driving circuit 200. For example, the first signal line and the second signal line may be pull-down control signal lines PL1 and PL2, respectively, the first transistor may be the transistor M4 or M10, and the second transistor may be the transistor M5 or M9, but not limited thereto. In addition, in some embodiments, the gate line in the active region extends along the first direction, the first signal line and the second signal line respectively have a first protrusion and a second protrusion, the channel layer of the first transistor is at least partially disposed on the first protrusion, and the channel layer of the second transistor is at least partially disposed on the second protrusion. The first signal line has a first side and a second side opposite to each other, the second signal line has a third side and a fourth side opposite to each other, and the second side of the first signal line and the third side of the second signal line are opposite to each other, so as to further reduce the layout area of the gate driving circuit 200, in the layout of the shift register 210 (i), the first transistor, the second transistor, the first protrusion and the second protrusion are located between the first side of the first signal line and the fourth side of the second signal line, and the projection of the first protrusion in the first direction may overlap with the projection of the second protrusion in the first direction, so as to further reduce the layout area of the gate driving circuit 200. In still other embodiments, each stage shift register 210 (i) further includes a third transistor and a fourth transistor, the control terminals (gates) of the third transistor and the fourth transistor respectively receive the first signal and the second signal, so that in the layout of the gate driving circuit 200, another portion of the first signal line can be used as the control terminal (gate) of the third transistor at the same time, and another portion of the second signal line can be used as the control terminal (gate) of the fourth transistor at the same time, that is, the third transistor overlaps the first signal line partially, and the fourth transistor overlaps the second signal line partially, so as to reduce the layout area of the gate driving circuit 200. The first signal line and the second signal line are respectively provided with a third protruding part and a fourth protruding part, the channel layer of the third transistor is at least partially arranged on the third protruding part, the channel layer of the fourth transistor is at least partially arranged on the fourth protruding part, the third transistor, the fourth transistor, the third protruding part and the fourth protruding part are positioned between the first side edge of the first signal line and the fourth side edge of the second signal line, and the projection of at least one of the first protruding part and the third protruding part in the first direction can be overlapped with the projection of at least one of the second protruding part and the fourth protruding part in the first direction, so that the layout area of the gate driving circuit 200 is further reduced. For example, the first transistor and the third transistor may be the transistors M4 and M10, respectively, and the second transistor and the fourth transistor may be the transistors M5 and M9, respectively, but not limited thereto.

Referring to fig. 5 and 8A simultaneously, since a part and another part of the pull-down control signal line PL1 in the second embodiment (fig. 8A) are respectively used as the control terminal m4_c of the transistor M4 and the control terminal m10_c of the transistor M10, and a part and another part of the pull-down control signal line PL2 are respectively used as the control terminal m5_c of the transistor M5 and the control terminal m9_c of the transistor M9, the layout of the pull-down control signal lines PL1, PL2 in the first embodiment (fig. 5) and the control terminal m4_ C, M5_ C, M9_ C, M10_c of the transistors M4, M5, M9, M10 are not laid out separately from each other, and are not shared with the control terminals m4_ C, M5_ C, M9_ C, M10_c of the transistors M4, M5, M9, M10, respectively, the layout of fig. 8A (fig. 5) is smaller in area than the layout of the gate electrode of the first embodiment. By the configuration method described in the second embodiment, the layout area of the shift register in the peripheral area of the display panel can be further reduced, so that the narrow frame requirement of the display panel can be advantageously met. Because of the reduced layout area of the shift register, the distance between the signal line (including the reference potential signal line, the start signal line, the end signal line, the clock signal line, the pull-down control signal line, etc.) and the boundary of the active array substrate (i.e., the boundary of the display panel) can be lengthened, so that the effect of electrostatic discharge can be further enhanced. In addition, through the configuration mode, the pull-down control signal line is not required to cross another pull-down control signal line in a mode of configuring additional connecting wires and connecting structures to be electrically connected with different metal layers, so that the pull-down control signal is transmitted to the transistors in the shift register, and the production cost can be saved.

The configuration method described in the above embodiments may also be applied to other display devices or display panels, such as an odd-shaped display panel, or applied to other display devices or display panels after modification, so as to reduce the layout area, extend the distance between the signal lines and the boundary of the active array substrate, and save the production cost. Referring to fig. 9, fig. 9 is a schematic diagram of a display panel 300 according to an embodiment of the invention. The display panel 300 may be a liquid crystal display panel such as a twisted nematic type, a horizontal switching type, a fringe field switching type, or a vertical alignment type, but is not limited thereto. The display panel 300 includes an active array substrate 302 and has an active region 310 and a peripheral region 320, wherein the active region 310 has a plurality of pixel units disposed on the active array substrate 302, and the peripheral region 320 includes a gate driver 330 for generating a scan signal and transmitting the scan signal to gate lines (not shown in fig. 9) in the active region 310, such that the pixel units in the active region 310 are driven by the scan signal to display an image at a specific time.

In addition, as shown in fig. 9, the display panel 300 is a shaped display panel, that is, the active array substrate 302 is shaped. In fig. 9, the upper left corner, the lower left corner, the upper right corner, and the lower right corner of the display panel 300 are all arc-shaped instead of right angles. In addition, the active region 310 is a shaped active region, and the edge 310E of the active region 310 is similar to the edge 300E of the display panel 300. If the size of each pixel in the active region 310 is the same, the number of pixel units in each pixel row at the top and bottom of the active region 310 is less than the number of pixel units in other pixel rows of the active region 310.

In an embodiment of the invention, the display panel 300 is a system-integrated glass panel. That is, the gate driver 330 is fabricated on the active array substrate 302 of the display panel 300. In this way, the same process can be used to fabricate the electronic devices in the gate driver 330 and the electronic devices in the active region 310 (e.g., but not limited to, thin film transistors, pixel electrodes, etc.).

The display panel of the present invention may have other aspects besides the display panel 300 shown in fig. 9. For example, referring to fig. 10, fig. 10 is a schematic diagram of a display panel 300' according to an embodiment of the invention. As shown in fig. 10, the display panel 300' is a shaped display panel, i.e., the active array substrate 302' is shaped, wherein the upper left corner, the lower left corner, the upper right corner and the lower right corner of the display panel 300' are all arc-shaped, rather than right angles. In addition, the active region 310' is a shaped active region, and the edge 310E ' of the active region 310' is similar to the edge 300E ' of the display panel 300 '. Compared to the display panel 300 of fig. 9, the display panel 300' of fig. 10 further has a recess (notch) in its top region B. The gate driver 330 of fig. 10 is the same as the gate driver 330 of fig. 9, and is not described here.

Fig. 11 shows the pixel cell arrangement and the element configuration in the upper left corner region a of the display panel 300. As shown in fig. 11, in the upper left corner region a, the boundary 310E of the active region 310 is curved. In the active region 310, there are pixel units P, each having a thin film transistor TFT and a pixel electrode PX. Each thin film transistor TFT is coupled to a corresponding data line and a corresponding gate line, and controls whether to input a data signal provided by the corresponding data line to the pixel electrode PX according to a scan signal provided by the corresponding gate line. The thin film transistor TFT may be an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, an indium gallium zinc oxide thin film transistor, or other suitable thin film transistor. The pixel electrode PX is configured to generate an electric field with a common electrode (not shown), so that the liquid crystal molecules in the pixel unit P are twisted by the electric field, and the pixel unit P displays a corresponding gray scale. The region a is a top region of the active region 310 having an arc edge, so the number of the pixel units P coupled to the gate line increases gradually from top to bottom. As shown in fig. 11, in the top region of the active region 310 with the arc edge, the number of the pixel units P coupled to the gate line SL (m) is smaller than the number of the pixel units P coupled to the gate line SL (m+1), and the number of the pixel units P coupled to the gate line SL (m+1) is smaller than the number of the pixel units P coupled to the gate line SL (m+2) (not shown). In contrast, in the bottom region of the active region 310 having the arc-shaped edge, the number of the pixel units P coupled to the gate lines gradually decreases from top to bottom.

Referring to fig. 12, fig. 12 shows the shift register and the device configuration in the upper left corner area a of the display panel 300. As shown in fig. 10 and 12, the shift registers 210 (m) and 210 (m+1) are disposed in the peripheral region 320 and are disposed between the active region 310 and signal lines such as the reference potential signal line VL, the start signal line SL1 and the clock signal lines L1 to L4, and output ends thereof are respectively coupled to the gate lines SL (m) and SL (m+1) to output the scan signals OUT (m) and OUT (m+1) to the gate lines SL (m) and SL (m+1), respectively. In the embodiment of fig. 12, the layout of the transistors and the signal lines in the shift register is exemplified by the layout of the shift register and the signal lines in the second embodiment (fig. 7) of the present invention, that is, the pull-down control signal lines PL1, PL2 penetrate through the layout areas of the shift registers 210 (m), 210 (m+1) and overlap with part of the transistors in the shift registers 210 (m), 210 (m+1). Since the edge 310E of the active region 310 in the upper left corner region a of the display panel 300 and the edge 300E of the display panel 300 are arc-shaped, the shift registers 210 (m), 210 (m+1) are arranged along the edge 310E of the active region 310 in the peripheral region 320, i.e. the projection of the shift registers 210 (m), 210 (m+1) in the direction X is partially overlapped or not overlapped at all, and the extending directions of the signal lines such as the reference potential signal line VL, the start signal line SL1, the clock signal lines L1-L4, the pull-down control signal lines PL1, PL2 are also not completely parallel to the vertical direction (direction Y), i.e. the section of the signal line corresponding to the shift register 210 (m) (or 210 (m+1)) in the direction Y is a broken line. Herein, the section of the signal line corresponding to the shift register 210 (m) (or 210 (m+1)) in the direction Y refers to the section of the signal line between the coordinates a and b in the direction Y when the shift register 210 (m) (or 210 (m+1)) is located between the coordinates a and b in the direction Y. Taking the clock signal line L1 as an example, the section of the clock signal line L1 corresponding to the shift register 210 (m) in the direction Y and the section of the corresponding shift register 210 (m+1) each include at least one line segment (e.g., a line segment parallel to the direction X or a diagonal line segment non-parallel to the direction X and the direction Y) non-parallel to the direction Y, so that the clock signal line L1 is disposed along the edges of the shift registers 210 (m), 210 (m+1). For example, as shown in fig. 12, the section of the clock signal line L1 corresponding to the shift register 210 (m) in the direction Y includes first to third lines LN1 to LN3, wherein the first line LN1 and the third line LN3 are parallel to the direction Y, and two ends of the second line LN2 are respectively connected to the first line LN1 and the third line LN3 and are not parallel to the direction X and the direction Y, but not limited thereto.

It should be noted that the lengths of the first to third line segments LN1 to LN3, the included angle between the first line segment LN1 and the second line segment LN2, and the included angle between the second line segment LN2 and the third line segment LN3 can be adjusted correspondingly according to the tangential slope of the edge 300E of the display panel 300 and/or the configuration position of the shift register. In addition, the clock signal line L1 may also have first to third lines LN1 to LN3 corresponding to the sections of the other shift registers in the direction Y, and the lengths and angles of the first to third lines LN1 to LN3 of each section may be all the same, partially the same, or all different. The arrangement of the other signal lines (e.g., the clock signal lines L2 to L4, the start signal line SL1, and/or the reference potential signal line VL, etc.) may also be similar to the arrangement of the clock signal line L1 described above.

As shown in fig. 12, the area between the shift registers 210 (m) to 210 (m+1) and the active region 310 includes a forward input signal line FL for providing the forward input signal FW, a reverse input signal line BL for providing the reverse input signal BW, and wirings for outputting the scan signals OUT (m-2) to OUT (m+3), respectively. The arrangement of the forward input signal line FL, the reverse input signal line BL and the wirings for outputting the scan signals OUT (m-2) to OUT (m+3) respectively may be similar to the arrangement of the wirings of the clock signal lines L1 to L4, the reference potential signal line VL and the like.

In addition, there is a signal lead VWL between adjacent shift registers, which is coupled to these adjacent shift registers and the reference potential signal line VL to provide the reference potential VGL to the shift registers. As shown in fig. 12, the signal leads VWL are respectively disposed on the upper side of the shift register 210 (m), between the shift registers 210 (m) and 210 (m+1), and on the lower side of the shift register 210 (m), and are coupled to the shift registers 210 (m), 210 (m+1), and the reference potential signal line VL. Each of the signal leads VWL and the reference potential signal line VL belong to the same metal layer.

Fig. 13 is an example of a partial layout of the shift register 210 (m), the clock signal line L1, and the pull-down control signal lines PL1, PL2 in the upper left corner region a of the display panel 300. Referring to fig. 12 and 13, the pull-down control signal line PL1 has a first side PLE1 and a second side PLE2 opposite to each other, wherein the first side PLE1 is closer to an edge 300E of the display panel 300 than the second side PLE2, and the pull-down control signal line PL2 has a third side PLE3 and a fourth side PLE4 opposite to each other, wherein the fourth side PLE4 is closer to an edge 310E of the active region 310 than the third side PLE 3; the transistors M4, M5, M9, M10 are arranged in a region between the first side PLE1 of the pull-down control signal line PL1 and the fourth side PLE4 of the pull-down control signal line PL2, wherein the pull-down control signal line PL1 overlaps the transistors M4, M10 and the pull-down control signal line PL2 overlaps the transistors M5, M9. In comparison with the partial layout shown in fig. 8A, in the partial layout shown in fig. 13, the section of the pull-down control signal line PL1 corresponding to the shift register 210 (m) in the direction Y includes a first line segment PL1S1, a second line segment PL1S2, and a third line segment PL1S3 having different extending directions from each other, wherein the length extending direction of the first line segment PL1S1 is parallel to the vertical direction (direction Y), the length extending direction of the second line segment PL1S2 is parallel to the horizontal direction (direction X), the length extending direction of the third line segment PL1S3 has a non-zero included angle with both the vertical direction (direction Y) and the horizontal direction (direction X), the two ends of the second line segment PL1S2 are coupled to the first line segment PL1S1 and the third line segment PL1S3, respectively, the first line segment PL1S1 overlaps the transistors M4, M10, that is, the first line segment PL1S1 has two protrusions overlapping the channel layers of the transistors M4, M10, respectively, and the section of the pull-down control signal line PL2 corresponding to the shift register 210 (M) in the direction Y includes the first line segment PL2S1 and the second line segment PL2S2 having different extending directions from each other, wherein the length extending direction of the first line segment PL2S1 is parallel to the vertical direction (direction Y), the length extending direction of the second line segment PL2S2 is parallel to the horizontal direction (direction X), and the first line PL2S1 overlaps the transistors M5, M9, i.e. the first line PL2S1 has two protrusions that overlap the channel layers of the transistors M5, M9, respectively. Other arrangements of the pull-down control signal lines PL1, PL2 and the transistors M4, M5, M9, M10 are similar to those described in fig. 7 to 8C, and thus are not repeated here. It should be noted that the sections of the pull-down control signal line PL1 corresponding to the shift register 210 (m) in the direction Y include the first to third line segments PL1S1, PL1S2, PL1S3 having different extending directions from each other, and the sections of the pull-down control signal line PL2 corresponding to the shift register 210 (m) in the direction Y include the first line segment PL2S1 and the second line segment PL2S2 having different extending directions from each other, which are only illustrative and not limiting. The section of the pull-down control signal lines PL1, PL2 corresponding to the shift register 210 (m) in the direction Y may include at least one line segment having a length extending direction parallel to the vertical direction (direction Y) and at least one line segment having a length extending direction not parallel to the vertical direction (direction Y).

Fig. 14 is another example of a partial layout of the shift register 210 (m) in the upper left corner area a of the display panel 300. The partial layout shown in fig. 14 differs from fig. 13 in that in the partial layout shown in fig. 13, a line segment in the length-extending direction parallel direction Y in the pull-down control signal line PL1 has two convex portions partially overlapping the channel layers of the transistors M4, M10, whereas in the partial layout shown in fig. 14, a line segment in the length-extending direction parallel direction Y in the pull-down control signal line PL1 has one convex portion partially overlapping the channel layer of the transistor M4, and another line segment in the length-extending direction non-parallel direction Y and the direction X in the pull-down control signal line PL1 has another convex portion partially overlapping the channel layer of the transistor M10. As shown in fig. 14, the section of the pull-down control signal line PL1 corresponding to the shift register 210 (m) in the direction Y further includes a fourth line segment PL1S4, the length extending direction of the fourth line segment PL1S4 has a non-zero included angle with the vertical direction (direction Y) and the horizontal direction (direction X), two ends of the fourth line segment PL1S4 are coupled to the first line segment PL1S1 and the second line segment PL1S2, respectively, and two ends of the second line segment PL1S2 are coupled to the fourth line segment PL1S4 and the third line segment PL1S3, respectively. In addition, the first line segment PL1S1 has one protruding portion partially overlapping the channel layer of the transistor M4, and the fourth line segment PL1S4 has another protruding portion partially overlapping the channel layer of the transistor M10. The arrangement of the transistors M5 and M9 shown in fig. 14 is the same as that of fig. 13, and thus is not repeated here. Similarly, the sections of the pull-down control signal line PL1 corresponding to the shift register 210 (m) in the direction Y include the first to fourth line segments PL1S1, PL1S2, PL1S3, PL1S4, which are only examples, but not limited thereto. The section of the pull-down control signal line PL1 corresponding to the shift register 210 (M) in the direction Y may include at least one line segment having a length extending direction parallel to the vertical direction (direction Y) and at least one line segment having a length extending direction not parallel to the vertical direction (direction Y), and at least one line segment having a length extending direction not parallel to the direction Y in the pull-down control signal line PL1 has at least one protrusion partially overlapping with the channel layer of at least one of the transistors M4, M10.

The element configurations in the above embodiments may also be applied to a display device in which the gate drivers are respectively disposed on opposite sides (e.g., left and right sides) of the display panel. Referring to fig. 15, fig. 15 is a schematic diagram of a display device 400 according to an embodiment of the invention. The display device 400 includes a display panel 410, a source driver 420, and gate drivers 430A, 430B. The display panel 410 includes an active array substrate 412, and the active array substrate includes a plurality of data lines DL, a plurality of gate lines SL and a plurality of pixels PX. The display panel 410 may be, for example, a twisted nematic, a horizontal switching, a fringe field switching, or a vertical alignment type liquid crystal display panel, but is not limited thereto. The source driver 420 is electrically connected to the display panel 410, and is used for transmitting source driving signals to the display panel 410. The display panel 410 has an active area AA and a peripheral area PA, and the gate drivers 430A and 430B are disposed in the peripheral area PA, and are used for generating scan signals and transmitting the scan signals to the gate lines in the active area AA, respectively, so that the pixels PX in the active area AA are driven by the source driving signals and the scan signals to display images at a specific time. As shown in fig. 15, the gate drivers 430A, 430B are disposed in the peripheral area PA and are located at both sides of the display panel 410, respectively.

In the embodiment of the invention, the display panel 410 is a system-integrated glass panel. That is, the gate drivers 430A, 430B are fabricated in the display panel 410. In this way, the same process can be used to fabricate the electronic components in the gate drivers 430A and 430B and the electronic components in the active area AA (e.g., but not limited to, thin film transistors, pixel electrodes, etc.).

In addition, although the active area AA of the display panel 410 in fig. 15 is rectangular, the shape is not limited thereto. In a variant embodiment, the display panel 410 may be a special-shaped display panel, i.e. the active area AA is non-rectangular in shape, and the gate drivers 430A, 430B are respectively located in the peripheral area PA outside the opposite sides of the active area AA.

Fig. 16 is a schematic diagram of a gate driving circuit 500A, 500B according to an embodiment of the invention. The gate driving circuits 500A and 500B may respectively correspond to two gate drivers respectively located at two sides of the display panel in the dual-side driving display panel. For example, the gate drivers 430A, 430B of fig. 15 may include gate driving circuits 500A, 500B, respectively. As shown in fig. 16, the gate driving circuit 500A includes shift registers 510A (1), 510A (2), …, 510A (M), and the gate driving circuit 500B includes shift registers 510B (1), 510B (2), …, 510B (M). The following description takes the example in which the gate driving circuits 500A and 500B correspond to the gate drivers 430A and 430B of fig. 15, respectively. The shift registers 510A (1), 510A (2), …, 510A (M) are used for sequentially outputting the scan signals OUTA (1) to OUTA (M) to the scan lines in the active region AA. Similarly, the shift registers 510B (1), 510B (2), …, 510B (M) are configured to sequentially output the scan signals OUTB (1) to OUTB (M) to the scan lines in the active area AA. In the gate driving circuits 500A and 500B, the same level of shift registers outputs scan signals to the same gate line, i.e., the shift registers 510A (1) and 510B (1) are coupled to the first gate line, and the shift registers 510A (2) and 510B (2) are coupled to the second gate line …, so as to increase the driving capability of the display panel 410. The equivalent circuits of the shift registers 510A (1) to 510A (M), 510B (1) to 510B (M) are the same as those of the shift register 210 (i) of fig. 3. Further, the gate driving circuit 500A includes clock signal lines LA1 to LA4, a start signal line SLA1, an end signal line SLA2, pull-down control signal lines PLA1, PLA2, and a reference potential signal line VLA, and the gate driving circuit 500B includes clock signal lines LB1 to LB4, a start signal line SLB1, an end signal line SLB2, pull-down control signal lines PLB1, PLB2, and a reference potential signal line VLB. Signals supplied from the clock signal lines LA1 to LA4, the start signal line SLA1, the end signal line SLA2, the pull-down control signal lines PLA1, PLA2, and the reference potential signal line VLA may correspond to signals supplied from the clock signal lines L1 to L4, the start signal line SL1, the end signal line SL2, the pull-down control signal lines PL1, PL2, and the reference potential signal line VL, respectively, of fig. 2. Similarly, signals supplied from the clock signal lines LB1 to LB4, the start signal line SLB1, the end signal line SLB2, the pull-down control signal lines PLB1, PLB2, and the reference potential signal line VLB may correspond to signals supplied from the clock signal lines L1 to L4, the start signal line SL1, the end signal line SL2, the pull-down control signal lines PL1, PL2, and the reference potential signal line VL, respectively, of fig. 2.

The arrangement of the signal lines such as the start signal line SLA1, the clock signal lines LA1 to LA4, the pull-down control signal lines PLA1 and PLA2, and the reference potential signal line VLA in the gate driving circuit 500A may be the same as the arrangement of the signal lines such as the start signal line SL1, the clock signal lines L1 to L4, the pull-down control signal lines PL1 and PL2, and the reference potential signal line VL shown in fig. 7, and the layout of the elements such as the pull-down control signal lines PLA1 and PLA2 and the transistors (and the transistors M4, M5, M9, and M10) coupled thereto may be the same as the layout of fig. 8A to 8C. Since the gate driving circuits 500A and 500B are disposed on the left and right sides of the display panel 410, the arrangement and layout of the signal lines such as the start signal line SLB1, the clock signal lines LB1 to LB4, the pull-down control signal lines PLB1 and PLB2, and the reference potential signal line VLB are mirror-symmetrical in the direction Y with respect to the arrangement of the signal lines such as the start signal line SLA1, the clock signal lines LA1 to LA4, the pull-down control signal lines PLA1 and PLA2, and the reference potential signal line VLA. In the variant embodiment of the special-shaped panel, the arrangement of the wirings such as the start signal line SLA1, the clock signal lines LA1 to LA4, the pull-down control signal lines PLA1 and PLA2, and the reference potential signal line VLA may be the same as the arrangement of the signal lines such as the start signal line SL1, the clock signal lines L1 to L4, the pull-down control signal lines PL1 and PL2, and the reference potential signal line VL shown in fig. 12, and the layout of the elements such as the pull-down control signal lines PLA1 and PLA2 and the transistors (and the transistors M4, M5, M9 and M10) coupled thereto may be the same as the layout of fig. 13 or 14.

Fig. 17 is a schematic diagram of gate driving circuits 600A and 600B according to an embodiment of the invention. The gate driving circuits 600A and 600B may respectively correspond to two gate drivers respectively located at two sides of the display panel in the dual-side driving display panel. For example, gate drive circuit 600A may correspond to gate driver 430A of FIG. 15 and includes shift registers 610 (1), 610 (3), …, 610 (M-1), while gate drive circuit 600B may correspond to gate driver 430B of FIG. 15 and includes shift registers 610 (2), 610 (4), …, 610 (M). The combination of the gate driving circuit 600A and the gate driving circuit 600B may correspond to the gate driver 200 of fig. 2, i.e., the shift registers 610 (1), 610 (3), …, 610 (M-1) correspond to the odd-numbered stage shift registers 210 (1), 210 (3), …, 210 (M-1) in the gate driver 200, respectively, and the shift registers 610 (2), 610 (4), …, 610 (M) correspond to the even-numbered stage shift registers 210 (2), 210 (4), …, 210 (M) in the gate driver 200, respectively.

The shift registers 610 (1) to 610 (M) are used for sequentially outputting the scan signals OUT (1) to OUT (M) to the scan lines in the active area AA. The equivalent circuit of the shift registers 610 (1) to 610 (M) is the same as that of the shift register 210 (i) shown in fig. 3. Further, the gate driving circuit 600A includes a reference potential signal line VLA, a start signal line SLA1, an end signal line SLA2, pull-down control signal lines PLA1, PLA2, and clock signal lines L1, L3, and the gate driving circuit 600B includes a reference potential signal line VLB, a start signal line SLB1, an end signal line SLB2, pull-down control signal lines PLB1, PLB2, and clock signal lines L2, L4. The signals supplied from the clock signal lines L1 to L4 correspond to the signals supplied from the clock signal lines L1 to L4 of fig. 2, respectively, the signals supplied from the start signal lines SLA1, SLB1 correspond to the signals supplied from the start signal line SL1 of fig. 2, the signals supplied from the end signal lines SLA2, SLB2 correspond to the signals supplied from the end signal line SL2 of fig. 2, the pull-down control signal lines PLA1, PLB1 correspond to the signals supplied from the pull-down control signal line PL1 of fig. 2, the pull-down control signal lines PLA2, PLB2 correspond to the signals supplied from the pull-down control signal line PL2 of fig. 2, and the signals supplied from the reference potential signal lines VLA, VLB correspond to the signals supplied from the reference potential signal line VL of fig. 2.

The arrangement of the reference potential signal line VLA, the start signal line SLA1, the clock signal lines LA1 and LA3, the pull-down control signal lines PLA1 and PLA2, and the like may be similar to the arrangement of the reference potential signal line VL, the start signal line SL1, the clock signal lines L1 and L3, the pull-down control signal lines PL1 and PL2, and the like shown in fig. 7, and the arrangement of the pull-down control signal lines PLA1 and PLA2, and the transistors (and the transistors M4, M5, M9 and M10) coupled thereto may be the same as the arrangement of fig. 8A to 8C. In addition, the arrangement and layout of the reference potential signal line VLB, the start signal line SLB1, the clock signal lines LA2 and LA4, and the pull-down control signal lines PLB1 and PLB2 may be similar to the arrangement of the reference potential signal line VL, the start signal line SL1, the clock signal lines L2 and L4, and the pull-down control signal lines PL1 and PL2 shown in fig. 7 after the signal lines are turned right and left. In a variant embodiment of the special-shaped panel, the arrangement of the wirings such as the start signal line SLA1, the clock signal lines LA1 and LA3, the pull-down control signal lines PLA1 and PLA2, and the reference potential signal line VLA may be the same as the arrangement of the signal lines such as the start signal line SL1, the clock signal lines L1 and L3, the pull-down control signal lines PL1 and PL2, and the reference potential signal line VL shown in fig. 12, and the layout of the elements such as the pull-down control signal lines PLA1 and PLA2 and the transistors (and the transistors M4, M5, M9 and M10) coupled thereto may be the same as the layout of fig. 13 or 14.

In summary, the gate driving circuit and the display panel of the present invention can reduce the layout area, extend the distance between the signal line and the boundary of the active array substrate, and save the production cost.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather, it should be apparent to one skilled in the art that various changes and modifications can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1.A gate driving circuit, comprising:

A plurality of shift registers, providing a plurality of scanning signals to a plurality of gate lines of a display panel, wherein each shift register comprises a first transistor and a second transistor, and the gates of the first transistor and the second transistor respectively receive a first signal and a second signal; and

A first signal line and a second signal line providing the first signal to the gate of the first transistor and the second signal to the gate of the second transistor, respectively, wherein the first transistor partially overlaps the first signal line and the second transistor partially overlaps the second signal line; the first signal line is provided with a first extension part and a first protruding part, the second signal line is provided with a second extension part and a second protruding part, the channel layer of the first transistor is at least partially arranged on the first protruding part, and the channel layer of the second transistor is at least partially arranged on the second protruding part.

2. The gate drive circuit of claim 1, wherein a portion of the first signal line concurrently serves as a gate of the first transistor and a portion of the second signal line concurrently serves as a gate of the second transistor.

3. The gate driving circuit of claim 1, wherein a portion and another portion of the channel layer of the first transistor are disposed on the first extension and the first protrusion, respectively, and a portion and another portion of the channel layer of the second transistor are disposed on the second extension and the second protrusion, respectively.

4. The gate driving circuit of claim 1, wherein the first signal line has opposite first and second sides, the second signal line has opposite third and fourth sides, the second side of the first signal line and the third side of the second signal line are opposite each other, and the first transistor, the second transistor, the first protrusion, and the second protrusion are located between the first side of the first signal line and the fourth side of the second signal line.

5. The gate driving circuit of claim 4, wherein any one of the gate lines of the display panel extends along a first direction, and a projection of the first protrusion in the first direction overlaps a projection of the second protrusion in the first direction.

6. The gate driving circuit as recited in claim 4 wherein each of said shift registers further comprises a third transistor and a fourth transistor, wherein gates of said third transistor and said fourth transistor respectively receive said first signal and said second signal, wherein said first signal line and said second signal line respectively further have a third protrusion and a fourth protrusion, wherein said third transistor, said fourth transistor, said third protrusion and said fourth protrusion are located between said first side of said first signal line and said fourth side of said second signal line, wherein a channel layer of said third transistor is at least partially disposed on said third protrusion, and wherein a channel layer of said fourth transistor is at least partially disposed on said fourth protrusion.

7. The gate driving circuit of claim 6, wherein any one of the gate lines of the display panel extends along a first direction, a projection of at least one of the first and third protrusions in the first direction partially overlaps a projection of at least one of the second and fourth protrusions in the first direction.

8. The gate drive circuit of claim 1, wherein each of the shift registers further comprises:

a precharge unit coupled to a first node and outputting a precharge signal from the first node;

A pull-up unit coupled to the first node and the second node, the pull-up unit outputting one of the plurality of scan signals to the corresponding one of the plurality of gate lines from the second node; and

And a pull-down unit coupled to the first node and the second node, the pull-down unit including the first transistor and the second transistor, the pull-down unit receiving the precharge signal, the first signal, and the second signal.

9. A display panel having an active region and a peripheral region, the display panel comprising:

a plurality of gate lines; and

A gate drive circuit located in the peripheral region, the gate drive circuit comprising:

A plurality of shift registers, providing a plurality of scanning signals to the plurality of gate lines, wherein each shift register comprises a first transistor and a second transistor, and the gates of the first transistor and the second transistor respectively receive a first signal and a second signal; and

The first signal line and the second signal line respectively provide the first signal to the grid electrode of the first transistor and the second signal to the grid electrode of the second transistor, wherein the first transistor is partially overlapped with the first signal line, the second transistor is partially overlapped with the second signal line, the first signal line is provided with a first extension part and a first bulge, the second signal line is provided with a second extension part and a second bulge, a channel layer of the first transistor is at least partially arranged on the first bulge, and a channel layer of the second transistor is at least partially arranged on the second bulge.

10. The display panel of claim 9, wherein the display panel is a system-integrated glass panel.