CN112634802A

CN112634802A - Gate drive circuit and display panel

Info

Publication number: CN112634802A
Application number: CN201910949746.XA
Authority: CN
Inventors: 詹建廷
Original assignee: Hannstar Display Corp
Current assignee: Hannstar Display Corp
Priority date: 2019-10-08
Filing date: 2019-10-08
Publication date: 2021-04-09
Anticipated expiration: 2039-10-08
Also published as: CN112634802B

Abstract

The invention discloses a gate driving circuit and a display panel. The gate driving circuit includes a plurality of shift registers, a first signal line, and a second signal line. The shift registers respectively provide scanning signals to a plurality of gate lines of the display panel. Each shift register comprises a first transistor and a second transistor, and the grid electrode of the first transistor and the grid electrode of the second transistor respectively receive a first signal and a second signal. The first signal line and the second signal line respectively provide a first signal to a gate of the first transistor and a second signal to a gate of the second transistor, wherein the first transistor partially overlaps the first signal line, and the second transistor partially overlaps the second signal line. The invention at least has the advantages of reducing the layout area, prolonging the distance between the signal line and the boundary of the active array substrate, saving the production cost and the like.

Description

Gate drive circuit and display panel

Technical Field

The present invention relates to a gate driving circuit and a display panel, and more particularly, to a gate driving circuit and a display panel having the same.

Background

With the continuous progress of Thin Film Transistor (TFT) liquid crystal display technology, a technology of integrating a driving circuit (e.g., a gate driving circuit) on a display panel, such as a system-in-glass panel, has been widely used in the present display devices to minimize the size of the display device and to improve the performance of the display device. For the display panel with integrated gate driver, the gate driver and the pixel unit are both disposed on the active array substrate and located in the peripheral region and the active region of the display panel, respectively, so that the configuration space of the gate driver needs to be reserved in the peripheral region, which results in an increase in the width of the peripheral region, which is not favorable for the narrow frame requirement of the display panel.

Disclosure of Invention

The present invention is directed to a gate driving circuit and a display panel, which reduce the layout area of a shift register in the peripheral area of the display panel, thereby facilitating the realization of the narrow frame requirement of the display panel, and the distance between the signal line and the boundary of an active array substrate can be extended, so as to further enhance the electrostatic discharge effect.

In accordance with the above object, the present invention provides a gate driving circuit, which includes a plurality of shift registers, a first signal line and a second signal line. The shift registers respectively provide scanning signals to a plurality of gate lines of the display panel. Each shift register comprises a first transistor and a second transistor, and the grid electrode of the first transistor and the grid electrode of the second transistor respectively receive a first signal and a second signal. The first signal line and the second signal line respectively provide a first signal to a gate of the first transistor and a second signal to a gate of the second transistor, wherein the first transistor partially overlaps the first signal line, and the second transistor partially overlaps the second signal line.

According to an embodiment of the present invention, a portion of the first signal line simultaneously serves as the gate of the first transistor, and a portion of the second signal line simultaneously serves as the gate of the second transistor.

According to another embodiment of the present invention, the first signal line has a first extension portion and a first protrusion portion, the second signal line has a second extension portion and a second protrusion portion, the channel layer of the first transistor is at least partially disposed on the first protrusion portion, and the channel layer of the second transistor is at least partially disposed on the second protrusion portion.

According to another embodiment of the present invention, a portion and another portion of the channel layer of the first transistor are disposed on the first extension portion and the first protrusion, respectively, and a portion and another portion of the channel layer of the second transistor are disposed on the second extension portion and the second protrusion, respectively.

According to yet another embodiment of the present invention, the first signal line has a first side and a second side opposite to each other, the second signal line has a third side and a fourth side opposite to each other, the second side of the first signal line and the third side of the second signal line are opposite to each other, and the first transistor, the second transistor, the first protrusion and the second protrusion are located between the first side of the first signal line and the fourth side of the second signal line.

According to another embodiment of the present invention, any one of the gate lines of the display panel extends along a first direction, and a projection of the first protrusion portion in the first direction partially overlaps a projection of the second protrusion portion in the first direction.

According to another embodiment of the present invention, each of the shift registers further includes a third transistor and a fourth transistor, gates of the third transistor and the fourth transistor respectively receive the first signal and the second signal, the first signal line and the second signal line respectively further have a third protrusion and a fourth protrusion, the third transistor, the fourth transistor, the third protrusion and the fourth protrusion are located between the first side of the first signal line and the fourth side of the second signal line, a channel layer of the third transistor is at least partially disposed on the third protrusion, and a channel layer of the fourth transistor is at least partially disposed on the fourth protrusion.

According to another embodiment of the present invention, any one of the gate lines of the display panel extends along a first direction, and a projection of at least one of the first protrusion and the third protrusion in the first direction partially overlaps a projection of at least one of the second protrusion and the fourth protrusion in the first direction.

According to another embodiment of the present invention, each shift register further includes a precharge unit, a pull-down unit, and a pull-down unit. The precharge unit is coupled to the first node and outputs a precharge signal from the first node. The pull-up unit is coupled to the first node and the second node, and outputs one of the scan signals from the second node to a corresponding one of the gate lines. The pull-down unit is coupled to a first node and a second node, the pull-down unit includes the first transistor and the second transistor, and the pull-down unit receives a precharge signal, the first signal and the second signal.

According to the aforesaid objective, the present invention further provides a display panel having an active area and a peripheral area. The display panel comprises a plurality of gate lines and a gate driving circuit. The gate driving circuit is located in the peripheral region and includes a plurality of shift registers, a first signal line and a second signal line. The shift registers provide a plurality of scan signals to the gate lines. Each of the shift registers includes a first transistor and a second transistor, and a gate of the first transistor and a gate of the second transistor respectively receive a first signal and a second signal. The first signal line and the second signal line respectively provide a first signal to a gate of the first transistor and a second signal to a gate of the second transistor, wherein the first transistor partially overlaps the first signal line, and the second transistor partially overlaps the second signal line.

According to an embodiment of the present invention, the display panel is a system-integrated glass panel.

The invention has the beneficial effects that the layout area of the shift register in the peripheral area of the display panel can be further reduced by the configuration mode, and the narrow frame requirement of the display panel is further favorably realized. Due to the reduced layout area of the shift register, the distance between the signal lines (including the reference potential signal line, the start signal line, the end signal line, the clock signal line, the pull-down control signal line, etc.) and the boundary of the active array substrate (i.e., the boundary of the display panel) can be increased, thereby further enhancing the electrostatic discharge effect. In addition, through the configuration mode, the pull-down control signal line does not need to cross another pull-down control signal line in a mode of configuring an additional connecting structure to be electrically connected with different metal layers to transmit the pull-down control signal to the transistor in the shift register, so that the production cost can be saved.

Drawings

For a more complete understanding of the embodiments and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention;

FIG. 2 is a diagram of a gate driving circuit according to an embodiment of the invention;

FIG. 3 is an equivalent circuit diagram of a shift register in the gate driving circuit of FIG. 2;

FIG. 4 is a layout diagram of a shift register and signal lines according to a first embodiment of the present invention;

FIG. 5 is a partial enlarged view of the layout diagram shown in FIG. 4;

fig. 6A is a layout diagram of the first conductive layer in fig. 5;

FIG. 6B is a layout diagram of the first conductive layer and the channel layer in FIG. 5;

FIG. 6C is a layout diagram of the first conductive layer, the channel layer and the connection structure in FIG. 5;

FIG. 6D is a layout diagram of the first conductive layer, the channel layer, the connection structure and the second conductive layer in FIG. 5;

FIG. 7 is a layout diagram of a shift register and signal lines according to a second embodiment of the present invention;

FIG. 8A is a partial enlarged view of the layout diagram shown in FIG. 7;

FIG. 8B is a partially enlarged view of the pull-down control signal line shown in FIG. 8A;

FIG. 8C is a partially enlarged view of the pull-down control signal line, the channel layer and the connection structure shown in FIG. 8A;

FIG. 9 is a diagram of a display panel according to an embodiment of the present invention;

FIG. 10 is a diagram illustrating a display panel according to an embodiment of the present invention;

FIG. 11 shows pixel cell arrangements and element configurations in the upper left corner region of the display panel of FIG. 9;

FIG. 12 shows a shift register and element arrangement in the upper left corner region of the display panel of FIG. 9;

FIG. 13 is an example of a partial layout diagram of a shift register, clock signal lines, and pull-down control signal lines in the upper left corner region of the display panel of FIG. 9;

fig. 14 is another example of a partial layout diagram of a shift register, clock signal lines, and pull-down control signal lines in an upper left corner region of the display panel of fig. 9;

FIG. 15 is a diagram illustrating a display panel according to an embodiment of the present invention;

FIG. 16 is a diagram of a gate driving circuit according to an embodiment of the invention; and

FIG. 17 is a diagram of a gate driving circuit according to an embodiment of the invention.

Detailed Description

Embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are merely illustrative and are not intended to limit the scope of the present invention.

It will be understood that, although the terms "first," "second," "third," …, etc. may be used herein to describe various elements, components, regions and/or sections, these elements, components, regions and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region and/or section from another element, component, region and/or section.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. The singular forms "a", "an" and "the" are intended to mean "a", "an" and "the" unless the context clearly dictates otherwise. Furthermore, the spatially relative terms are used for descriptive purposes and not necessarily for limiting the relative orientations of the elements in use or operation. Elements may also be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted in a similar manner.

Reference numerals and/or letters may be repeated among the various embodiments for simplicity and clarity of illustration, but are not intended to indicate a resulting relationship between the various embodiments and/or configurations discussed.

As used herein, the term "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and "coupled" may mean that two or more elements are in operation or act with each other.

Referring to fig. 1, fig. 1 is a schematic view of a display device 100 according to an embodiment of the invention. The display device 100 includes a display panel 110, a source driver 120, and a gate driver 130. The display panel 110 may be various types of liquid crystal display panels such as a Twisted Nematic (TN) type, an in-plane switching (IPS) type, an FFS (fringe-field switching) type, or a VA (vertical alignment) type, or an organic light-emitting diode (OLED) display panel, but is not limited thereto. The source driver 120 is electrically connected to the display panel 110, and is configured to convert the image data into a source driving signal and transmit the source driving signal to the display panel 110. The gate driver 130 is configured to generate a gate driving signal and transmit the gate driving signal to the display panel 110. The display panel 110 has an active area AA (also referred to as a display area AA) in which a plurality of data lines DL, a plurality of gate lines SL and a plurality of pixels PX formed on an active array substrate 112 of the display panel 110 are disposed, the pixels PX being commonly driven by a source driving signal and a gate driving signal to display an image, and a peripheral area PA in which a plurality of wirings (not shown) coupled to the source driver 120 and the gate driver 130, respectively, and coupled to the plurality of data lines DL and the gate lines SL in the active area AA, respectively, to supply the source driving signal and the gate driving signal to thin film transistors TFT on the active array substrate 112 and at corresponding pixels PX, respectively, such that the pixels PX are controlled by the thin film transistors TFT to display a corresponding gray level at a specific time.

The display panel 110 of the present invention is a System On Glass (SOG) panel, that is, the gate driver 130 is formed in the display panel 110. Therefore, the same process can be used to simultaneously manufacture the electronic devices in the display panel 110 and the gate driver 130. For example, the thin film transistors in the gate driver 130 may be fabricated simultaneously with the thin film transistors in the active area AA of the display panel 110 by using the same process. In other embodiments, the source driver 120 may also be fabricated in the peripheral region PA of the display panel 110, and the same process may be used to fabricate the electronic components and the wiring in the display panel 110, the source driver 120, and the gate driver 130 at the same time.

Fig. 2 is a schematic diagram of a gate driving circuit 200 according to an embodiment of the invention. The gate driving circuit 200 is suitable for the display device 100 of fig. 1 or other similar display devices. The following description is given by taking the display device 100 of fig. 1 as an example, that is, the gate driver 130 of fig. 1 includes a gate driving circuit 200. The gate driving circuit 200 is located at the left edge of the display panel 110 and disposed in the peripheral region PA. The gate driving circuit 200 includes a plurality of signal lines including a reference potential signal line VL, a start signal line SL1, an end signal line SL2, clock signal lines L1 to L4, and pull-down control signal lines PL1 and PL2, and the plurality of signal lines each transmit a signal to at least one of the 1 st to M th shift registers 210(1) to 210(M), and the 1 st to M th shift registers 210(1) to 210(M) respectively and sequentially output scan signals OUT (1) to OUT (M) to the 1 st to M th gate lines in the active area AA, where M is a positive integer greater than or equal to 5. For example, in the same frame period (frame period), the 1 st stage shift register 210(1) outputs the 1 st stage scan signal OUT (1) to the 1 st gate line, the 2 nd stage shift register 210(2) outputs the 2 nd stage scan signal OUT (2) to the 2 nd gate line after a time t, the 3 rd stage shift register 210(3) outputs the 3 rd stage scan signal OUT (3) to the 3 rd gate line after a time t, and so on until the M th stage shift register 210(M) outputs the M th stage scan signal OUT (M) to the M th gate line. In some embodiments, as shown in fig. 2, M is a multiple of 4, and the clock signal line L1 provides the clock signal C1 to the 1 st, 5 th, … and (M-3) th shift registers 210(M-3), the clock signal line L2 provides the clock signal C2 to the 2 nd, 6 th, … and (M-2) th shift registers 210(2), (6) and 210(M-2), the clock signal line L3 provides the clock signal C3 to the 3 rd, 210(3), 7 th, … and (M-1) th shift registers 210(M-1), and the clock signal line L4 provides the clock signal C4 to the 4 th, 8 th and 3 th shift registers 210(M-1), 210(M-1), …, and an Mth stage shift register 210 (M). The clock signals C1-C4 are all periodic signals and have the same period length, wherein the clock signal C2 lags behind the clock signal C1 by 1/4 period times, the clock signal C3 lags behind the clock signal C2 by 1/4 period times, and the clock signal C4 lags behind the clock signal C3 by 1/4 period times. In addition, the reference potential signal line VL provides the reference potential signal VGL to the 1 st to M-th shift registers 210(1) -210 (M), the start signal line SL1 provides the start signal STV1 to the 1 st and 2 nd shift registers 210(1), 210(2), and the end signal line SL2 provides the end signal STV2 to the (M-1) th and M-th shift registers 210(M-1), 210 (M). The pull-down control signal lines PL1, PL2 supply pull-down control signals GPWL1, GPWL2 to the 1 st to M th stage shift registers 210(1) to 210(M), respectively. The reference potential signal line VL, the start signal line SL1, the end signal line SL2, the clock signal lines L1-L4, and the pull-down control signal lines PL1, PL2 may be coupled to one or more chips, i.e., the reference potential signal VGL, the clock signals C1-C4, the start signal STV1, the end signal STV2, and the pull-down control signals GPWL1, GPWL2 may be provided by one or more chips, such as a driver chip and/or a timing control chip, but are not limited thereto. It should be noted that, for the sake of simplicity, fig. 2 does not show all signal lines in the present embodiment. For example, the plurality of signal lines of the gate driving circuit 200 may further include a forward signal line FL and a reverse signal line BL for providing a forward input signal FW and a reverse input signal BW to the 1 st to M th shift registers 210(1) -210 (M), respectively, but not limited thereto.

Fig. 3 is an equivalent circuit diagram of the ith stage of shift register 210(i) in the gate driving circuit 200 according to fig. 2, wherein i is a positive integer from 1 to M. As shown in fig. 3, the ith stage of shift register 210(i) includes a pre-charge unit 212, a pull-up unit 214, a first pull-down unit 216 and a second pull-down unit 218, wherein one end of the pre-charge unit 212, the pull-up unit 214, the first pull-down unit 216 and the second pull-down unit 218 is coupled to a node X1, the other end of the pull-up unit 214, the first pull-down unit 216 and the second pull-down unit 218 is coupled to a node X2, and a node X2 is coupled to the ith gate line. The precharge unit 212 outputs a precharge signal pc (i) to the node X1, and the pull-up unit 214 outputs an i-th stage scan signal out (i) to the node X2. Herein, the nodes X1 and X2 may also be referred to as a first node X1 and a second node X2, respectively, and the node X2 may also be referred to as an output terminal of the ith stage of shift register 210 (i).

The precharge unit 212 receives the input signals IN1, IN2, and outputs a precharge signal pc (i) to the node X1 according to the input signals IN1, IN 2. The precharge unit 212 includes transistors M1, M2. IN the present embodiment, the gate driving circuit 200 is a bidirectional scanning driving circuit, and IN each of the shift registers 210(1) -210 (M), the control terminal of the transistor M1 receives the input signal IN1, the first terminal of the transistor M1 receives the forward input signal FW, and the second terminal of the transistor M1 outputs the precharge signal pc (i). The control terminal of the transistor M2 receives the input signal IN2, the first terminal of the transistor M2 receives the inverted input signal BW, the second terminal of the transistor M2 is coupled to the second terminal of the transistor M1, and the second terminals of the transistor M1 and the transistor M2 are coupled to the node X1. Herein, the "control terminal", "first terminal", and "second terminal" of the transistor refer to a gate, a source, and a drain of the transistor, respectively, or refer to a gate, a drain, and a source of the transistor, respectively. In other variations, the gate driving circuit 200 may be a unidirectional scan driving circuit, that is, the difference from fig. 3 is that the first terminal of the transistor M1 and the first terminal of the transistor M2 in each of the shift registers 210(1) to 210(M) in the present variation receive a high voltage and a low voltage respectively, or receive a low voltage and a high voltage respectively. For example, the first terminal of the transistor M1 and the first terminal of the transistor M2 may receive a gate high Voltage (VGH) and a gate low Voltage (VGL), respectively, or receive a gate low voltage and a gate high voltage, respectively, but not limited thereto.

If the shift register 210(i) is a1 st or 2 nd stage shift register (i.e., i is 1 or 2), the input signal IN1 is the start signal STV1, and the input signal IN2 is the scan signal OUT (i +2) output by the (i +2) th stage shift register 210(i +2) (i.e., the 3 rd stage scan signal OUT (3) or the 4 th stage scan signal OUT (4)). If the shift register 210(i) is any one of the 3 rd to (M-2) th shift registers (i.e., i is any positive integer from 3 to (M-2)), the input signals IN1 and IN2 are the (i-2) th scan signal OUT (i-2) output by the (i-2) th shift register 210(i-2) and the (i +2) th scan signal OUT (i +2) output by the (i +2) th shift register 210(i +2), respectively. If the shift register 210(i) is the (M-1) th stage or the M-th stage (i.e., i is (M-1) or M), the input signal IN1 is the scan signal OUT (i-2) outputted by the (i-2) th stage shift register 210(i-2) (i.e., the (M-3) th stage scan signal OUT (M-3) or the (M-2) th stage scan signal OUT (M-2)), and the input signal IN2 is the end signal STV 2.

The pull-up unit 214 is coupled to the precharge unit 212, receives the precharge signal PC (i) and the clock signal CN, and outputs the scan signal OUT (i) to the node X2 according to the precharge signal PC (i) and the clock signal CN, wherein the clock signal CN is any one of the clock signals C1C 4. In the embodiment where M is a multiple of 4, if i is 1, 5, …, (M-3), the clock signal CN is the clock signal C1; if i is 2, 6, … or (M-2), the clock signal CN is the clock signal C2; if i is 3, 7, … or (M-1), the clock signal CN is the clock signal C3; if i is 4, 8, …, M, the clock signal CN is the clock signal C4. The pull-up unit 214 includes a transistor M3 and a capacitance Cx. The control terminal of the transistor M3 receives the precharge signal pc (i), the first terminal of the transistor M3 receives the clock signal CN, and the second terminal of the transistor M3 outputs the scan signal out (i). The first terminal of the capacitor Cx is coupled to the control terminal of the transistor M3, and the second terminal of the capacitor Cx is coupled to the second terminal of the transistor M3.

The first pull-down unit 216 is coupled to the precharge unit 212 and the pull-up unit 214, receives the precharge signal pc (i) and the pull-down control signals GPWL1 and GPWL2, and controls whether to pull down the scan signal out (i) to the reference potential according to the precharge signal pc (i) and the pull-down control signals GPWL1 and GPWL 2. The reference potential in this embodiment is a low gate Voltage (VGL), but not limited thereto. In frame time, the pull-down control signals GPWL1 and GPWL2 are inverse to each other, i.e., one of the pull-down control signals GPWL1 and GPWL2 is high and the other is low. Herein, the pull-down control signals GPWL1 and GPWL2 may also be referred to as a first pull-down control signal and a second pull-down control signal, respectively. The first pull-down unit 216 includes transistors M4-M8. The control terminal and the first terminal of the transistor M4 input a pull-down control signal GPWL 1. The control terminal of the transistor M5 inputs the pull-down control signal GPWL2, the first terminal of the transistor M5 is coupled to the reference voltage VGL, the second terminal of the transistor M5 is coupled to the second terminal of the transistor M4, and the second terminals of the transistor M5 and the transistor M4 are coupled to the node P. The control terminal of the transistor M6 is coupled to the node X1, the first terminal of the transistor M6 is coupled to the reference voltage VGL, and the second terminal of the transistor M6 is coupled to the second terminal of the transistor M4. The control terminal of the transistor M7 is coupled to the second terminal of the transistor M6, the first terminal of the transistor M7 is coupled to the reference voltage VGL, and the second terminal of the transistor M7 is coupled to the node X1. The control terminal of the transistor M8 is coupled to the second terminal of the transistor M6, the first terminal of the transistor M8 is coupled to the reference voltage VGL, and the second terminal of the transistor M8 is coupled to the node X2. When the shift register 210(i) outputs the scan signal out (i) to activate the corresponding pixel row (row), i.e., the scan signal out (i) rises to the high level and stays at the high level for a period of time and then falls to the low level, the node X1 falls from the high level to the low level, and the first pull-down unit 216 starts to operate. When the pull-down control signal GPWL1 is low and the pull-down control signal GPWL2 is high, the node P is at a low state, such that the transistors M7 and M8 are turned off; when the pull-down control signal GPWL1 is high and the pull-down control signal GPWL2 is low, the node P is at a high state, so that the transistors M7 and M8 are turned on to set the potentials of the nodes X1 and X2 to the reference potential VGL. In a frame time, when the shift register 210(i) outputs the scan signal out (i) to activate the corresponding pixel row, that is, the scan signal out (i) rises to the high level and maintains the high level for a period of time and then falls to the low level, if the noise signal is coupled to the node X1 and/or the node X2 to cause the ripple of the potential of the node X1 and/or the node X2, the turned-on transistors M7 and M8 pull down the nodes X1 and X2 to the low level (e.g., the reference voltage VGL), that is, pull down and maintain the scan signal out (i) at the low level, without the scan signal out (i) being interfered by the noise.

The second pull-down unit 218 is coupled to the precharge unit 212 and the pull-up unit 214, receives the precharge signal pc (i) and the pull-down control signals GPWL1 and GPWL2, and controls whether to pull down (i) the scan signal out to and maintained at the reference potential VGL according to the precharge signal pc (i) and the pull-down control signals GPWL1 and GPWL 2. The second pull-down unit 218 includes transistors M9-M13. The control terminal and the first terminal of the transistor M9 input a pull-down control signal GPWL 2. The control terminal of the transistor M10 inputs a pull-down control signal GPWL1, the first terminal of the transistor M10 is coupled to the reference voltage VGL, the second terminal of the transistor M10 is coupled to the second terminal of the transistor M9, and the second terminal of the transistor M9 and the second terminal of the transistor 10 are coupled to the node Q. The control terminal of the transistor M11 is coupled to the node X1, the first terminal of the transistor M11 is coupled to the reference voltage VGL, and the second terminal of the transistor M11 is coupled to the second terminal of the transistor M9. The control terminal of the transistor M12 is coupled to the second terminal of the transistor M11, the first terminal of the transistor M12 is coupled to the reference voltage VGL, and the second terminal of the transistor M12 is coupled to the node X1. The control terminal of the transistor M13 is coupled to the second terminal of the transistor M11, the first terminal of the transistor M13 is coupled to the reference voltage VGL, and the second terminal of the transistor M13 is coupled to the node X2. After the shift register 210(i) outputs the scan signal out (i) to activate the corresponding pixel row, i.e., the scan signal out (i) rises to the high level and stays at the low level for a period of time, the node X1 falls from the high level to the low level, and the second pull-down unit 218 starts to operate. When the pull-down control signal GPWL1 is low and the pull-down control signal GPWL2 is high, the node Q is at a high state, so that the transistors M12 and M13 are turned on, and the potentials of the nodes X1 and X2 are set to the reference potential VGL; when the pull-down control signal GPWL1 is high and the pull-down control signal GPWL2 is low, the node Q is low, such that the transistors M12 and M13 are turned off. In a frame time, when the shift register 210(i) outputs the scan signal out (i) to activate the corresponding pixel row, i.e., the scan signal out (i) rises to the high level and stays at the low level for a period of time, if the noise signal is coupled to the node X1 and/or the node X2, the turned-on transistors M12 and M13 pull down the nodes X1 and X2 to the low level, i.e., the scan signal out (i) is pulled down and stays at the low level, without the scan signal out (i) being interfered by the noise. In summary, since the pull-down control signals GPWL1 and GPWL2 are inverse, when the node X1 is lowered from high potential to low potential, one of the first pull-down unit 216 and the second pull-down unit 218 starts to operate, that is, the transistors M7 and M8 are turned on and the transistors M12 and M13 are turned off, or the transistors M12 and M13 are turned on and the transistors M7 and M8 are turned off, so that compared with a circuit having a shift register with only one pull-down unit, the turn-on time of some transistors in the first pull-down unit 216 and the second pull-down unit 218 can be greatly reduced to avoid the abnormal gate driving circuit caused by the characteristic shift due to the long-time turn-on of the transistors. For example, the pull-down control signals GPWL1 and GPWL2 are inverse to each other, and the signal periods of the pull-down control signals GPWL1 and GPWL2 are 2 seconds, wherein the high duration and the low duration in the signal periods are both 1 second, so that the turn-on time of the partial transistors in the first pull-down unit 216 and the second pull-down unit 218 can be reduced to half compared to a circuit having a shift register with only one pull-down unit.

It should be noted that the gate driving circuit 200 may be changed to sequentially output the scan signals OUT (1) -OUT (m) to the gate lines in the active area AA in opposite directions. When the gate driving circuit 200 is in forward scan, i.e. the forward input signal FW is high and the reverse input signal BW is low, STV1 is the start signal and STV2 is the end signal. Conversely, when the gate driving circuit 200 is in the reverse scan mode, i.e. the forward input signal FW is at the low potential and the reverse input signal BW is at the high potential, STV2 is the start signal, STV1 is the end signal, and the clock signals C1-C4 are changed to: the clock signal C3 lags the clock signal C4 by 1/4 cycle times, the clock signal C2 lags the clock signal C3 by 1/4 cycle times, and the clock signal C1 lags the clock signal C2 by 1/4 cycle times, so that during the same frame period, the M-th stage shift register 210(M) outputs the M-th scan signal OUT (M) to the M-th gate line, the (M-1) -th stage shift register 210(M-1) outputs the (M-1) -th scan signal OUT (M-1) to the (M-1) -th gate line after a time t, the (M-2) -th stage shift register 210(M-2) outputs the (M-2) -th scan signal OUT (M-2) to the (M-2) -th gate line after a time t, and so on until the 1 st stage shift register 210(1) outputs the 1 st stage scan signal OUT (1) to the 1 st gate line. In the embodiment of the present disclosure, a forward scan is taken as an example, that is, STV1 is a start signal and STV2 is an end signal. The implementation of the reverse scan embodiment can be directly derived from the above description and is not described in detail here.

The transistors M1-M13 in the shift register 210(i) may be amorphous silicon (amorphous silicon) thin film transistors, Low Temperature Polysilicon (LTPS) thin film transistors, Indium Gallium Zinc Oxide (IGZO) thin film transistors, or other suitable thin film transistors. If the amorphous silicon thin film transistor is used, the production cost of the gate driving circuit 200 can be further reduced.

Examples of the layout of the shift register circuits 210(1) to 210(M) and the related signal lines in the gate driver circuit 200 are as follows. Referring to fig. 4, fig. 4 is a layout diagram of a shift register and signal lines according to a first embodiment of the invention. For convenience of explanation, fig. 4 shows only the shift register 210(5) of fig. 3. However, the layout of the remaining shift registers 210(1) - (210 (4), 210(6) - (210 (M)) can be directly deduced by those skilled in the art from the layout shown in FIG. 4 and the contents of FIGS. 2 and 3. In fig. 4, signal lines such as the reference potential signal line VL, the start signal line SL1, the clock signal lines L1 to L4, and the pull-down control signal lines PL1, PL2 are located in a region near the boundary 112A of the active array substrate 112 and extend in the direction Y. In addition, the active area AA is located at the right side of the shift register 210(5), the gate lines of the gate lines in the active area AA may extend along the direction X (not shown), and the shift register 210(5) outputs the 5 th scan signal OUT (5) to the corresponding gate lines. The forward signal line FL, the backward signal line BL, the output end of the 5 th stage shift register 210(5), and the lines through which the scan signals OUT (3), OUT (4), OUT (6), and OUT (7) output by the 3 rd, 4 th, 6 th, and 7 th stage shift registers 210(3), 210(4), 210(6), and 210(7) are respectively transmitted are located in the area near the active area AA. As shown in fig. 4, the layout area of the 5 th stage shift register circuit 210(5) includes transistors M1 to M13 and a capacitor Cx located between some signal lines (including the ground line GL, the start signal line SL1, the clock signal lines L1 to L4, and the pull-down control signal lines PL1, PL2, etc.) and the active area AA. In the 5 th stage shift register circuit 210(5), the pull-down control signal lines PL1, PL2 are disposed between the layout regions of the transistors M1 to M13 and the capacitor Cx and the layout regions of the clock signal lines L1 to L4. Further, as shown in fig. 4, the layout regions of the transistors M4 to M8 of the first pull-down cell 216 and the layout regions of the transistors M9 to M13 of the second pull-down cell 218 are located between the layout regions of the pull-down control signal lines PL1, PL2 and the layout region of the pull-up cell 214 (including the transistor M3 and the capacitance Cx).

Further referring to fig. 5, which is a partial enlarged view of the layout diagram depicted in fig. 4. As shown in fig. 4 and 5, the pull-down control signal lines PL1, PL2 are located between the clock signal lines L1 to L4 and the transistors M4, M5, M9, M10, and the transistors M4, M5 in the first pull-down unit 216 and the transistors M9, M10 in the second pull-down unit 218 are located in the regions between the pull-down control signal lines PL1, PL2 and the transistors M7, M12.

Fig. 5 is a layout diagram of a device including a first conductive layer, a channel layer, a connection structure, and a second conductive layer, wherein the first conductive layer includes a gate of a transistor, and the second conductive layer includes a source and a drain of the transistor. In the layout of the transistor of the present embodiment, in the top view of fig. 5, the channel layer of the transistor is located above the gate, and the source and the drain (i.e., one and the other of the first end and the second end) are located above and opposite to the channel layer. The first conductive layer and the second conductive layer can be a single-layer structure or a multi-layer stacked structure. In the present embodiment, the first conductive layer and the second conductive layer can be a first metal layer and a second metal layer, respectively, but not limited thereto. Referring to fig. 5 and fig. 6A to 6D, fig. 6A is a layout diagram of the first conductive layer in fig. 5, fig. 6B is a layout diagram of the first conductive layer and the channel layer in fig. 5, fig. 6C is a layout diagram of the first conductive layer, the channel layer and the connection structure in fig. 5, and fig. 6D and fig. 5 are layout diagrams including the first conductive layer, the channel layer, the connection structure and the second conductive layer, which are different in element designation in fig. 5 and fig. 6D, so that the drawings are concise and readable. As shown in fig. 6A, the first conductor layer includes a clock signal line L1, pull-down control signal lines PL1, PL2, and gates M4_ C, M5_ C, M7_ C, M9_ C, M10_ C, M12_ C of transistors M4, M5, M7, M9, M10, M12. As shown in fig. 6B, in the transistor M4, the channel layer M4_ S is located above the gate M4_ C, and the first end M4_1 and the second end M4_2 are located above the channel layer M4_ S and are oppositely disposed. Similarly, in fig. 5, the channel layers M5_ S, M7_ S, M9_ S, M10_ S, M12_ S, the control terminals M5_ C, M7_ S, M9_ C, M10_ C, M12_ C, the first terminals M5_1, M7_1, M9_1, M10_1, M12_1, and the second terminals M5_2, M7_2, M9_2, and M10_2 of the transistors M5, M7, M9, M10, and M12 are arranged in the same manner as the transistor M4, and are not described herein again. As shown in fig. 6C and 6D, the connection structure CT is disposed between the first conductive layer and the second conductive layer for electrically connecting the first conductive layer and the second conductive layer. In this embodiment, at least one insulating layer is disposed between the first conductive layer and the second conductive layer, and the connection structure CT is a through hole of the at least one insulating layer, which exposes a portion of the first conductive layer, so that the second conductive layer can extend into the through hole to contact with the first conductive layer, so as to electrically connect the first conductive layer and the second conductive layer, but the connection structure CT is not limited thereto. In a variation, the connection structure CT may include a connection electrode, a first via and a second via, at least one insulating layer between the first conductor layer and the connection electrode, the at least one insulating layer having the first via to expose a portion of the first conductor layer, at least one insulating layer between the second conductor layer and the connection electrode, the at least one insulating layer having the second via to expose a portion of the second conductor layer, the connection electrode extending into the first via and the second via to contact the first conductor layer and the second conductor layer, respectively, such that the first conductor layer may be electrically connected to the second conductor layer via the connection electrode. For example, the connection electrode may be formed simultaneously with the pixel electrode or the common electrode, i.e., the connection electrode may belong to the same transparent conductive layer as the pixel electrode or the common electrode, so as to save the process steps. As shown in fig. 6D, in the transistor M4, the first terminal M4_1 and the second terminal M4_2 are located above the channel layer M4_ S and are oppositely disposed. Similarly, in fig. 6D, the first terminals M5_1, M7_1, M9_1, M10_1, M12_1 and the second terminals M5_2, M7_2, M9_2, M10_2, M12_2 of the transistors M5, M7, M9, M10, M12 are arranged in the same manner as the transistor M4, and thus, the description thereof is omitted. Referring to fig. 5 and fig. 6D, the first end M4_1 of the transistor M4 is electrically connected to the gate M4_ C of the transistor M4 through the connection line CL1 and the connection structure CT1, and the first end M4_1 of the transistor M4 is electrically connected to the pull-down control signal line PL1 through the connection lines CL1, CL2 and the connection structure CT 2. The gate M5_ C of the transistor M5 is electrically connected to the pull-down control signal line PL2 via a connection line CL 3. The first end M9_1 of the transistor M9 is electrically connected to the gate M9_ C of the transistor M9 through the connection line CL4 and the connection structure CT3, and the gate M9_ C of the transistor M9 is electrically connected to the pull-down control signal line PL2 through the connection line CL 5. The gate M10_ C of the transistor M10 is electrically connected to the pull-down control signal line PL1 through the connection structure CT4, the connection line CL6 and the connection structure CT 5. In the present embodiment, the connection lines CL3 and CL5 are formed of the first conductor layer, and the connection lines CL1, CL2, CL4 and CL6 are formed of the second conductor layer.

Referring to fig. 7, fig. 7 is a layout diagram of a shift register and signal lines according to a second embodiment of the invention. For convenience of explanation, fig. 7 shows only the shift register 210(5) of fig. 3. However, the layout of the remaining shift registers 210(1) - (210 (4), 210(6) - (210 (M)) can be directly deduced by those skilled in the art from the layout shown in FIG. 7 and the contents of FIGS. 2 and 3.

As shown in fig. 7, the difference between fig. 7 and fig. 4 is that the pull-down control signal lines PL1, PL2 of fig. 4 are located in the regions between the clock signal lines L1 to L4 and the transistors M4 to M13, that is, in the regions between the clock signal lines L1 to L4 and the first and second pull-

down cells

216, 218, while the layout regions of the pull-down control signal lines PL1, PL2 of fig. 7 partially overlap the layout region of the first pull-down cell 216 and the layout region of the second pull-down cell 218 in the top view direction (i.e., the direction perpendicular to the X-Y plane). In addition, the active area AA is located at the right side of the shift register 210(5), the gate lines of the gate lines in the active area AA can extend along the direction X (not shown), and the shift register 210(5) outputs the 5 th-stage scan signal OUT (5) to the corresponding gate lines.

Further referring to fig. 8A, a partial enlarged view of the layout diagram depicted in fig. 7 is shown. Fig. 8A is a layout diagram of a device including a first conductive layer, a channel layer, a connection structure, and a second conductive layer, wherein the first conductive layer includes a gate of a transistor, and the second conductive layer includes a source and a drain of the transistor. As shown in fig. 8A, the pull-down control signal lines PL1, PL2 are located between the clock signal lines L1 to L4 and the transistors M7, M12. The pull-down control signal line PL1 has a first side PLE1 and a second side PLE2 opposite to each other, wherein the first side PLE1 is closer to the boundary 112A of the active array substrate 112 than the second side PLE2, and the pull-down control signal line PL2 has a third side PLE3 and a fourth side PLE4 opposite to each other, wherein the fourth side PLE4 is closer to the active area AA than the third side PLE3, and the second side PLE2 and the third side PLE3 are opposite to each other. The transistors M4, M5 in the first pull-down cell 216 and the transistors M9, M10 in the second pull-down cell 218 are located in the region between the first side PLE1 and the fourth side PLE 4.

As shown in fig. 8A, the pull-down control signal line PL1 overlaps with the transistor M4 in the first pull-down unit 216 and the transistor M10 in the second pull-down unit 218, and the pull-down control signal line PL2 overlaps with the transistor M5 in the first pull-down unit 216 and the transistor M9 in the second pull-down unit 218. That is, a portion and another portion of the pull-down control signal line PL1 are respectively the control terminal (gate) M4_ C of the transistor M4 and the control terminal (gate) M10_ C of the transistor M10, and a portion and another portion of the pull-down control signal line PL2 are respectively the control terminal (gate) M5_ C of the transistor M5 and the control terminal (gate) M9_ C of the transistor M9. The arrangement of the gates, the channel layer, the first ends and the second ends of the transistors M4, M5, M9 and M10 in fig. 8A is the same as that in the first embodiment (fig. 5 to 6D), and thus the description thereof is omitted. The control terminal M4_ C of the transistor M4 is electrically connected to the first terminal M4_1 of the transistor M4 through the connection structure CT6, and the control terminal M9_ C of the transistor M9 is electrically connected to the first terminal M9_1 of the transistor M9 through the connection structure CT 7. The structures of the connection structures CT6 and CT7 are the same as the connection structures CT1 to CT5 in the first embodiment, that is, the connection structures CT6 and CT7 in this embodiment are through holes of at least one insulating layer between the first conductor layer and the second conductor layer, but not limited thereto. In a variant embodiment, the structure of the connection structures CT6, CT7 may be the same as the connection structure including the connection electrode, the first via and the second via in the variant embodiment of the first embodiment.

Referring to fig. 8B, it is a partially enlarged view of the pull-down control signal lines PL1, PL2 shown in fig. 8A. As shown in fig. 8B, the pull-down control signal line PL1 has an extension portion PL1_ L and protrusions PL1_ P1, PL1_ P2, PL1_ P3, while the pull-down control signal line PL2 has an extension portion PL2_ L and protrusions PL2_ P1, PL2_ P2, PL2_ P3. The extensions PL1_ L are directly connected by the projections PL1_ P1, PL1_ P2, PL1_ P3, and the extensions PL2_ L are directly connected by the projections PL2_ P1, PL2_ P2, PL2_ P3. The length of the projections PL1_ P1, PL1_ P3 in the direction X (perpendicular to the direction Y) is W1, the length of the projections PL1_ P2 in the direction X is W2, the length of the projections PL2_ P1, PL2_ P2 in the direction X is W3, and the length of the projections PL2_ P3 in the direction X is W4. The length W1 is greater than the length W2, and the length W3 is greater than the length W4, but not limited thereto. In some embodiments, length W1 may be the same as length W3, and/or length W2 may be the same as length W4, but is not so limited. The protruding portions PL1_ P1 to PL1_ P3 and PL2_ P1 to PL2_ P3 are staggered in the direction Y. In addition, the projections of the protrusions PL1_ P1 and PL1_ P3 in the direction X may partially overlap with the projections of the protrusions PL2_ P1 and PL2_ P2 in the direction X, so as to further reduce the distance between the first side PLE1 and the fourth side PLE4, and further reduce the layout area of the gate driving circuit 200, thereby achieving the narrow frame requirement of the display panel. For example, the projections of the protrusions PL1_ P1 and PL1_ P3 in the direction X are located between the coordinates a and b in the direction X, and the projections of the protrusions PL2_ P1 and PL2_ P2 in the direction X are located between the coordinates c and d in the direction X, wherein the interval from the coordinate a to the coordinate b in the direction X partially overlaps with the interval from the coordinate c to the coordinate d.

Fig. 8C is a partially enlarged view of the pull-down control signal lines PL1 and PL2, the channel layer M4_ S, M5_ S, M9_ S, M10_ S, and the connection structures CT6 and CT7 shown in fig. 8A. As shown in fig. 8C, the lengths of the extension portions PL1_ P1, PL2_ P1, PL2_ P2 and PL1_ P3 in the direction Y are respectively greater than the lengths of the channel layers M4_ S, M5_ S, M9_ S, M10_ S in the direction Y, the extension portions PL1_ L are directly connected to the extension portions PL1_ P1 and PL1_ P3, and the extension portions PL2_ P1 and PL2_ P2 are directly connected to the extension portions PL2_ L, so that the channel layer M4_ S is simultaneously disposed on the extension portions PL1_ L and PL1_ P1, the channel layer M1 _ S is simultaneously disposed on the extension portions PL1_ L and PL1_ P1, and the channel layer M1 _ S is simultaneously disposed on the extension portions PL1_ P1 and PL1_ P1. Furthermore, the lengths of the protruding portions PL1_ P2, PL2_ P3 in the direction Y are respectively greater than the lengths of the connecting structures CT6, CT7 in the direction Y, the protruding portion PL1_ P2 directly connects the extending portion PL1_ L, and the PL2_ P3 directly connects the extending portion PL2_ L, so that the connecting structure CT6 is provided on both the extending portion PL1_ L and the protruding portion PL1_ P2, and the connecting structure CT7 is provided on both the extending portion PL2_ L and the protruding portion PL2_ P3. In other embodiments, the channel layer M4_ S may be completely disposed on the protrusion PL1_ P1, the channel layer M5_ S may be completely disposed on the protrusion PL2_ P1, the channel layer M9_ S may be completely disposed on the protrusion PL2_ P2, the channel layer M10_ S may be completely disposed on the protrusion PL1_ P3, the connection structure CT6 may be completely disposed on the protrusion PL1_ P2, and/or the connection structure CT7 may be completely disposed on the protrusion PL2_ P3.

In other embodiments, the layout shown in fig. 8A may be changed according to the design requirements, in which at most only one of the transistors M4 and M10 overlaps the pull-down control signal line PL1, and/or at most only one of the transistors M5 and M9 overlaps the pull-down control signal line PL 2. In some embodiments, the pull-down control signal line PL1 does not have the protrusions PL1_ P1, PL1_ P2, PL1_ P3, the pull-down control signal line PL2 does not have the protrusions PL2_ P1, PL2_ P2, PL2_ P3, and the transistors M4, M5, M9, M10 are disposed entirely in the space between the second side PLE2 and the third side PLE 3.

In the present embodiment, the control terminals of the start signal line SL1, the end signal line SL2, the clock signal lines L1 to L4, the pull-down control signal lines PL1 and PL2, and the transistors M1 to M13 belong to a first conductor layer (e.g., a first metal layer) in the display panel 110, and the control terminals of the reference potential signal line VL, the transistors M1 to M13 and the second terminal belong to a second conductor layer (e.g., a second metal layer) in the display panel 110. The start signal line SL1, the end signal line SL2, the clock signal lines L1 to L4, the pull-down control signal lines PL1, PL2, and the control terminals of the transistors M1 to M13 may be formed through the same process, and the reference potential signal line VL, the first terminals and the second terminals of the transistors M1 to M13 may be formed through the same process.

It should be noted that the equivalent circuit diagram of the ith stage shift register 210(i) in the gate driving circuit 200 of the present invention is not limited to fig. 3. In other words, in other embodiments, the circuits of the precharge unit, the pull-up unit, the first pull-down unit, and the second pull-down unit in the ith stage shift register 210(i) may be at least partially different from the circuits of the precharge unit 212, the pull-up unit 214, the first pull-down unit 216, and the second pull-down unit 218 of fig. 3. In addition, in some embodiments, the number of pull-down units in the ith stage of shift register 210(i) may be one or more than two. In various embodiments of the shift register circuit, if two signal lines in the gate driving circuit 200 respectively provide a first signal to the gate of at least one transistor in the ith stage of shift register 210(i) and provide a second signal to the gate of at least one other transistor in the ith stage of shift register 210(i), a circuit layout similar to that shown in fig. 7 to 8C may be adopted to reduce the layout area of the gate driving circuit 200, thereby realizing the narrow frame requirement of the display panel.

In summary, the gate driving circuit 200 includes a plurality of signal lines and 1 st to M th shift registers 210(1) to 210(M), the signal lines include adjacent first and second signal lines for providing first and second signals to the 1 st to M th shift registers 210(1) to 210(M), respectively, each of the shift registers 210(i) includes a first transistor and a second transistor, and control terminals (gates) of the first and second transistors respectively receive the first and second signals, so that in the layout of the gate driving circuit 200, a portion of the first signal line can be used as a control terminal (gate) of the first transistor, and a portion of the second signal line can be used as a control terminal (gate) of the second transistor, that is, the first transistor and the first signal line partially overlap, and the second transistor is partially overlapped with the second signal line to reduce the layout area of the gate driving circuit 200. For example, the first signal line and the second signal line may be pull-down control signal lines PL1, PL2, respectively, the first transistor may be transistor M4 or M10, and the second transistor may be transistor M5 or M9, but not limited thereto. In addition, in some embodiments, the gate line in the active region extends along a first direction, the first signal line and the second signal line respectively have a first protrusion and a second protrusion, the channel layer of the first transistor is at least partially disposed on the first protrusion, and the channel layer of the second transistor is at least partially disposed on the second protrusion. In order to further reduce the layout area of the gate driving circuit 200, in the layout of the shift register 210(i), the first transistor, the second transistor, the first protrusion portion and the second protrusion portion are located between the first side of the first signal line and the fourth side of the second signal line, and the projection of the first protrusion portion in the first direction may overlap with the projection of the second protrusion portion in the first direction, so as to further reduce the layout area of the gate driving circuit 200. In still other embodiments, each of the stage shift registers 210(i) further includes a third transistor and a fourth transistor, and control terminals (gates) of the third transistor and the fourth transistor respectively receive the first signal and the second signal, so in the layout of the gate driving circuit 200, another portion of the first signal line can simultaneously serve as a control terminal (gate) of the third transistor, and another portion of the second signal line can simultaneously serve as a control terminal (gate) of the fourth transistor, that is, the third transistor partially overlaps the first signal line, and the fourth transistor partially overlaps the second signal line, so as to reduce the layout area of the gate driving circuit 200. The first signal line and the second signal line respectively have a third protrusion and a fourth protrusion, the channel layer of the third transistor is at least partially disposed on the third protrusion, the channel layer of the fourth transistor is at least partially disposed on the fourth protrusion, the third transistor, the fourth transistor, the third protrusion and the fourth protrusion are located between the first side of the first signal line and the fourth side of the second signal line, and the projection of at least one of the first protrusion and the third protrusion in the first direction can overlap with the projection of at least one of the second protrusion and the fourth protrusion in the first direction, so as to further reduce the layout area of the gate driving circuit 200. For example, the first transistor and the third transistor may be the transistors M4 and M10, respectively, and the second transistor and the fourth transistor may be the transistors M5 and M9, respectively, but not limited thereto.

Referring to fig. 5 and 8A simultaneously, since a portion and another portion of the pull-down control signal line PL1 in the second embodiment (fig. 8A) are respectively used as the control terminal M4_ C of the transistor M4 and the control terminal M10_ C of the transistor M10, and a portion and another portion of the pull-down control signal line PL2 are respectively used as the control terminal M5_ C of the transistor M5 and the control terminal M9_ C of the transistor M9, while the pull-down control signal lines PL 9, PL 9 and the control terminals M9_ 9_ 9_ C of the transistors M9, M9 in the first embodiment (fig. 5) are separately arranged without simultaneously connecting a portion of the pull-down control signal lines PL 9, PL 9 with the control terminals M9_ 9_ 9_ C of the transistors M9, M9 and M9, and thus the layout of the second embodiment (fig. 5 a) is less frequently connected, that is, the layout area of the gate driving circuit of the second embodiment is smaller than that of the first embodiment. Through the configuration manner described in the second embodiment, the layout area of the shift register in the peripheral area of the display panel can be further reduced, thereby being beneficial to realizing the narrow frame requirement of the display panel. Due to the reduced layout area of the shift register, the distance between the signal lines (including the reference potential signal line, the start signal line, the end signal line, the clock signal line, the pull-down control signal line, etc.) and the boundary of the active array substrate (i.e., the boundary of the display panel) can be increased, thereby further enhancing the electrostatic discharge effect. In addition, through the configuration mode, the pull-down control signal line does not need to cross another pull-down control signal line in a mode of configuring an additional connecting line and a connecting structure to be electrically connected with different metal layers so as to transmit a pull-down control signal to a transistor in the shift register, and therefore production cost can be saved.

The configuration described in the above embodiments can also be applied to other display devices or display panels, such as an odd-shaped display panel, or be applied to other display devices or display panels after being changed, so as to achieve the effects of reducing the layout area, extending the distance between the signal lines and the boundary of the active array substrate, and saving the production cost. Referring to fig. 9, fig. 9 is a schematic view of a display panel 300 according to an embodiment of the invention. The display panel 300 may be a liquid crystal display panel such as a twisted nematic type, a horizontal switching type, a fringe field switching type, or a vertical alignment type, but is not limited thereto. The display panel 300 includes an active array substrate 302 and has an active area 310 and a peripheral area 320, wherein the active area 310 has a plurality of pixel units disposed on the active array substrate 302, and the peripheral area 320 includes a gate driver 330 for generating a scan signal and transmitting the scan signal to gate lines (not shown in fig. 9) in the active area 310, such that the pixel units in the active area 310 are driven by the scan signal to display an image at a specific time.

In addition, as shown in fig. 9, the display panel 300 is a specially shaped display panel, i.e., the active array substrate 302 is specially shaped. In fig. 9, the upper left corner, the lower left corner, the upper right corner and the lower right corner of the display panel 300 are all arc-shaped instead of right-angled. In addition, the active region 310 is a shaped active region, and the shape of the edge 310E of the active region 310 is similar to the shape of the edge 300E of the display panel 300. If the size of each pixel unit in the active region 310 is the same, the number of pixel units in each pixel row at the top and bottom of the active region 310 is smaller than the number of pixel units in other pixel rows of the active region 310.

In the embodiment of the present invention, the display panel 300 is a system-integrated glass panel. That is, the gate driver 330 is fabricated on the active array substrate 302 of the display panel 300. In this way, the electronic elements in the gate driver 330 and the electronic elements in the active region 310 (such as, but not limited to, thin film transistors, pixel electrodes, etc.) can be fabricated by the same process.

The display panel of the present invention may have other aspects than the display panel 300 shown in fig. 9. For example, referring to fig. 10, fig. 10 is a schematic view of a display panel 300' according to an embodiment of the invention. As shown in fig. 10, the display panel 300 ' is a special-shaped display panel, that is, the active array substrate 302 ' is special-shaped, wherein the shapes of the upper left corner, the lower left corner, the upper right corner and the lower right corner of the display panel 300 ' are all arc shapes rather than right angles. In addition, the active region 310 ' is a shaped active region, and the shape of the edge 310E ' of the active region 310 ' is similar to the shape of the edge 300E ' of the display panel 300 '. Compared to the display panel 300 of fig. 9, the display panel 300' of fig. 10 has a recess (notch) in the top region B. The gate driver 330 of fig. 10 is the same as the gate driver 330 of fig. 9, and is not described herein again.

Fig. 11 shows the pixel unit arrangement and the element configuration in the upper left corner area a of the display panel 300. As shown in fig. 11, in the upper left corner region a, the boundary 310E of the active region 310 is arc-shaped. In the active region 310, there are pixel units P each having a thin film transistor TFT and a pixel electrode PX. Each TFT is coupled to a corresponding data line and a corresponding gate line, and controls whether to input a data signal provided by the corresponding data line to the pixel electrode PX according to a scan signal provided by the corresponding gate line. The thin film transistor TFT may be an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, an indium gallium zinc oxide thin film transistor, or other suitable thin film transistors. The pixel electrode PX is used to generate an electric field with a common electrode (not shown), so that the liquid crystal molecules in the pixel unit P are twisted under the action of the electric field, and the pixel unit P displays a corresponding gray scale. The area a is a top area of the active region 310 having an arc-shaped edge, so that the number of the pixel units P coupled to the gate lines gradually increases from top to bottom. As shown in fig. 11, in the top region of the active region 310 having the arc-shaped edge, the number of pixel units P coupled to the gate lines SL (m) is less than the number of pixel units P coupled to the gate lines SL (m +1), and the number of pixel units P coupled to the gate lines SL (m +1) is less than the number of pixel units P coupled to the gate lines SL (m +2) (not shown). In contrast, in the bottom region of the active region 310 having the arc-shaped edge, the number of the pixel units P coupled to the gate line is gradually decreased from top to bottom.

Referring to fig. 12, fig. 12 shows the arrangement of the shift registers and the elements in the upper left corner area a of the display panel 300. As shown in fig. 10 and 12, the shift registers 210(m), 210(m +1) are disposed in the peripheral region 320 and between the active region 310 and the signal lines such as the reference potential signal line VL, the start signal line SL1, and the clock signal lines L1 to L4, and the output ends thereof are respectively coupled to the gate lines SL (m), SL (m +1) to respectively output the scan signals OUT (m), OUT (m +1) to the gate lines SL (m), SL (m + 1). In the embodiment of fig. 12, the layout of the transistors and the signal lines in the shift register is exemplified by the layout of the shift register and the signal lines in the second embodiment (fig. 7) of the present invention, that is, the pull-down control signal lines PL1, PL2 penetrate the layout regions of the shift registers 210(m), 210(m +1) and overlap with some of the transistors in the shift registers 210(m), 210(m + 1). Since the edge 310E of the active region 310 in the upper left corner region a of the display panel 300 and the edge 300E of the display panel 300 are arc-shaped, the shift registers 210(m), 210(m +1) are arranged along the edge 310E of the active region 310 in the peripheral region 320, i.e., the projections of the shift registers 210(m), 210(m +1) in the direction X are partially overlapped or completely non-overlapped, and the extending directions of the signal lines such as the reference potential signal line VL, the start signal line SL1, the clock signal lines L1-L4, the pull-down control signal lines PL1, PL2, etc. are not completely parallel to the vertical direction (direction Y), i.e., the sections of the signal lines corresponding to the shift register 210(m) (or 210(m +1)) in the direction Y are broken lines. Herein, the section of the signal line corresponding to the shift register 210(m) (or 210(m +1)) in the direction Y refers to a section of the signal line between the coordinates a and b in the direction Y when the shift register 210(m) (or 210(m +1)) is located between the coordinates a and b in the direction Y. Taking the clock signal line L1 as an example, the segment of the clock signal line L1 corresponding to the shift register 210(m) in the direction Y and the segment corresponding to the shift register 210(m +1) both include at least one line segment not parallel to the direction Y (e.g., a line segment parallel to the direction X or a diagonal line segment not parallel to the directions X and Y), so that the clock signal line L1 is disposed along the edges of the shift registers 210(m) and 210(m + 1). For example, as shown in fig. 12, a section of the clock signal line L1 corresponding to the shift register 210(m) in the direction Y includes first to third line segments LN1 to LN3, wherein the first line segment LN1 and the third line segment LN3 are parallel to the direction Y, and two ends of the second line segment LN2 are respectively connected to the first line segment LN1 and the third line segment LN3 and are not parallel to the direction X and the direction Y, but not limited thereto.

It should be noted that the lengths of the first to third line segments LN 1-LN 3, the included angle between the first line segment LN1 and the second line segment LN2, and the included angle between the second line segment LN2 and the third line segment LN3 may be correspondingly adjusted according to the tangential slope of the edge 300E of the display panel 300 and/or the configuration position of the shift register. In addition, the clock signal line L1 may also have first to third line segments LN1 to LN3 in the direction Y corresponding to the sectors of other shift registers, and the lengths and angles of the first to third line segments LN1 to LN3 of each sector may be all the same, partially the same, or all the different. The configuration of other signal lines (e.g., the clock signal lines L2 to L4, the start signal line SL1, and/or the reference potential signal line VL, etc.) may also be similar to that of the clock signal line L1 described above.

As shown in fig. 12, the region between the shift registers 210(m) to 210(m +1) and the active region 310 includes a forward input signal line FL for supplying a forward input signal FW, a reverse input signal line BL for supplying a reverse input signal BW, and traces for outputting scan signals OUT (m-2) to OUT (m +3), respectively. The layout of the forward input signal line FL, the backward input signal line BL, and the wirings for outputting the scan signals OUT (m-2) to OUT (m +3) may be similar to the layout of the wirings of the clock signal lines L1 to L4, the reference potential signal line VL, and the like.

In addition, a signal lead VWL is provided between adjacent shift registers, and is coupled to the adjacent shift registers and the reference potential signal line VL for providing the reference potential VGL to the shift registers. As shown in fig. 12, the signal leads VWL are respectively arranged on the upper side of the shift register 210(m), between the shift registers 210(m) and 210(m +1), and on the lower side of the shift register 210(m), and are coupled to the shift registers 210(m), 210(m +1), and the reference potential signal line VL. Each signal lead VWL and the reference potential signal line VL belong to the same metal layer.

Fig. 13 is an example of a partial layout diagram of the shift register 210(m), the clock signal line L1, and the pull-down control signal lines PL1, PL2 in the upper left corner region a of the display panel 300. Referring to fig. 12 and 13, the pull-down control signal line PL1 has a first side PLE1 and a second side PLE2 opposite to each other, wherein the first side PLE1 is closer to the edge 300E of the display panel 300 than the second side PLE2, and the pull-down control signal line PL2 has a third side PLE3 and a fourth side PLE4 opposite to each other, wherein the fourth side PLE4 is closer to the edge 310E of the active area 310 than the third side PLE 3; the transistors M4, M5, M9, M10 are disposed in a region between the first side PLE1 of the pull-down control signal line PL1 and the fourth side PLE4 of the pull-down control signal line PL2, wherein the pull-down control signal line PL1 overlaps the transistors M4, M10, and the pull-down control signal line PL2 overlaps the transistors M5, M9. Compared to the partial layout shown in fig. 8A, in the partial layout shown in fig. 13, a section of the pull-down control signal line PL1 corresponding to the shift register 210(M) in the direction Y includes a first line segment PL1S1, a second line segment PL1S2 and a third line segment PL1S3 having different extending directions from each other, wherein the length extending direction of the first line segment PL1S1 is parallel to the vertical direction (direction Y), the length extending direction of the second line segment PL1S2 is parallel to the horizontal direction (direction X), the length extending direction of the third line segment PL1S3 has a non-zero included angle with both the vertical direction (direction Y) and the horizontal direction (direction X), both ends of the second line segment PL1S2 are respectively coupled to the first line segment PL1S1 and the third line segment PL1S3, the first line segment PL1S1 overlaps with the transistors 4 and M10, that is the first line segment PL1S1 has two channel overlapping portions of the transistors 4 and the transistors 10, the section of the pull-down control signal line PL2 corresponding to the shift register 210(M) in the direction Y includes a first line segment PL2S1 and a second line segment PL2S2 having different extending directions from each other, wherein the length extending direction of the first line segment PL2S1 is parallel to the vertical direction (direction Y), the length extending direction of the second line segment PL2S2 is parallel to the horizontal direction (direction X), and the first line segment PL2S1 overlaps the transistors M5 and M9, that is, the first line segment PL2S1 has two protruding portions overlapping the channel layer portions of the transistors M5 and M9, respectively. The other configurations of the pull-down control signal lines PL1 and PL2 and the transistors M4, M5, M9 and M10 are similar to those described in fig. 7 to 8C, and therefore are not repeated herein. It is noted that the section of the pull-down control signal line PL1 corresponding to the shift register 210(m) in the direction Y includes the first to third line segments PL1S1, PL1S2, PL1S3 having the extending directions different from each other, and the section of the pull-down control signal line PL2 corresponding to the shift register 210(m) in the direction Y includes the first line segment PL2S1 and the second line segment PL2S2 having the extending directions different from each other are merely illustrative and not limited thereto. The section of the pull-down control signal lines PL1, PL2 corresponding to the shift register 210(m) in the direction Y may include at least one line segment whose length extension direction is parallel to the vertical direction (direction Y) and at least one line segment whose length extension direction is not parallel to the vertical direction (direction Y).

Fig. 14 is another example of a partial layout diagram of the shift register 210(m) in the upper left corner area a of the display panel 300. The partial layout diagram shown in fig. 14 differs from fig. 13 in that, in the partial layout diagram shown in fig. 13, a line segment in the length extending direction parallel direction Y in the pull-down control signal line PL1 has two projections that partially overlap with the channel layers of the transistors M4, M10, whereas, in the partial layout diagram shown in fig. 14, a line segment in the length extending direction parallel direction Y in the pull-down control signal line PL1 has one projection that partially overlaps with the channel layer of the transistor M4, and another line segment in the length extending direction non-parallel direction Y in the pull-down control signal line PL1 has another projection that partially overlaps with the channel layer of the transistor M10. As shown in fig. 14, the section of the pull-down control signal line PL1 corresponding to the shift register 210(m) in the direction Y further includes a fourth line segment PL1S4, the length extension direction of the fourth line segment PL1S4 has a non-zero angle with both the vertical direction (direction Y) and the horizontal direction (direction X), both ends of the fourth line segment PL1S4 are coupled to the first line segment PL1S1 and the second line segment PL1S2, respectively, and both ends of the second line segment PL1S2 are coupled to the fourth line segment PL1S4 and the third line segment PL1S3, respectively. Further, the first line segment PL1S1 has one projection partially overlapping the channel layer of the transistor M4, and the fourth line segment PL1S4 has another projection partially overlapping the channel layer of the transistor M10. The arrangement of the transistors M5 and M9 shown in fig. 14 is the same as that shown in fig. 13, and therefore, the description thereof is omitted here. Similarly, the section of the pull-down control signal line PL1 corresponding to the shift register 210(m) in the direction Y includes the first to fourth line sections PL1S1, PL1S2, PL1S3, PL1S4 for illustration only, and is not limited thereto. The section of the pull-down control signal line PL1 corresponding to the shift register 210(M) in the direction Y may include at least one line segment having a length extending direction parallel to the vertical direction (direction Y) and at least one line segment having a length extending direction not parallel to the vertical direction (direction Y), and at least one line segment of the pull-down control signal line PL1 having a length extending direction not parallel to the vertical direction Y has at least one protrusion partially overlapping with a channel layer of at least one of the transistors M4, M10.

The element configuration in the above embodiments can also be applied to a display device in which the gate drivers are respectively disposed on two opposite sides (e.g., left and right sides) of the display panel. Referring to fig. 15, fig. 15 is a schematic diagram of a display device 400 according to an embodiment of the invention. The display device 400 includes a display panel 410, a source driver 420, and

gate drivers

430A, 430B. The display panel 410 includes an active array substrate 412 including a plurality of data lines DL, a plurality of gate lines SL, and a plurality of pixels PX. The display panel 410 may be a liquid crystal display panel such as a twisted nematic type, a horizontal switching type, a fringe field switching type, or a vertical alignment type, but is not limited thereto. The source driver 420 is electrically connected to the display panel 410, and is configured to transmit a source driving signal to the display panel 410. The display panel 410 has an active area AA and a peripheral area PA, and the

gate drivers

430A and 430B are disposed in the peripheral area PA for generating scan signals and respectively transmitting the scan signals to the gate lines in the active area AA, so that the pixels PX in the active area AA are driven by the source driving signals and the scan signals to display images at specific times. As shown in fig. 15, the

gate drivers

430A and 430B are disposed in the peripheral region PA and located at two sides of the display panel 410 respectively.

In the embodiment of the present invention, the display panel 410 is a system-integrated glass panel. That is, the

gate drivers

430A and 430B are fabricated in the display panel 410. Thus, the electronic devices in the

gate drivers

430A and 430B and the electronic devices in the active area AA (such as, but not limited to, thin film transistors, pixel electrodes, etc.) can be fabricated by the same process.

In addition, although the shape of the active area AA of the display panel 410 in fig. 15 is a rectangle, the invention is not limited thereto. In an alternative embodiment, the display panel 410 may be a special-shaped display panel, that is, the active area AA is non-rectangular, and the

gate drivers

430A and 430B are respectively located in the peripheral area PA outside two opposite sides of the active area AA.

Fig. 16 is a schematic diagram of

gate driving circuits

500A and 500B according to an embodiment of the invention. The

gate driving circuits

500A and 500B may respectively correspond to two gate drivers respectively located at two sides of the display panel in the dual-side driving display panel. For example, the

gate drivers

430A, 430B of fig. 15 may include

gate driving circuits

500A, 500B, respectively. As shown in fig. 16, the gate driving circuit 500A includes shift registers 510A (1), 510A (2), …, 510A (m), and the gate driving circuit 500B includes shift registers 510B (1), 510B (2), …, 510B (m). The following description will take as an example that the

gate driver circuits

500A and 500B correspond to the

gate drivers

430A and 430B of fig. 15, respectively. The shift registers 510A (1), 510A (2), …, 510A (m) are used for sequentially outputting the scan signals OUTA (1) -OUTA (m) to the scan lines in the active area AA. Similarly, the shift registers 510B (1), 510B (2), …, 510B (m) are used for sequentially outputting the scan signals OUTB (1) -OUTB (m) to the scan lines in the active area AA. In the

gate driving circuits

500A and 500B, the same stage of shift registers output the scan signals to the same gate line, i.e., the shift registers 510A (1) and 510B (1) are coupled to the first gate line, and the shift registers 510A (2) and 510B (2) are coupled to the second gate line …, etc., to increase the driving capability of the display panel 410. Equivalent circuits of the shift registers 510A (1) to 510A (m), 510B (1) to 510B (m) are the same as those of the shift register 210(i) of fig. 3. Further, the gate drive circuit 500A includes clock signal lines LA1 to LA4, a start signal line SLA1, an end signal line SLA2, pull-down control signal lines PLA1, PLA2, and a reference potential signal line VLA, and the gate drive circuit 500B includes clock signal lines LB1 to LB4, a start signal line SLB1, an end signal line SLB2, pull-down control signal lines PLB1, PLB2, and a reference potential signal line VLB. Signals provided by the clock signal lines LA1 to LA4, the start signal line SLA1, the end signal line SLA2, the pull-down control signal lines PLA1, PLA2, and the reference potential signal line VLA may correspond to signals provided by the clock signal lines L1 to L4, the start signal line SL1, the end signal line SL2, the pull-down control signal lines PL1, PL2, and the reference potential signal line VL of fig. 2, respectively. Similarly, signals supplied from the clock signal lines LB1 to LB4, the start signal line SLB1, the end signal line SLB2, the pull-down control signal lines PLB1, PLB2, and the reference potential signal line VLB may correspond to signals supplied from the clock signal lines L1 to L4, the start signal line SL1, the end signal line SL2, the pull-down control signal lines PL1, PL2, and the reference potential signal line VL of fig. 2, respectively.

The arrangement of the signal lines such as the start signal line SLA1, the clock signal lines LA1 to LA4, the pull-down control signal lines PLA1, PLA2 and the reference potential signal line VLA in the gate driving circuit 500A may be the same as the arrangement of the signal lines such as the start signal line SL1, the clock signal lines L1 to L4, the pull-down control signal lines PL1, PL2 and the reference potential signal line VL shown in fig. 7, and the arrangement of the pull-down control signal lines PLA1, PLA2 and the elements coupled thereto (and the transistors M4, M5, M9 and M10) may be the same as the arrangement of the elements shown in fig. 8A to 8C. Further, since the

gate driving circuits

500A and 500B are disposed on the left and right sides of the display panel 410, the arrangement and layout of the signal lines such as the start signal line SLB1, the clock signal lines LB1 to LB4, the pull-down control signal lines PLB1, PLB2, and the reference potential signal line VLB can be mirror-symmetrical to the arrangement of the signal lines such as the start signal line SLA1, the clock signal lines LA1 to LA4, the pull-down control signal lines PLA1, PLA2, and the reference potential signal line VLA in the direction Y. In the modified embodiment of the non-uniform panel, the layout of the routing lines of the start signal line SLA1, the clock signal lines LA1 to LA4, the pull-down control signal lines PLA1, PLA2, and the reference potential signal line VLA may be the same as the layout of the signal lines of the start signal line SL1, the clock signal lines L1 to L4, the pull-down control signal lines PL1, PL2, and the reference potential signal line VL shown in fig. 12, and the layout of the pull-down control signal lines PLA1, PLA2 and the coupled transistors (and the transistors M4, M5, M9, M10) may be the same as the layout of fig. 13 or fig. 14.

Fig. 17 is a diagram of

gate driving circuits

600A and 600B according to an embodiment of the invention. The

gate driving circuits

600A and 600B may respectively correspond to two gate drivers respectively located at two sides of the display panel in the dual-side driving display panel. For example, the gate driving circuit 600A may correspond to the gate driver 430A of fig. 15 and includes shift registers 610(1), 610(3), …, 610(M-1), and the gate driving circuit 600B may correspond to the gate driver 430B of fig. 15 and includes shift registers 610(2), 610(4), …, 610 (M). The combination of the gate driving circuit 600A and the gate driving circuit 600B may be equivalent to the gate driver 200 of fig. 2, i.e., the shift registers 610(1), 610(3), …, and 610(M-1) respectively correspond to the odd-numbered shift registers 210(1), 210(3), …, and 210(M-1) of the gate driver 200, and the shift registers 610(2), 610(4), …, and 610(M) respectively correspond to the even-numbered shift registers 210(2), 210(4), …, and 210(M) of the gate driver 200.

The shift registers 610(1) to 610(M) are used for sequentially outputting the scan signals OUT (1) to OUT (M) to the scan lines in the active area AA. Equivalent circuits of the shift registers 610(1) to 610(M) are the same as those of the shift register 210(i) shown in fig. 3. Further, the gate drive circuit 600A includes a reference potential signal line VLA, a start signal line SLA1, an end signal line SLA2, pull-down control signal lines PLA1, PLA2, and clock signal lines L1, L3, while the gate drive circuit 600B includes a reference potential signal line VLB, a start signal line SLB1, an end signal line SLB2, pull-down control signal lines PLB1, PLB2, and clock signal lines L2, L4. Signals supplied from the clock signal lines L1 to L4 correspond to signals supplied from the clock signal lines L1 to L4 in fig. 2, signals supplied from the start signal lines SLA1 and SLB1 correspond to signals supplied from the start signal line SL1 in fig. 2, signals supplied from the end signal lines SLA2 and SLB2 correspond to signals supplied from the end signal line SL2 in fig. 2, pull-down control signal lines PLA1 and PLB1 correspond to signals supplied from the pull-down control signal line PL1 in fig. 2, pull-down control signal lines PLA2 and PLB2 correspond to signals supplied from the pull-down control signal line PL2 in fig. 2, and signals supplied from the reference potential signal lines VLA and VLB correspond to signals supplied from the reference potential signal line VL in fig. 2, respectively.

The signal lines of the reference potential signal line VLA, the start signal line SLA1, the clock signal lines LA1, LA3, the pull-down control signal lines PLA1, PLA2, etc. may be arranged in a similar manner to the signal lines of the reference potential signal line VL, the start signal line SL1, the clock signal lines L1, L3, the pull-down control signal lines PL1, PL2, etc. shown in fig. 7, and the layout of the pull-down control signal lines PLA1, PLA2, the transistors coupled thereto (and the transistors M4, M5, M9, M10), etc. may be arranged in a similar manner to the layout manner of the elements of fig. 8A to 8C. The arrangement and layout of the signal lines such as the reference potential signal line VLB, the start signal line SLB1, the clock signal lines LA2, LA4, and the pull-down control signal lines PLB1, PLB2 may be reversed to the left or right, similar to the arrangement of the signal lines such as the reference potential signal line VL, the start signal line SL1, the clock signal lines L2, L4, and the pull-down control signal lines PL1, PL2 shown in fig. 7. In the modified embodiment of the profiled panel, the routing manners of the start signal line SLA1, the clock signal lines LA1, LA3, the pull-down control signal lines PLA1, PLA2, and the reference potential signal line VLA may be the same as the routing manners of the start signal line SL1, the clock signal lines L1, L3, the pull-down control signal lines PL1, PL2, and the reference potential signal line VL shown in fig. 12, and the layout manners of the pull-down control signal lines PLA1, PLA2 and the transistors coupled thereto (and the transistors M4, M5, M9, M10) may be the same as the layout manners of fig. 13 or fig. 14.

In summary, the gate driving circuit and the display panel of the invention can reduce the layout area, extend the distance between the signal line and the boundary of the active array substrate, and save the production cost.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A gate driving circuit, comprising:

a plurality of shift registers for providing a plurality of scanning signals to a plurality of gate lines of a display panel, each shift register comprising a first transistor and a second transistor, wherein a gate of the first transistor and a gate of the second transistor respectively receive a first signal and a second signal; and

and a first signal line and a second signal line which respectively supply the first signal to a gate of the first transistor and the second signal to a gate of the second transistor, wherein the first transistor partially overlaps with the first signal line, and the second transistor partially overlaps with the second signal line.

2. The gate driver circuit according to claim 1, wherein a part of the first signal line simultaneously functions as a gate of the first transistor, and a part of the second signal line simultaneously functions as a gate of the second transistor.

3. The gate driver circuit according to claim 1, wherein the first signal line has a first extension portion and a first protrusion portion, the second signal line has a second extension portion and a second protrusion portion, the channel layer of the first transistor is at least partially disposed on the first protrusion portion, and the channel layer of the second transistor is at least partially disposed on the second protrusion portion.

4. The gate driving circuit according to claim 3, wherein a portion and another portion of the channel layer of the first transistor are disposed on the first extension portion and the first protrusion, respectively, and a portion and another portion of the channel layer of the second transistor are disposed on the second extension portion and the second protrusion, respectively.

5. A gate driver circuit as claimed in claim 3, wherein the first signal line has first and second opposite sides, the second signal line has third and fourth opposite sides, the second side of the first signal line and the third side of the second signal line are opposite to each other, and the first transistor, the second transistor, the first protrusion, and the second protrusion are located between the first side of the first signal line and the fourth side of the second signal line.

6. The gate driving circuit according to claim 5, wherein any one of the gate lines of the display panel extends along a first direction, and a projection of the first protrusion in the first direction partially overlaps a projection of the second protrusion in the first direction.

7. The gate driving circuit according to claim 5, wherein each of the shift registers further comprises a third transistor and a fourth transistor, gates of the third transistor and the fourth transistor respectively receive the first signal and the second signal, the first signal line and the second signal line respectively further have a third protrusion and a fourth protrusion, the third transistor, the fourth transistor, the third protrusion and the fourth protrusion are located between the first side of the first signal line and the fourth side of the second signal line, a channel layer of the third transistor is at least partially disposed on the third protrusion, and a channel layer of the fourth transistor is at least partially disposed on the fourth protrusion.

8. A gate driving circuit as claimed in claim 7, wherein any one of the gate lines of the display panel extends along a first direction, and a projection of at least one of the first projection and the third projection in the first direction partially overlaps a projection of at least one of the second projection and the fourth projection in the first direction.

9. The gate driver circuit of claim 1, wherein each of the shift registers further comprises:

the pre-charging unit is coupled with a first node and outputs a pre-charging signal by the first node;

a pull-up unit coupled to the first node and a second node, the pull-up unit outputting one of the plurality of scan signals to a corresponding one of the plurality of gate lines from the second node; and

a pull-down unit coupled to the first node and the second node, the pull-down unit including the first transistor and the second transistor, the pull-down unit receiving the precharge signal, the first signal, and the second signal.

10. A display panel having an active area and a peripheral area, the display panel comprising:

a plurality of gate lines; and

a gate driving circuit in the peripheral region, the gate driving circuit comprising:

a plurality of shift registers for providing a plurality of scanning signals to the plurality of gate lines, each shift register comprising a first transistor and a second transistor, wherein a gate of the first transistor and a gate of the second transistor respectively receive a first signal and a second signal; and

11. The display panel of claim 10, wherein the display panel is a system-integrated glass panel.