CN112579334A - Ethernet-based signal recording method and device facing processor - Google Patents
Ethernet-based signal recording method and device facing processor Download PDFInfo
- Publication number
- CN112579334A CN112579334A CN202011461903.1A CN202011461903A CN112579334A CN 112579334 A CN112579334 A CN 112579334A CN 202011461903 A CN202011461903 A CN 202011461903A CN 112579334 A CN112579334 A CN 112579334A
- Authority
- CN
- China
- Prior art keywords
- signal
- processor
- data
- recording
- observed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The disclosure provides a processor-oriented signal recording method, device, equipment and storage medium based on Ethernet. Wherein, the method comprises the following steps: acquiring a recording enabling signal, wherein the recording enabling signal indicates to record a signal to be observed in a processor; and responding to the record enabling signal, performing data recording on a plurality of signals to be observed in the processor, and sending data of at least one signal in the plurality of signals to be observed through the Ethernet interface.
Description
Technical Field
The present disclosure relates to processor debugging technologies, and more particularly, to an ethernet-based processor-oriented signal recording method, apparatus, device, and storage medium.
Background
In recent years, the rapid development of information processing applications such as artificial intelligence and big data processing makes the design of processors increasingly complex and large, and how to debug complex processors has become a difficult problem in processor verification. The debugging process of a complex processor often needs to acquire the execution sequence (for example, the program count pointer value) of multiple programs or multiple threads, the internal signals of the processor, registers, bus transactions and states, etc. to locate the software and hardware of the processor, while for general system-level debugging, the process often needs tens of hours less, and more needs several days or even longer, so how to record the execution sequence of the processor and the internal bus signals of the processor in real time to improve the debugging efficiency has become a difficult point in the debugging technology of the processor. The debugging technology of the current processor cannot record the track of the execution program of the processor in real time and for a long time, and is difficult to meet the debugging requirement of a complex processor.
Therefore, a method for recording signals during debugging of a processor in real time, for a long time and with high efficiency is needed.
Disclosure of Invention
In order to solve the above problems, the present disclosure realizes real-time, large-capacity, long-time, and efficient recording of debugging signal information inside a processor by transmitting recorded data of a signal to be observed back to a host via an ethernet interface in real time and completing offline analysis by the host.
The embodiment of the present disclosure provides a processor-oriented signal recording method based on ethernet, including: acquiring a recording enabling signal, wherein the recording enabling signal indicates to record a signal to be observed in the processor; and responding to the record enabling signal, performing data record on a plurality of signals to be observed in the processor, and sending data of at least one signal in the plurality of signals to be observed through an Ethernet interface.
According to an embodiment of the present disclosure, wherein the signal recording method further comprises: and responding to the record enabling signal, and setting a sending data source of the Ethernet interface as the recorded data of the plurality of signals to be observed inside the processor.
According to an embodiment of the present disclosure, wherein the signal recording method further comprises: and responding to the record enabling signal, resetting the Ethernet interface before setting the sending data source of the Ethernet interface, and resetting each module of the processor after completing the setting of the sending data source of the Ethernet interface.
According to an embodiment of the present disclosure, the data recording of the plurality of signals to be observed inside the processor and the sending of the data of at least one of the plurality of signals to be observed through the ethernet interface includes: determining a plurality of signals to be observed internal to the processor; sampling the plurality of signals to be observed, and selecting data of at least one signal from the sampled data of the plurality of signals to be observed; and transmitting data of the selected at least one signal through the ethernet interface.
According to an embodiment of the present disclosure, wherein the transmitting data of the selected at least one signal through the ethernet interface further comprises: adding an Ethernet packet header and an integrity check code to the data of the selected at least one signal to generate an Ethernet data packet, wherein the Ethernet packet header comprises a target address, a source address and a packet type; and sending the Ethernet data packet through an Ethernet interface.
According to an embodiment of the present disclosure, the determining a plurality of signals to be observed inside the processor further comprises: acquiring observation indication signals indicating a plurality of signals to be observed inside the processor; and determining the plurality of signals to be observed internal to the processor based on the observation indication signal.
According to an embodiment of the present disclosure, wherein the signal recording method further comprises: acquiring a recording disable signal, wherein the recording disable signal indicates to stop recording a signal to be observed in the processor; and responding to the recording disable signal, stopping recording the signal to be observed in the processor, and setting a sending data source of the Ethernet interface as normal operation data.
According to an embodiment of the present disclosure, wherein the signal to be observed includes at least one of: processor program count pointer, processor internal bus, processor internal register, and processor internal program execution sequence.
An embodiment of the present disclosure provides an ethernet-based processor-oriented signal recording apparatus, including: a signal receiving module configured to receive a recording enable signal indicating that a signal to be observed inside the processor is recorded; a signal recording module configured to perform data recording on a plurality of signals to be observed inside the processor in response to the recording enable signal; and an Ethernet interface module configured to transmit data of at least one of the plurality of signals to be observed through an Ethernet interface in response to the record enable signal.
According to an embodiment of the present disclosure, wherein the signal recording apparatus further includes: a signal selection module configured to: responding to the record enabling signal, setting a sending data source of the Ethernet interface module as the recorded data of a plurality of signals to be observed inside the processor; and selecting data of at least one signal from the recorded data of a plurality of signals to be observed inside the processor.
According to an embodiment of the present disclosure, wherein the signal recording apparatus further includes: a reset control module configured to reset the ethernet interface module before setting the transmission data source of the ethernet interface module in response to the record enable signal, and reset the modules of the processor after the signal selection module completes the setting of the transmission data source of the ethernet interface module.
According to an embodiment of the present disclosure, the signal recording module includes a first number of signal samplers and a first number of recording data registers, wherein each signal sampler is configured to sample one of the plurality of signals to be observed and store the obtained sampled data in a corresponding recording data register.
According to an embodiment of the present disclosure, wherein the record data register is an asynchronous first-in first-out register.
According to an embodiment of the present disclosure, wherein the ethernet interface module includes: the signal packer is used for adding an Ethernet packet header and an integrity check code to data of at least one signal in the plurality of signals to be observed so as to generate an Ethernet data packet, wherein the Ethernet packet header comprises a target address, a source address and a packet type; and the Ethernet interface is used for sending the Ethernet data packet through the Ethernet interface.
According to an embodiment of the present disclosure, wherein the signal receiving module is further configured to receive an observation indication signal indicating a plurality of signals to be observed inside the processor; wherein the signal recording module is further configured to determine the plurality of signals to be observed internal to the processor based on the observation indication signal.
According to an embodiment of the present disclosure, the signal receiving module is further configured to receive a recording disable signal, where the recording disable signal indicates to stop recording a signal to be observed inside the processor; wherein the signal recording module is further configured to stop recording a signal to be observed inside the processor in response to the recording disable signal; and the signal selection module is further configured to set a transmission data source of the ethernet interface module as normal operation data in response to the recording disable signal.
According to the embodiment of the disclosure, based on the running state of the processor comprising a debugging state and a normal state, the running mode of the signal recording device comprises a signal recording mode and a normal running mode, wherein in response to the processor entering the debugging state from the normal state, the recording enable signal is sent to the signal recording device, so that the signal recording device enters the signal recording mode; and responding to the processor returning to the normal state from the debugging state, sending the recording disabling signal to the signal recording device, so that the signal recording device enters the normal operation mode.
According to an embodiment of the present disclosure, wherein the signal to be observed includes at least one of: processor program count pointer, processor internal bus, processor internal register, and processor internal program execution sequence.
An embodiment of the present disclosure provides an ethernet-based processor-oriented signal recording device, including: a processor; and a memory having stored thereon computer-executable instructions for implementing the method as described above when executed by the processor.
Embodiments of the present disclosure provide a computer-readable storage medium having stored thereon computer-executable instructions for implementing the method as described above when executed by a processor.
Embodiments of the present disclosure provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the ethernet-based processor-oriented signal recording method according to the embodiments of the present disclosure.
The embodiment of the disclosure provides a method, a device, equipment and a storage medium for recording signals facing a processor based on an Ethernet. According to the method provided by the embodiment of the disclosure, the signal to be observed, the register and the like in the processor are recorded and packaged, then the data packet of the recorded signal is sent to the host computer through the Ethernet interface in real time, and offline analysis is completed on the host computer, so that real-time, long-time and large-capacity recording of debugging signal information in the processor is realized, the efficiency and the depth of verification and debugging of the processor are greatly improved, meanwhile, the method can be reused for realizing real-time transmission and analysis of related recorded signals of other functions when the processor is in a non-debugging state, and the method has wide applicability.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings used in the description of the embodiments will be briefly introduced below. It is apparent that the drawings in the following description are only exemplary embodiments of the disclosure, and that other drawings may be derived from those drawings by a person of ordinary skill in the art without inventive effort.
Fig. 1 shows a flow diagram of an ethernet-based processor-oriented signal recording method 100 according to an embodiment of the present disclosure.
Fig. 2 shows a schematic structural diagram of an ethernet packet according to an embodiment of the present disclosure.
Fig. 3 illustrates a flow chart of an ethernet-based processor-oriented signal recording method 300 according to an embodiment of the present disclosure.
Fig. 4a shows a schematic diagram of an ethernet-based processor-oriented signal recording apparatus 400 according to an embodiment of the present disclosure.
Fig. 4b shows a detailed internal schematic diagram of an ethernet-based processor-oriented signal recording apparatus 400 according to an embodiment of the present disclosure.
Fig. 5 illustrates a workflow diagram of an ethernet-based processor-oriented signal recording apparatus according to an embodiment of the present disclosure.
Fig. 6 shows a schematic diagram of an ethernet-based processor-oriented signal recording device 600 according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present disclosure more apparent, example embodiments according to the present disclosure will be described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of the embodiments of the present disclosure and not all embodiments of the present disclosure, with the understanding that the present disclosure is not limited to the example embodiments described herein.
In the present specification and the drawings, substantially the same or similar steps and elements are denoted by the same or similar reference numerals, and repeated descriptions of the steps and elements will be omitted. Meanwhile, in the description of the present disclosure, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance or order.
In the specification and drawings, elements are described in singular or plural according to embodiments. However, the singular and plural forms are appropriately selected for the proposed cases only for convenience of explanation and are not intended to limit the present disclosure thereto. Thus, the singular may include the plural and the plural may also include the singular, unless the context clearly dictates otherwise.
The verification and debugging of a complex processor often needs to record a program execution sequence of the processor, observe internal signals, register values, bus transactions, states and the like of the processor, so that the real-time and large-capacity recording of the program execution sequence or the bus transactions and the like is very important for improving the efficiency of the verification and debugging.
A processor debugging technology can be based on an external logic analyzer, signals to be observed, registers and the like in a processor are connected to a debugging bus and output to pins, and then signal data, register values and the like in the processor are sampled and obtained through the external logic analyzer to be used for debugging and observing. The external logic analyzer can only sample dozens to hundreds of signals due to the limitation of sampling width and depth, the sampling depth is only thousands to millions of clock cycles, and the width and depth of data which can be observed simultaneously are also very limited, so that the method cannot record the track of a processor execution program in real time and for a long time, the debugging requirements on various complex applications and software and hardware on the processor are difficult to meet, in addition, the method also needs to occupy debugging pins, and the bus width which can be observed simultaneously is also very limited.
Therefore, the present disclosure provides a method and an apparatus for recording signals to a processor based on ethernet, which can obtain key information in the processor in real time, for a long time, and efficiently.
Embodiments of the present disclosure will be further described with reference to the accompanying drawings.
Fig. 1 shows a flow diagram of an ethernet-based processor-oriented signal recording method 100 according to an embodiment of the present disclosure.
As shown in fig. 1, first, at step 101, a recording enable signal may be acquired, the recording enable signal indicating that a signal to be observed inside a processor is recorded.
The acquisition of the recording enable signal can indicate that the processor needs to be debugged currently, and the signal to be observed in the processor needs to be recorded in the debugging process. Wherein, according to an embodiment of the present disclosure, the signal to be observed may include at least one of: processor program count pointer, processor internal bus, processor internal register, and processor internal program execution sequence. According to an embodiment of the present disclosure, the signal to be observed may also be any other signal that needs to be recorded inside the processor.
Then, at step 102, in response to the record enable signal, data recording may be performed on a plurality of signals to be observed inside the processor, and data of at least one of the plurality of signals to be observed may be transmitted through the ethernet interface.
According to an embodiment of the present disclosure, data recording the plurality of signals to be observed inside the processor and transmitting data of at least one signal of the plurality of signals to be observed through the ethernet interface may include determining the plurality of signals to be observed inside the processor; sampling a plurality of signals to be observed, and selecting data of at least one signal from the sampled data of the plurality of signals to be observed; and transmitting data of the selected at least one signal through the ethernet interface.
Wherein, according to an embodiment of the present disclosure, determining the plurality of signals to be observed inside the processor may further include obtaining an observation indication signal indicating the plurality of signals to be observed inside the processor, and determining the plurality of signals to be observed inside the processor based on the observation indication signal. By this observation indication signal, it is possible to determine to record a plurality of signals such as a processor program count pointer, a processor internal bus, and the like among various signals to be observed inside the processor. After determining the plurality of signals to be observed to be recorded, the signals may be sampled separately to obtain sampled data for each signal. Considering that these sampled data can be transmitted in packets, the data of at least one signal to be currently transmitted can be selected among the sampled data of these signals. For example, the plurality of signals to be observed may include debug signals A, B, C and D, the four debug signals are all sampled and the sampled data of each signal is obtained, and the sampled data of these signals may be transmitted in packets, where the data transmitted at a single time may include 64-bit data of debug signal a, 32-bit data of debug signal B, and 32-bit data of debug signal C.
According to an embodiment of the present disclosure, transmitting the data of the selected at least one signal through the ethernet interface may further include adding an ethernet header and an integrity check code to the data of the selected at least one signal to generate an ethernet data packet, wherein the ethernet header may include a destination address, a source address, a packet type; and sending the Ethernet data packet through the Ethernet interface. A data packet conforming to the ethernet standard may be generated by adding various control information to the data of the selected at least one signal, which may be transmitted in real time via the ethernet interface to a host for parsing the data packet.
Specifically, fig. 2 shows a schematic structural diagram of an ethernet packet according to an embodiment of the present disclosure.
As shown in fig. 2, an ethernet packet may include a destination address field, a source address field, a type/length field, a data field, and a redundancy check field. The destination address field may indicate a transmission destination address of the data packet, the source address field may indicate a source address of the data packet, the type/length field may indicate an upper layer protocol after the data packet is transmitted to the destination address, the data field may include data to be transmitted, padding data, an upper layer protocol, and the like, and the redundancy check field may include an integrity check code for checking whether damage occurs during data transmission. When the host receives the Ethernet data packet, firstly checking whether the target address of the data packet is matched with the local address, if so, continuously checking the redundancy check code field to determine whether the data packet is complete, after the completion is confirmed, removing auxiliary information such as the address and the redundancy check in the data packet and extracting recorded signal data, and sending the data to an upper layer protocol indicated by the type/length field for subsequent processing.
According to the embodiment of the present disclosure, the host for offline parsing may receive the ethernet packet via its ethernet interface, capture the relevant packet by a commonly used packet capture tool (e.g., ethernet packet capture tool Wireshark), and store it in the host file for subsequent parsing, so that the signal recording method 100 can theoretically achieve processor-internal signal recording with approximately infinite duration and infinite depth.
The ethernet-based processor-oriented signal recording method proposed by the present disclosure may comprise further steps in addition to the steps as described with reference to fig. 1. In particular, as a non-limiting example, fig. 3 shows a flow chart of an ethernet-based processor-oriented signal recording method 300 according to an embodiment of the present disclosure. As shown in fig. 3, based on the signal recording method 100, the signal recording method 300 may include the following steps in addition to the steps 101 and 102.
According to an embodiment of the present disclosure, at step 303, in response to the record enable signal, the ethernet interface may be reset.
In response to the record enable signal, the ethernet interface may be first enabled to enter a state capable of sending data, so as to avoid a situation that data required to be sent by the module cannot be sent after the other modules are first enabled and then the data is transferred to the ethernet interface.
According to an embodiment of the present disclosure, at step 304, in response to the record enable signal, a transmission data source of the ethernet interface may be set as the recorded data of the plurality of signals to be observed inside the processor.
After the start of the ethernet interface is completed, a data sending source thereof may be set to communicate the recorded data of the plurality of signals to be observed inside the processor to the ethernet interface.
According to an embodiment of the present disclosure, at step 305, in response to the record enable signal, the modules of the processor may be reset after the setup of the transmission data source of the ethernet interface is completed.
After completing the operations of steps 303 and 304, the preparation for sending the logging data required by debugging the processor is completed, and at this time, the modules in the processor may be reset, so that the processor starts debugging operations, and the data of the signal to be observed may flow into the ethernet interface normally.
According to an embodiment of the present disclosure, at step 306, a logging disable signal may be obtained, the logging disable signal indicating that logging of a signal to be observed inside the processor is stopped.
Acquiring the logging disable signal may indicate that the current processor has exited debugging and may therefore indicate to stop logging the signal to be observed within the processor.
According to the embodiment of the present disclosure, at step 307, in response to the recording disable signal, the signal to be observed inside the recording processor is stopped, and the transmission data source of the ethernet interface is set as normal operation data.
After the processor exits debugging, the steps of the signal recording method 300 may be multiplexed into the real-time transfer of the relevant signal records that implement other functions of the processor by setting the sending data source of the ethernet interface to normal operating data.
Fig. 4a shows a schematic diagram of an ethernet-based processor-oriented signal recording apparatus 400 according to an embodiment of the present disclosure.
As shown in fig. 4a, the ethernet-based processor-oriented signal recording apparatus 400 may include a signal receiving module 401, a signal recording module 402, and an ethernet interface module 403.
The signal receiving module 401 may be configured to receive a recording enable signal, which may indicate that a signal to be observed inside the processor is recorded. The receiving of the recording enable signal may indicate that the processor needs to be debugged currently, and the recording enable signal may indicate to record a signal to be observed during the debugging process of the processor. According to an embodiment of the present disclosure, the signal to be observed may include at least one of: processor program count pointer, processor internal bus, processor internal register, and processor internal program execution sequence. According to an embodiment of the present disclosure, the signal to be observed may also be any other signal that needs to be recorded inside the processor.
According to an embodiment of the present disclosure, the signal receiving module 401 may be further configured to receive an observation indication signal, which may indicate a plurality of signals to be observed inside the processor. According to an embodiment of the present disclosure, the observation indication signal may indicate that a plurality of signals such as a processor program count pointer, a processor internal bus, and the like among various signals to be observed are recorded.
According to an embodiment of the present disclosure, the signal receiving module 401 may be further configured to receive a recording disable signal, which may instruct to stop recording the signal to be observed inside the processor; wherein the signal recording module 402 may be configured to stop recording the signal to be observed inside the processor in response to the recording disable signal. Receipt of the logging disable signal may indicate that the current processor has exited debugging and thus the logging disable signal may indicate that the signal logging module 402 is no longer logging signals to be observed within the processor.
The signal recording module 402 may be configured to perform data recording of a plurality of signals to be observed inside the processor in response to the recording enable signal. According to an embodiment of the present disclosure, the signal recording module 402 may be further configured to determine a plurality of signals to be observed inside the processor based on the observation indicative signal.
According to an embodiment of the present disclosure, the signal recording module 402 may determine to record a plurality of signals, such as a processor program counter pointer, a processor internal bus, and the like, among various signals to be observed based on the observation indication signal, and then sample each of the determined plurality of signals to be observed respectively and store corresponding sample data thereof.
According to an embodiment of the present disclosure, the signal recording apparatus 400 may further include a signal selection module 404 and a reset control module 405.
According to an embodiment of the present disclosure, the signal selection module 404 may be configured to set the transmission data source of the ethernet interface module 403 as the recorded data of the plurality of signals to be observed inside the processor in response to the recording enable signal, and select data of at least one signal from the recorded data of the plurality of signals to be observed inside the processor. The signal selection module 404 may select a transmission data source required to implement a current function (e.g., a debugging function) from among a plurality of transmission data sources corresponding to signal records for implementing different functions of the processor, and select data of at least one signal to be currently recorded from the transmission data sources to transfer to the ethernet interface module 403.
The ethernet interface module 403 may be configured to transmit data of at least one signal of the plurality of signals to be observed through the ethernet interface in response to the logging enable signal. The ethernet interface module 403 may generate a data packet conforming to the ethernet standard by adding various control information to the data of at least one of the signals to be observed, and transmit the data packet to a host for parsing the data packet in real time via the ethernet interface.
According to an embodiment of the present disclosure, the signal selection module 404 may be further configured to set the transmission data source of the ethernet interface module 403 as normal operation data in response to the logging disable signal. After the processor exits the debugging, the signal recording apparatus 400 can be reused to implement the real-time transmission of the related signal records of other functions of the processor by setting the sending data source of the ethernet interface module 403 as the normal operation data.
According to an embodiment of the present disclosure, the reset control module 405 may be configured to preferentially reset the ethernet interface module 403 before setting the transmission data source of the ethernet interface module 403 in response to the record enable signal, and reset the respective modules of the processor after the signal selection module 404 completes the setting of the transmission data source of the ethernet interface module 403.
In response to the record enable signal, the reset control module 405 may instruct the entire signal recording apparatus 400 to start the real-time debug recording function, at which point the reset control module 405 may apply an improved reset control procedure, which will temporarily suppress the resetting of the processor and other modules in the signal recording apparatus 400 and preferentially reset the ethernet interface module 403. After the reset of the ethernet interface module 403 and the setting of the sending data source are completed, the sending interface of the signal recording apparatus 400 is turned on, and at this time, each module of the processor may be reset, so that the data of the signal to be observed may normally flow into the ethernet interface module 403.
In particular, as a non-limiting example, fig. 4b shows a specific internal schematic diagram of an ethernet-based processor-oriented signal recording apparatus 400 according to an embodiment of the present disclosure.
As shown in fig. 4b, the ethernet-based processor-oriented signal recording apparatus 400 may include a signal receiving module 401, a signal recording module 402, and an ethernet interface module 403.
The signal receiving module 401 may be configured to receive a recording enable signal, which may indicate that a signal to be observed inside the processor is recorded. The receiving of the recording enable signal may indicate that the processor needs to be debugged currently, and the recording enable signal may indicate to record a signal to be observed during the debugging process of the processor. According to an embodiment of the present disclosure, the signal to be observed may include at least one of: processor program count pointer, processor internal bus, processor internal register, and processor internal program execution sequence.
According to an embodiment of the present disclosure, the signal receiving module 401 may be further configured to receive an observation indication signal, which may indicate a plurality of signals to be observed inside the processor; wherein the signal recording module 402 may be configured to determine a plurality of signals to be observed internal to the processor based on the observation indication signal. According to an embodiment of the present disclosure, the signal recording apparatus 400 may determine to record a plurality of signals such as a processor program count pointer, a processor internal bus, and the like among various signals to be observed based on the observation indication signal.
According to an embodiment of the present disclosure, the signal receiving module 401 may be further configured to receive a recording disable signal, which may instruct to stop recording the signal to be observed inside the processor; wherein the signal recording module 402 may be further configured to stop recording the signal to be observed inside the processor in response to the recording disable signal. Receipt of the logging disable signal may indicate that the current processor has exited debugging and thus the logging disable signal may indicate that the signal logging module 402 is no longer logging signals to be observed within the processor.
The signal recording module 402 may be configured to perform data recording of a plurality of signals to be observed inside the processor in response to the recording enable signal.
According to an embodiment of the present disclosure, the signal recording module 402 may include a first number of signal samplers 412 and a first number of recorded data registers 422, where each signal sampler 412 may be configured to sample one of the plurality of signals to be observed and store the obtained sampled data in a corresponding recorded data register 422.
According to an embodiment of the present disclosure, the signal sampler 412 may locally sample the signal to be observed based on the clock domain in which the signal is located and store its data in the corresponding logging data register 422. The record data register 422 may be an asynchronous first-in first-out register, according to embodiments of the present disclosure. The read and write operations of the logging data register 422 may be performed separately depending on the clock domains of the read and write sides, and the logging data register 422 may enable the signal sampler 412 based on its empty/full state. According to an embodiment of the present disclosure, the data size storable by the logging data register 422 may be 1536 bytes. According to the ethernet protocol, the length of the normal ethernet packet is not greater than 0x0600(1536) bytes, so the record data register 422 can store the data of the signal to be observed in the size of the data size of the complete ethernet packet.
The ethernet interface module 403 may be configured to transmit data of at least one signal of the plurality of signals to be observed through the ethernet interface in response to the logging enable signal.
According to an embodiment of the present disclosure, the ethernet interface module 403 may include: a signal packetizer 413, which may be configured to add an ethernet header and an integrity check code to data of at least one of the plurality of signals to be observed to generate an ethernet packet, wherein the ethernet header may include a destination address, a source address, and a packet type; and an ethernet interface 423 that may be used to transmit ethernet packets over the ethernet interface 423.
According to an embodiment of the present disclosure, in the ethernet packet transmitted by the signal recording apparatus 400 in response to the record enable signal, the destination address may be an address of the host for offline resolution, the source address may be an address of the signal recording apparatus 400, the data field may include data of at least one of the plurality of signals to be observed, and the redundancy check field may be an integrity check code such as a cyclic redundancy check code. When the host receives the Ethernet data packet, firstly checking whether the target address of the data packet is matched with the local address, if so, continuously checking the redundancy check field to determine whether the data packet is complete, after the completion is confirmed, removing auxiliary information such as the address and the redundancy check in the data packet and extracting recorded signal data, and sending the data to an upper layer protocol indicated by the type/length field for subsequent processing.
According to an embodiment of the present disclosure, the ethernet packet may include therein sampled data of a plurality of signals to be observed. For each of the multiple data sources that can be sent by the signal recording apparatus 400, the data of each signal may be stored in a data packet according to a corresponding predetermined data source format, for example, an ethernet data packet corresponding to the current data source may include 128 bits of data, where the data of the debug signal a is located in [ 0: 63] bits, the data of debug signal B is located in [ 64: 95] bits, the data of debug signal C is located in [ 96: 127. After being sent to the host, the host can respectively parse the data belonging to different signals in the data packet according to the predetermined data source format.
According to an embodiment of the present disclosure, when the sending data source of the ethernet interface module 403 is changed, the signal packetizer 413 may insert a gap packet between two data packets before and after the change to indicate the change of the sending data source. The interval packet may be a data packet in a special format (e.g., 0xdeadbeef character padding), and in the subsequent parsing by the host, if the content of the received data packet is determined to be the same as that of the interval packet, it is determined that the sending data source of the next data packet will be changed, and a new predetermined data source format is applied to the changed sending data source for parsing.
According to an embodiment of the present disclosure, the ethernet interface 423 may include a Media Access Control (MAC) interface and a Physical Layer (PHY) interface. Wherein, after receiving the data packet from the signal packetizer 413, the MAC interface may split and repackage the data packet such that the data packet includes the destination MAC address and its own source MAC address, and then send it to the PHY interface. The PHY interface is primarily responsible for encoding and serializing data from the MAC interface and then converting the digital signal to an analog signal for transmission. According to the embodiment of the present disclosure, the host for offline parsing may receive the ethernet packet from the signal recording apparatus 400 via its ethernet interface, capture the relevant packet by a commonly used packet capture tool (e.g., ethernet packet capture tool Wireshark) and store it in the host file for subsequent parsing, so that the signal recording apparatus 400 can theoretically realize processor-internal signal recording with approximately infinite duration and infinite depth.
According to an embodiment of the present disclosure, the ethernet-based processor-oriented signal recording apparatus 400 may further include a signal selection module 404 and a reset control module 405.
According to an embodiment of the present disclosure, the signal selection module 404 may be configured to set the transmission data source of the ethernet interface module 403 as the recorded data of the plurality of signals to be observed inside the processor in response to the recording enable signal, and select data of at least one signal from the recorded data of the plurality of signals to be observed inside the processor.
According to an embodiment of the present disclosure, the signal selection module 404 may include a signal selector 414, and the signal selector 414 may select at least one signal to be observed from a plurality of signals to be observed, gate its corresponding recorded data register 422 and extract the sampled data of the signal therefrom, and write it into the signal packetizer 413 in the ethernet interface module 403.
According to an embodiment of the disclosure, the signal selection module 404 may select, by using the signal selector 414, a transmission data source required to implement a current function (e.g., a debugging function) among a plurality of transmission data sources corresponding to signal records for implementing different functions of a processor. Wherein, for each data source transmittable by the signal recording apparatus 400, the transmitting data source may include data of a plurality of signals to be recorded, and the data read from the data source may be in a predetermined data source format corresponding thereto. For example, in a case where a debugging function of the processor needs to be implemented in response to the record enable signal, the signal selector 414 may set the transmission data source of the ethernet interface module 403 as a debugging signal data source (i.e., data of a plurality of signals to be observed), and sequentially read data of a part of signals from the data of the plurality of signals to be observed according to a predetermined data source format corresponding to the transmission data source, for example, sequentially gate and extract 64-bit data of the debugging signal a, 32-bit data of the debugging signal B, and 32-bit data of the debugging signal C.
According to an embodiment of the present disclosure, the reset control module 405 may be configured to preferentially reset the ethernet interface module 403 before setting the transmission data source of the ethernet interface module 403 in response to the record enable signal, and reset the respective modules of the processor after the signal selection module 404 completes the setting of the transmission data source of the ethernet interface module 403.
In response to the record enable signal, the reset control module 405 may instruct the entire signal recording apparatus 400 to start the real-time debug recording function, at which point the reset control module 405 may apply an improved reset control procedure, which will temporarily suppress the resetting of the processor and other modules in the signal recording apparatus 400 and preferentially reset the ethernet interface module 403. After the reset of the ethernet interface module 403 and the setting of the sending data source are completed, the sending interface of the signal recording apparatus 400 is turned on, and at this time, each module of the processor may be reset, so that the data of the signal to be observed may normally flow into the ethernet interface module 403.
As described above, the signal recording apparatus 400 can select any signal to be recorded, such as a processor program counter pointer, a processor internal bus, etc., record its sample data in the corresponding recording data register 422, perform the gating on the sample data by the signal selector 414 to generate a data packet conforming to the ethernet standard format, and transmit the data packet to the host via the ethernet interface 423 in real time to complete the signal recording.
According to an embodiment of the present disclosure, the signal selection module 404 may be further configured to set the transmission data source of the ethernet interface module 403 as normal operation data in response to the logging disable signal. After the processor exits the debugging, the signal recording apparatus 400 may be reused to implement real-time transmission of related signal records of other functions of the processor by setting the sending data source of the ethernet interface module 403 as normal operation data.
According to an embodiment of the present disclosure, based on the operating state of the processor may include a debugging state and a normal state, the operating mode of the signal recording apparatus 400 may include a signal recording mode and a normal operating mode, wherein, in response to the processor entering the debugging state from the normal state, a recording enable signal is sent to the signal recording apparatus 400, so that the signal recording apparatus 400 enters the signal recording mode; in response to the processor returning to the normal state from the debug state, a logging disable signal is sent to signal logging apparatus 400, causing signal logging apparatus 400 to enter a normal operating mode. The operating mode of signal recording device 400 may be switched in response to a change in the operating state of the current processor.
Fig. 5 illustrates a workflow diagram of an ethernet-based processor-oriented signal recording apparatus according to an embodiment of the present disclosure. Specifically, fig. 5 shows a process of switching the operation mode of the signal recording apparatus with the change of the operation state of the processor after the signal recording apparatus is activated, in consideration that the operation mode of the signal recording apparatus can be switched between the signal recording mode and the normal operation mode accordingly as the operation state of the processor changes between the debug state and the normal state.
As shown in fig. 5, after the signal recording apparatus is activated, whether a recording enable signal is received may be determined by the signal receiving module (501).
If the processor is always running in the normal state, the signal receiving module does not receive the record enabling signal, and all modules of the processor can be normally reset by the reset control module (502), so that all modules of the processor are started (503) and run the program normally (504). In this case, the signal recording device operates in a normal operation mode, which may be used to transmit an ethernet packet of related signals that needs to be recorded when the processor performs other operations except for the debugging task, where a transmission data source of the ethernet interface module in the signal recording device is a common data register.
According to the embodiment of the disclosure, in response to the processor entering the debugging state from the normal state, a recording enable signal may be sent to the signal receiving module. After the signal receiving module determines that the recording enable signal is received, the signal recording apparatus may be instructed to enter a signal recording mode. First, a reset control flow setting (510) of each block in the signal recording apparatus and the processor is performed by a reset control block, and then the ethernet interface block is preferentially reset according to the reset control flow (511). After the Ethernet interface module is reset, the sending data source of the Ethernet interface module can be switched to the recording data register (512) in the signal recording module from the common data register through the signal selection module. After the foregoing steps are completed, the preparation of the signal recording device for sending debug record data is completed, at this time, other modules of the device and modules in the processor may be reset (513), so that the processor starts debugging operations (514), and sends the debug record data packet acquired by the device to the host for parsing through the ethernet interface.
During the debugging process of the processor, whether the recording disabling signal is received or not can be judged in real time by the signal receiving module (515).
According to the embodiment of the disclosure, in response to the processor returning to the normal state from the debugging state, a recording disable signal may be sent to the signal receiving module. If the signal recording device is kept started, after the signal receiving module determines that the recording disabling signal is received, the signal recording device is indicated to be switched from the signal recording mode to the normal operation mode, at this time, a sending data source of the Ethernet interface module can be switched to other common data registers (516) from a recording data register in the signal recording module, the signal recording device can be multiplexed in real-time transmission of relevant signal recording for realizing other functions of the processor in the normal operation mode, and after the switching of the sending data source is completed, the processor can restore normal program operation (504).
Fig. 6 shows a schematic diagram of an ethernet-based processor-oriented signal recording device 600 according to an embodiment of the present disclosure.
As shown in fig. 6, an ethernet-based processor-oriented signal recording device 600 according to an embodiment of the present disclosure may include a processor 601 and a memory 602, which may be interconnected by a bus 603.
The processor 601 may perform various actions and processes according to programs or codes stored in the memory 602. In particular, the processor 601 may be an integrated circuit chip having signal processing capabilities. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, flows, and logic blocks disclosed in the embodiments of the disclosure may be implemented or performed. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, which may be the X86 architecture or the ARM architecture or the like.
The memory 602 stores executable instructions that, when executed by the processor 601, are used to implement an ethernet-based processor-oriented signal recording method according to an embodiment of the present disclosure. The memory 602 may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchronous Link Dynamic Random Access Memory (SLDRAM), and direct memory bus random access memory (DRRAM). It should be noted that the memories of the methods described herein are intended to comprise, without being limited to, these and any other suitable types of memory.
Embodiments of the present disclosure also provide a computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, may implement an ethernet-based processor-oriented signal recording method according to an embodiment of the present disclosure. Similarly, computer-readable storage media in embodiments of the disclosure may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. It should be noted that the memories of the methods described herein are intended to comprise, without being limited to, these and any other suitable types of memory.
Embodiments of the present disclosure also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the ethernet-based processor-oriented signal recording method according to the embodiments of the present disclosure.
The embodiment of the disclosure provides a method, a device, equipment and a storage medium for recording signals facing a processor based on an Ethernet. According to the method provided by the embodiment of the disclosure, the signal to be observed, the register and the like in the processor are recorded and packaged, then the data packet of the recorded signal is sent to the host computer through the Ethernet interface in real time, and offline analysis is completed on the host computer, so that real-time, long-time and large-capacity recording of debugging signal information in the processor is realized, the efficiency and the depth of verification and debugging of the processor are greatly improved, meanwhile, the method can be reused for realizing real-time transmission and analysis of related recorded signals of other functions when the processor is in a non-debugging state, and the method has wide applicability.
It is to be noted that the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises at least one executable instruction for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In general, the various example embodiments of this disclosure may be implemented in hardware or special purpose circuits, software, firmware, logic or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While aspects of embodiments of the disclosure have been illustrated or described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.
The exemplary embodiments of the present disclosure described in detail above are merely illustrative, and not restrictive. It will be appreciated by those skilled in the art that various modifications and combinations of these embodiments or features thereof may be made without departing from the principles and spirit of the disclosure, and that such modifications are intended to be within the scope of the disclosure.
Claims (20)
1. An ethernet-based processor-oriented signal recording method, comprising:
acquiring a recording enabling signal, wherein the recording enabling signal indicates to record a signal to be observed in the processor; and
and responding to the record enabling signal, performing data record on a plurality of signals to be observed in the processor, and sending data of at least one signal in the plurality of signals to be observed through an Ethernet interface.
2. The signal recording method of claim 1, further comprising:
and responding to the record enabling signal, and setting a sending data source of the Ethernet interface as the recorded data of the plurality of signals to be observed inside the processor.
3. The signal recording method of claim 2, further comprising:
and responding to the record enabling signal, resetting the Ethernet interface before setting the sending data source of the Ethernet interface, and resetting each module of the processor after completing the setting of the sending data source of the Ethernet interface.
4. The signal recording method of claim 1, wherein the data recording the plurality of signals to be observed inside the processor and transmitting data of at least one of the plurality of signals to be observed through an ethernet interface comprises:
determining a plurality of signals to be observed internal to the processor;
sampling the plurality of signals to be observed, and selecting data of at least one signal from the sampled data of the plurality of signals to be observed; and
transmitting data of the selected at least one signal through the Ethernet interface.
5. The signal recording method of claim 4, wherein the transmitting data of the selected at least one signal through the ethernet interface further comprises:
adding an Ethernet packet header and an integrity check code to the data of the selected at least one signal to generate an Ethernet data packet, wherein the Ethernet packet header comprises a target address, a source address and a packet type; and
and sending the Ethernet data packet through an Ethernet interface.
6. The signal recording method of claim 4, wherein said determining a plurality of signals to be observed internal to the processor further comprises:
acquiring observation indication signals indicating a plurality of signals to be observed inside the processor; and
determining the plurality of signals to be observed internal to the processor based on the observation indication signal.
7. The signal recording method of claim 2, further comprising:
acquiring a recording disable signal, wherein the recording disable signal indicates to stop recording a signal to be observed in the processor; and
and in response to the recording disable signal, stopping recording the signal to be observed in the processor, and setting a sending data source of the Ethernet interface as normal operation data.
8. The signal recording method of claim 1, wherein the signal to be observed comprises at least one of: processor program count pointer, processor internal bus, processor internal register, and processor internal program execution sequence.
9. An ethernet-based processor-oriented signal recording device comprising:
a signal receiving module configured to receive a recording enable signal indicating that a signal to be observed inside the processor is recorded;
a signal recording module configured to perform data recording on a plurality of signals to be observed inside the processor in response to the recording enable signal; and
an Ethernet interface module configured to transmit data of at least one of the plurality of signals to be observed through an Ethernet interface in response to the record enable signal.
10. The signal recording apparatus of claim 9, further comprising:
a signal selection module configured to:
responding to the record enabling signal, setting a sending data source of the Ethernet interface module as the recorded data of a plurality of signals to be observed inside the processor; and
selecting data for at least one signal from the recorded data for a plurality of signals to be observed internal to the processor.
11. The signal recording apparatus of claim 10, further comprising:
a reset control module configured to reset the ethernet interface module before setting the transmission data source of the ethernet interface module in response to the record enable signal, and reset the modules of the processor after the signal selection module completes the setting of the transmission data source of the ethernet interface module.
12. The signal recording device of claim 9, wherein the signal recording module comprises a first number of signal samplers and a first number of recorded data registers, wherein each signal sampler is configured to sample one of the plurality of signals to be observed and store the obtained sampled data in a corresponding recorded data register.
13. The signal recording device of claim 12, wherein the recording data register is an asynchronous first-in first-out register.
14. The signal recording device according to claim 9, wherein the ethernet interface module comprises:
the signal packer is used for adding an Ethernet packet header and an integrity check code to data of at least one signal in the plurality of signals to be observed so as to generate an Ethernet data packet, wherein the Ethernet packet header comprises a target address, a source address and a packet type; and
and the Ethernet interface is used for sending the Ethernet data packet through the Ethernet interface.
15. The signal recording apparatus of claim 9, wherein the signal receiving module is further configured to receive an observation indication signal, the observation indication signal indicating a plurality of signals to be observed internal to the processor;
wherein the signal recording module is further configured to determine the plurality of signals to be observed internal to the processor based on the observation indication signal.
16. The signal recording device of claim 10, wherein the signal receiving module is further configured to receive a recording disable signal indicating to stop recording a signal to be observed inside the processor;
wherein the signal recording module is further configured to stop recording a signal to be observed inside the processor in response to the recording disable signal; and
the signal selection module is further configured to set a transmission data source of the ethernet interface module as normal operation data in response to the record disable signal.
17. The signal recording apparatus according to claim 10 or 16, wherein the operation mode of the signal recording apparatus includes a signal recording mode and a normal operation mode based on the operation state of the processor including a debug state and a normal state, wherein,
in response to the processor entering the debug state from the normal state, sending the record enable signal to the signal recording device, so that the signal recording device enters the signal recording mode;
and responding to the processor returning to the normal state from the debugging state, sending the recording disabling signal to the signal recording device, so that the signal recording device enters the normal operation mode.
18. The signal recording apparatus of claim 9, wherein the signal to be observed comprises at least one of: processor program count pointer, processor internal bus, processor internal register, and processor internal program execution sequence.
19. An ethernet-based processor-oriented signal recording device comprising:
a processor; and
memory having stored thereon computer-executable instructions for implementing the method of any one of claims 1-8 when executed by the processor.
20. A computer-readable storage medium having stored thereon computer-executable instructions for implementing the method of any one of claims 1-8 when executed by a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011461903.1A CN112579334B (en) | 2020-12-08 | 2020-12-08 | Signal recording method and device for processor based on Ethernet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011461903.1A CN112579334B (en) | 2020-12-08 | 2020-12-08 | Signal recording method and device for processor based on Ethernet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112579334A true CN112579334A (en) | 2021-03-30 |
| CN112579334B CN112579334B (en) | 2023-04-25 |
Family
ID=75132266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011461903.1A Active CN112579334B (en) | 2020-12-08 | 2020-12-08 | Signal recording method and device for processor based on Ethernet |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112579334B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050198546A1 (en) * | 2004-03-02 | 2005-09-08 | Matsushita Electric Industrial Co., Ltd. | Device and method for controlling an internal state of information processing equipment |
| CN101334667A (en) * | 2007-06-26 | 2008-12-31 | 株洲南车时代电气股份有限公司 | Locomotive status messages checking and diagnosis recording method and device |
| JP2010044622A (en) * | 2008-08-13 | 2010-02-25 | Hitachi Information & Communication Engineering Ltd | Information processor test program and method |
| CN102216909A (en) * | 2011-05-27 | 2011-10-12 | 华为技术有限公司 | A network processor and a diagnostic method of procedures stored in the network process |
| CN102566470A (en) * | 2012-01-11 | 2012-07-11 | 株洲南车时代电气股份有限公司 | System and method for timely monitoring and recording running condition and adjusting parameter of locomotive |
| CN102687123A (en) * | 2009-11-10 | 2012-09-19 | 飞思卡尔半导体公司 | Advanced communication controller unit and method for recording protocol events |
| CN103686439A (en) * | 2013-12-11 | 2014-03-26 | 深圳Tcl新技术有限公司 | Reporting method and device of television fault information |
| CN106485806A (en) * | 2016-09-27 | 2017-03-08 | 株洲中车时代电气股份有限公司 | A kind of locomotive integrated information tape deck and recording method |
| CN106502814A (en) * | 2016-10-19 | 2017-03-15 | 杭州迪普科技股份有限公司 | A kind of method and device of record PCIE device error message |
| CN107885134A (en) * | 2017-12-25 | 2018-04-06 | 成都实时技术股份有限公司 | A kind of fault data recorder method and device based on Aerial Electronic Equipment |
| CN108806209A (en) * | 2018-06-29 | 2018-11-13 | 重庆工商职业学院 | Intelligent alarm system for perceiving screen distance |
-
2020
- 2020-12-08 CN CN202011461903.1A patent/CN112579334B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050198546A1 (en) * | 2004-03-02 | 2005-09-08 | Matsushita Electric Industrial Co., Ltd. | Device and method for controlling an internal state of information processing equipment |
| CN101334667A (en) * | 2007-06-26 | 2008-12-31 | 株洲南车时代电气股份有限公司 | Locomotive status messages checking and diagnosis recording method and device |
| JP2010044622A (en) * | 2008-08-13 | 2010-02-25 | Hitachi Information & Communication Engineering Ltd | Information processor test program and method |
| CN102687123A (en) * | 2009-11-10 | 2012-09-19 | 飞思卡尔半导体公司 | Advanced communication controller unit and method for recording protocol events |
| CN102216909A (en) * | 2011-05-27 | 2011-10-12 | 华为技术有限公司 | A network processor and a diagnostic method of procedures stored in the network process |
| CN102566470A (en) * | 2012-01-11 | 2012-07-11 | 株洲南车时代电气股份有限公司 | System and method for timely monitoring and recording running condition and adjusting parameter of locomotive |
| CN103686439A (en) * | 2013-12-11 | 2014-03-26 | 深圳Tcl新技术有限公司 | Reporting method and device of television fault information |
| CN106485806A (en) * | 2016-09-27 | 2017-03-08 | 株洲中车时代电气股份有限公司 | A kind of locomotive integrated information tape deck and recording method |
| CN106502814A (en) * | 2016-10-19 | 2017-03-15 | 杭州迪普科技股份有限公司 | A kind of method and device of record PCIE device error message |
| CN107885134A (en) * | 2017-12-25 | 2018-04-06 | 成都实时技术股份有限公司 | A kind of fault data recorder method and device based on Aerial Electronic Equipment |
| CN108806209A (en) * | 2018-06-29 | 2018-11-13 | 重庆工商职业学院 | Intelligent alarm system for perceiving screen distance |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112579334B (en) | 2023-04-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11913990B2 (en) | Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program for handling command errors | |
| US20220252665A1 (en) | On-chip Debugging Device and Method | |
| CN108009065B (en) | Method and apparatus for monitoring AXI bus | |
| CN112148515B (en) | Fault positioning method, system, device, medium and equipment | |
| US7237151B2 (en) | Apparatus and method for trace stream identification of a processor reset | |
| KR20080022181A (en) | Mechanism for storing and extracting trace information using internal memory in microcontrollers | |
| US7930165B2 (en) | Procedure and device for emulating a programmable unit providing system integrity control | |
| US20150355673A1 (en) | Methods and systems with delayed execution of multiple processors | |
| CN116627877B (en) | On-chip bus state recording system and method | |
| CN112579334B (en) | Signal recording method and device for processor based on Ethernet | |
| US5276809A (en) | Method and apparatus for capturing real-time data bus cycles in a data processing system | |
| EP3961403A1 (en) | Bus monitoring device and method, storage medium, and electronic device | |
| EP1734537A2 (en) | Bitmap analysis system and method for high speed testing of a memory device | |
| US7210072B2 (en) | Apparatus and method for trace stream identification of a pipeline flattener primary code flush following initiation of an interrupt service routine | |
| US20040117717A1 (en) | Apparatus and method for a flush procedure in an interrupted trace stream | |
| US7225365B2 (en) | Apparatus and method for identification of a new secondary code start point following a return from a secondary code execution | |
| CN117591380B (en) | Bus performance monitoring method and device | |
| US20220334939A1 (en) | High-Frequency Event-Based Hardware Diagnostics | |
| US20230142759A1 (en) | Centrally logging and aggregating miscompares on chip during memory test | |
| US20230359537A1 (en) | High frequency event-based hardware diagnostics | |
| CN117880158A (en) | Method and device for testing serial communication protocol of communication equipment of Internet of things | |
| US7428666B2 (en) | Apparatus and method for trace stream identification of a pipeline flattener secondary code flush following a return to primary code execution | |
| CN116662189A (en) | Program testing method, device, equipment and storage medium | |
| US20040117701A1 (en) | Apparatus and method for identification of a primary code start sync point following a return to primary code execution | |
| US20050010909A1 (en) | Non-intrusive testing method for real-time software |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |