CN112534575A - 高压隔离组件的裂纹抑制结构 - Google Patents
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Abstract
一种集成电路(IC)(100)包括衬底(102),衬底(102)具有用于实现至少一个电路功能的功能电路(106),该功能电路与至少一个高压隔离组件一起配置,该高压隔离组件包括衬底(102)上方的顶部金属特征件(132)。至少包括抗裂电介质层的抗裂电介质结构(155)至少在顶部金属特征件(132)的顶部上。至少一个电介质钝化涂层(PO)层(160)在顶部金属特征件(132)的外部。
Description
技术领域
本公开总体涉及具有包括裂纹抑制结构的高压组件(诸如电容器或变压器)的集成电路(IC)器件的制造。
背景技术
一些IC包括高压(HV)隔离组件,例如电容器或变压器,其通常包括第一螺旋电感器和第二螺旋电感器,其中第一螺旋电感器起作用以磁激励第二螺旋电感器。高压隔离组件位于金属堆叠内的半导体表面上方,通常在(一个或多个)钝化层正下方的顶部金属层处具有顶部金属特征件。
化学机械抛光/平面化(CMP)是结合化学力和机械力使表面光滑的广泛使用的工艺。CMP工艺使用研磨性和腐蚀性化学浆以及通常比晶圆直径大的抛光垫和挡圈。该垫和晶圆由动态抛光头压在一起,并由挡圈固定在适当的位置。动态抛光头以不同的旋转轴旋转,从而去除晶圆表面的材料,并趋向于平整任何不规则的形貌,从而使晶圆平面化。
例如当CMP用于平坦化通常包括氧化硅(例如氧化硅上的氧氮化硅)的钝化层堆叠时,CMP可在被抛光的电介质层中产生裂纹。通常在氧化硅上执行CMP,然后沉积钝化堆叠的氧氮化硅部分。可以改变CMP工艺条件,以尽量减少此类氧化硅层裂纹的发生。
发明内容
提供本发明内容是为了以简化的形式介绍所公开的概念的简要选择,这些概念在包括所提供的附图的详细描述中在下面进一步描述。本发明内容并不旨在限制所要求保护的主题名称的范围。
公开的方面包括一种IC,其包括具有功能电路的衬底,该功能电路用于实现至少一个电路功能,该功能电路具有包括在衬底上方的顶部金属特征件的至少一个高压隔离组件。一种至少包括抗裂电介质层的裂纹抑制电介质结构,其在顶部金属特征件的至少顶部上。至少一个电介质钝化涂层(PO)层在顶部金属特征件的外部。
附图说明
现在将参考附图,附图不一定按比例绘制,其中:
图1A描绘具有高压隔离电容器(HV ISO电容器)的示例IC的一部分的横截面图,该HV ISO电容器包括在HV ISO电容器的顶板的顶部上的所公开的电介质裂纹抑制结构。
图1B描绘具有HV ISO电容器的示例IC的一部分的横截面图,该HV ISO电容器包括在顶板的顶部上和沿着HV ISO电容器的侧壁的所公开的电介质裂纹抑制结构。
图1C示出示例3层裂纹抑制结构。
图2A至图2F是根据示例方面的示出用于形成具有HV ISO电容器的IC的示例方法的处理过程的横截面图。
图2G是根据示例方面的示出用于形成具有HV变压器的IC的示例方法的HV ISO电容器的与图2F相对应的处理过程中的步骤的横截面图。
具体实施方式
参考附图描述示例方面,其中使用相似的附图标记来表示相似或等效的元件。因为某些行为或事件可能以不同的顺序发生和/或与其他行为或事件同时发生,因此行为或事件的图示顺序不应被视为限制性的。此外,可能不需要某些图示的行为或事件来实现根据本公开的方法。
此外,如本文所使用的术语“耦合到”或“与……耦合”(及诸如此类),无需进一步限定,旨在描述间接或直接电连接。因此,如果第一器件“耦合”到第二器件,则该连接可以通过路径中仅存在寄生体的直接电连接,或者通过经由包括其他器件和连接的中间项的间接电连接。对于间接耦合,中间项通常不修改信号的信息,但可以调整其电流电平、电压电平和/或功率电平。
虽然在某种程度上是有效的,但人们认识到,旨在减少电介质裂纹的CMP处理解决方案并不能在很大程度上消除由于CMP工艺造成的裂纹。本发明还认识到在CMP期间生成的电介质裂纹可以延伸到并终止于底层金属层,这可以导致器件故障或性能下降。当CMP后的稀氢氟酸(HF)清洁剂穿透钝化层中的电介质裂纹,从而侵蚀底层的顶部金属,在顶部金属中形成空洞时,就会出现器件故障的一个示例。这种空洞可以导致器件故障,包括现场故障(如可靠性故障)或IC性能下降。
本发明增加了一种电介质裂纹抑制结构,该结构包括在(一个或多个)钝化层和待裂纹保护的HV隔离组件的顶部金属层之间的抗裂电介质层,该抗裂电介质层显著降低了到达顶部金属的可导致IC故障或性能下降的电介质裂纹的发生率。HV隔离组件通常设计为能够承受至少100伏的电压。例如,抗裂电介质层可包括氮化硅(SiN)层,该氮化硅(SiN)层可在形成(一个或多个)钝化层之前沉积在顶部金属的顶部上,其起到止裂层的作用,以在(一个或多个)钝化层的CMP期间形成裂纹时保护HV隔离组件的顶部金属免受化学侵蚀。
图1A描绘具有HV ISO电容器104的示例IC 100的一部分的横截面图,该HV ISO电容器104包括所公开的电介质裂纹抑制结构155,该电介质裂纹抑制结构155通过示例示出为HV ISO电容器104的顶板132的顶部上的外部上的单个抗裂电介质层。电介质裂纹抑制结构155未示出在通过电介质钝化涂层(PO)层160打开的内窗口中,因为其在PO层160的蚀刻期间被移除。
电介质抗裂电介质层通常包括SiN,例如厚度为300至压缩应力为100至200MPa。抗裂电介质层还可以包括其它抗裂材料,例如SiC。电介质裂纹抑制结构155还可以包括2层或更多层,例如下面描述的图1C中所示的3层裂纹抑制结构,其中所示的抗裂电介质层155b位于顶层155c和底层155a之间。顶板132可以包括TiN、铝(Al)或TaN。HV ISO电容器104的底板如参考130所示。底板130可包括例如铝或铜或其合金。
IC 100可以作为IC的一部分或作为片上***(SOC)等提供。IC 100的其他配置(例如混合电路)在本示例的范围内。IC 100形成在诸如硅晶圆的衬底102上。HV ISO电容器104被配置为用于在具有不同电压电平的IC或***的两个电压域之间提供电流隔离。举例来说,可在约24伏特或更低电压下操作的,描绘为具有通常小于70纳米厚的栅极电介质层110的金属氧化物半导体(MOS)晶体管106的低压组件具有在其上的栅极电极113。MOS晶体管106是功能电路的一部分,该功能电路包括形成在衬底102中的被配置为与HV ISO电容器104一起实现诸如模拟(例如,放大器、功率转换器或功率场效应晶体管(FET))、射频、数字或记忆功能的至少一个电路功能的电路元件(包括晶体管,通常包括二极管、电阻器、电容器等)。
场氧化物(FOX)层或区域112可形成在衬底102中(例如,靠近或邻近衬底的顶表面)以横向电隔离IC 100的元件。在衬底102上方形成金属前电介质(PMD)层114,该衬底102包括在后续金属层(例如,金属层级118-1到118-N)沉积之前的任何FOX层或区域。填充通孔116可通过PMD层114设置以为诸如MOS晶体管106的低压组件以及微电子器件100A的其他组件或电路部分(图1A中未具体示出)提供电连接。
多个金属层级118-1(底部或“第一”金属层级)到118-N(顶部金属层级)设置在PMD层114上方,PMD层114可以包括被连接到MOS晶体管106以及任何附加组件、器件或电路部分的金属互连120。层级间电介质(ILD)层122a、122b、122c(例如,电介质材料或由二氧化硅基材料等组成的组合物)设置在每个金属层级中的金属互连120之间。各个通孔层级124设置在金属层级118-1到118-N之间,其中示例通孔层级124可以包括连接金属互连120的金属通孔126。在一种布置中,可以使用类似材料在类似工艺流程中形成各种电介质层。应当理解,用于ILD层122a、122b、122c的其他电介质材料,例如低电介质常数(к)材料,在本实施例的范围内,例如,FSG(к=3.6的氟化硅酸盐玻璃)、OSG(к=2.9的有机硅酸盐玻璃)和ULK(к=2.5的超低k电介质材料)。ILD层可以包括不同电介质材料(例如SiN)的盖层和蚀刻停止层。
HV ISO电容器104的底板130设置在金属层级的一个中,例如如图1A所描绘的第一金属层级118-1中。由顶部金属层级118-N形成的HV ISO电容器104的顶电极132在PO层160下方,例如另一个PO层156(例如PO硅氧化层,其被描绘为在ILD层122c上方)上的PO硅氧氮化物层。
在CMP之后的PO层156厚度通常为1.0到2.0μm,例如在顶部金属层118-N上方测量为1.5μm。PO层160通常为2.5μm到3.0μm,例如约为2.8μm并且包括氧氮化硅。由于单个PO层也是可能的,但是仅包括氧化硅的PO不能提供防潮层,并且当顶部金属层118-N包括铝时,仅包括氮化硅的PO可提供过大的应力。
HV ISO电容器104的底板130和顶板132竖直地设置在一起,以作为HV电容器来操作,例如,在IC 100的示例实施方式中,提供具有期望击穿特性的合适的电流隔离,根据某些实施例,具有高达10kV峰值的典型单电容器浪涌能力和高达17至24kV峰值的串联电容器(加强隔离)浪涌能力。
包括ILD层122a、122b和122c的HV ISO电容器104的电介质可以形成为具有至少2微米(μm)的总厚度,并且可以由HV ISO电容器104在其板130、132和可能的衬底102之间的期望操作电压来确定。例如,HV ISO电容器104的一个实施例,其中顶板132被设计为在750伏下操作,可以具有厚度为8μm到14μm的电容器电介质。
图1B描绘具有HV ISO电容器104’的示例IC 150的一部分的横截面图,该HV ISO电容器104’包括在顶板132的顶部上并沿着HV ISO电容器104’的侧壁的所公开的电介质裂纹抑制结构155’。与图1A中的HV ISO电容器104一样,电介质裂纹抑制结构155’不存在于通过PO层160打开的内窗口中,因为其在PO层160的蚀刻期间被移除。电介质裂纹抑制结构可以在顶部金属特征件的图案化和蚀刻之前沉积在顶部金属特征件(图1B中的顶板132)上。在这种情况下,可以使用单掩模,并且抗裂电介质层(例如,SiN)和顶部金属蚀刻通常将使用不同的化学物,并且裂纹抑制结构155’将仅在顶部金属特征件的顶部(如图1A所示)上。在顶部金属特征件的图案化和蚀刻之后,还可以沉积裂纹抑制电介质结构。在这种情况下,裂纹抑制电介质结构也被定位在顶部金属特征件的顶部上和其侧壁上以及金属特征件之间的层122c上方。
图1C示出示例3层裂纹抑制结构,示出为在底层155a上的抗裂电介质层155b上的顶层155c。3层裂纹抑制结构可包括用作粘附层155a的氧化硅层、用作裂纹抑制电介质层的抗裂电介质层155b的SiN,以及包括盖氧化物以提供用于金属图案化的亲水表面的层155c。一个特定示例3层电介质裂纹抑制结构堆叠包括作为50A氧化硅层的层155a、作为300至500A SiN层的抗裂电介质层155b以及作为50A氧化硅层的层155c。
图2A以横截面图图示在底板130的形成开始时所示的IC上的在制品HV ISO电容器的结构。图2A中描绘的是半导体衬底102,其上的处理层212表示在先前执行的常规半导体处理步骤中的前端处理期间形成的多个层、在处理层上的PMD层114和在PMD层114上的金属层级118-1。填充通孔116通过PMD层114形成。在最终的HV ISO电容器中,金属层级118-1将被图案化为底板130。在处理层212中,先前的处理步骤,例如光刻、蚀刻、离子注入和扩散,以在衬底102中形成各种器件(为简单起见未示出),并且可以将这些器件互连,例如包括MOS晶体管、双极晶体管或除MOS以外的FET的晶体管、二极管、电阻器、电感器、电容器等。
金属层级118-1例如可以是铝或铜或其合金,金属是在特定半导体制造工艺中使用的金属。单、双镶嵌铜或铜合金材料可用于形成金属层级118-1。然而,图2B至图2G示出使用可由铝金属层制成的非镶嵌金属层,该铝金属层与铜不同,可以直接蚀刻。
图2B示出在图案化金属层级118-1(包括形成HV ISO电容器的底板130,接着沉积且随后平坦化ILD层122a)之后的IC上的在制品HV ISO电容器。图2C示出在形成若干更多金属互连层级(包括在ILD层中形成填充通孔116,随后在其上形成图案化金属等)之后的IC上的在制品HV ISO电容器,若干更多金属互连层级如由ILD 122a、122b、122c分开的118-2、118-3所示。在底板130上方形成HV ISO电容器的区域中,仅存在电介质,如ILD层122a、122b和122c所示。提供底板130的金属层级如118-1所示。
图2D示出在形成和图案化包括顶板132的顶部金属层级118-4之后的IC上的在制品HV ISO电容器。图2E示出在顶板132的顶部和沿着HV ISO电容器的侧壁形成如抗裂电介质层155b所示的电介质裂纹抑制结构之后的IC上的在制品HV ISO电容器。用于电介质裂纹抑制结构的(一个或多个)电介质层可通过低压化学气相沉积(LPCVD)工艺沉积,例如等离子体增强CVD(PECVD)或高压沉积(HPD)。图2F示出在形成包括在抗裂电介质层155b上方的PO层160且随后用化学机械平坦化(CMP)进行平坦化之后的IC上的HV ISO电容器104”。
所示的裂纹291是从PO层160的表面(这可能是由于CMP处理)发出的,其停止在抗裂电介质层155b处。如上所述,在蚀刻PO层160期间,在通过PO层160打开的内窗口中通常移除抗裂电介质层155b或包括两层或更多层的电介质裂纹抑制结构的相应层。未示出的是在顶板132的一部分的上方蚀刻穿过PO层160的孔以使键合线与之键合。尽管未示出与底板130的接触,但通常通过金属互连120从底板上方延伸到附近的电路元件(例如数字转换器或调制器)来进行接触。与底板130的连接可以是输入节点,也可以是输出节点,这取决于HVISO电容器是在发射机信道中还是在接收机信道中。
图2G是示出根据示例方面的用于形成具有HV变压器250的IC的示例方法的HV ISO电容器的与图2F相对应的处理过程中的步骤的横截面图。HV变压器250包括顶电极132a、顶电感线圈133、底电极130a和底电感线圈133’。在磁传感器的情况下,仅有一个电感线圈需要在顶部。
所公开的方面可用于形成半导体管芯,该半导体管芯可集成到各种组装流中以形成各种不同的器件和相关产品。半导体管芯可包括其中的各种元件和/或其上的层,包括阻挡层、电介质层、器件结构、有源元件和无源元件,包括源极区、漏极区、位线、基极、发射极、集电极、导电线、导电通孔等。另外,半导体管芯可以由多种工艺形成,包括双极、绝缘栅双极晶体管(IGBT)、CMOS、BiCMOS和MEMS。
本公开所涉及领域的技术人员将了解,在所要求保护的发明的范围内许多其他方面是可能的,并且在不脱离本公开的范围的情况下可以对所描述的方面进行进一步的添加、删除、替换和修改。
Claims (18)
1.一种制造集成电路即IC的方法,其包括:
提供具有功能电路的衬底,所述功能电路用于实现至少一个电路功能,所述功能电路具有包括在所述衬底上方的顶部金属特征件的至少一个高压隔离组件;
在所述顶部金属特征件上沉积包括至少一个抗裂电介质层的裂纹抑制电介质结构;
图案化和蚀刻至少所述顶部金属特征件;
在所述顶部金属特征件的至少顶部上沉积至少一个电介质钝化涂层即电介质PO层,以及
平坦化所述电介质PO层。
2.根据权利要求1所述的方法,其中在图案化和蚀刻所述顶部金属特征件之前,所述裂纹抑制电介质结构沉积在所述顶部金属特征件上。
3.根据权利要求1所述的方法,其中在图案化和蚀刻所述顶部金属特征件之后,沉积所述裂纹抑制电介质结构,使得所述裂纹抑制电介质结构也定位在所述顶部金属特征件的侧壁上。
4.根据权利要求1所述的方法,其中所述裂纹抑制电介质层包括氮化硅层即SiN层或碳化硅层即SiC层。
5.根据权利要求4所述的方法,其中所述SiN层或所述SiC层的厚度为200至800A且压缩应力为50至500兆帕即Mpa。
6.根据权利要求1所述的方法,其中所述裂纹抑制电介质层包括通过等离子体增强化学气相沉积工艺沉积的氮化硅层即SiN层。
7.根据权利要求6所述的方法,其中沉积所述裂纹抑制电介质结构进一步包括在沉积所述SiN层之前沉积底部氧化硅层,以及在沉积所述SiN层之后沉积顶部氧化硅层。
8.根据权利要求1所述的方法,其中平坦化所述电介质PO层包括化学机械抛光即CMP。
9.根据权利要求1所述的方法,其中所述高压隔离组件包括高压电容器。
10.根据权利要求1所述的方法,其中所述高压隔离组件包括变压器,并且其中所述顶部金属特征件包括感应地耦合到外部定位电感线圈的顶电极。
11.根据权利要求1所述的方法,进一步包括通过所述电介质PO层和通过所述裂纹抑制电介质结构蚀刻开口以达到所述顶部金属特征件。
12.一种集成电路即IC,其包括:
衬底,其具有用于实现至少一个电路功能的功能电路,所述功能电路具有包括在所述衬底上方的顶部金属特征件的至少一个高压隔离组件;
裂纹抑制电介质结构,其至少包括在所述顶部金属特征件的至少顶部上的抗裂电介质层,以及
在所述顶部金属特征件的外部上的至少一个电介质钝化涂层即电介质PO层。
13.根据权利要求12所述的IC,其中所述裂纹抑制电介质结构也位于所述顶部金属特征件的侧壁上。
14.根据权利要求12所述的IC,其中所述抗裂电介质层包括氮化硅层即SiN层或碳化硅层即SiC层。
15.根据权利要求14所述的IC,其中所述SiN层或所述SiC层的厚度为200-800A且压缩应力为50至500兆帕即Mpa。
16.根据权利要求12所述的IC,其中所述裂纹抑制电介质层包括在顶部氧化硅层与底部氧化硅层之间的氮化硅层即SiN层。
17.根据权利要求12所述的IC,其中所述高压隔离组件包括高压电容器。
18.根据权利要求12所述的IC,其中所述高压隔离组件包括变压器,并且其中所述顶部金属特征件包括感应地耦合到外部定位电感线圈的顶电极。
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