CN112511157B

CN112511157B - Broadband prescaler

Info

Publication number: CN112511157B
Application number: CN202011624716.0A
Authority: CN
Inventors: 田彤; 伍锡安; 袁圣越
Original assignee: Maidui Microelectronic Technology Shanghai Co ltd
Current assignee: Maidui Microelectronic Technology Shanghai Co ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2024-05-17
Anticipated expiration: 2040-12-31
Also published as: CN112511157A

Abstract

The invention provides a broadband prescaler, which comprises a first data selector, a second data selector, a first NAND gate, a second NAND gate and a first trigger, wherein a frequency division trigger group is arranged between the first data selector and the second data selector; the first data selector is respectively connected with the frequency division trigger group and the first NAND gate; the first NAND gate and the second NAND gate are both connected with the first trigger; the second data selector is respectively connected with the frequency division trigger group and the second NAND gate; the second NAND gate is connected with the frequency division trigger group; the invention realizes the switching of frequency bands by adding two data selectors, thereby simplifying the complexity of the circuit, reducing the design difficulty of the circuit and effectively avoiding the reduction of the working speed of the circuit; different pre-frequency dividing ratios can be realized aiming at different frequency bands, the working frequency range of the broadband pre-frequency divider is greatly expanded, and the universality and the applicability of the broadband pre-frequency divider are greatly enhanced.

Description

Broadband prescaler

Technical Field

The invention relates to the field of electricity, in particular to a frequency division technology, and particularly relates to a broadband prescaler.

Background

The frequency divider is a key module in the frequency synthesizer and the clock generator, and has the main function of completing the frequency division function of the high-frequency signal, namely, realizing the conversion from the high-frequency signal to the low-frequency signal. The frequency divider is one of circuit modules with extremely high working speed, and meanwhile, the working frequency range of the frequency divider needs to be wide enough to meet the universality, while the prescaler is a module which is directly connected with a high-frequency signal in the frequency divider and can work in a high-speed and wide-frequency range, so that the key is that the frequency divider can work in a wide frequency range; in the development process of integrated circuits, the requirements on the working speed of the circuits are higher and higher, the working frequency range of input signals is wider and wider, the working frequency of the frequency divider is closely related to the circuit structure and the adopted process nodes, and is limited by the process nodes, so that the frequency divider is difficult to normally work in a wide input frequency range and realize the required frequency division ratio, and therefore, on the basis of not needing to redesign a rear-stage circuit, the problem that the rear-stage circuit still can work continuously in a wide frequency range even in the same frequency is solved, and the technical problem to be solved urgently by the technicians in the field is solved.

In order to solve the above problems, the currently adopted method generally realizes the multi-band function in the prescaler of the frequency divider, but the existing multi-band prescaler often realizes the switching of different frequency bands through a complex combinational logic circuit, on one hand, the complexity of the circuit is increased, the design difficulty of the circuit is increased, and more time cost is consumed; on the other hand, the increased logic gates on the critical signal links greatly reduce the operating speed of the circuit, which is not suitable for use in the high frequency domain, and thus reduces its applicability.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a wideband prescaler, which is used for solving the problems of complex circuit structure and high circuit design difficulty of the existing multi-band prescaler.

To achieve the above and other related objects, the present invention provides a wideband prescaler comprising: a first data selector, a second data selector, a first NAND gate, a second NAND gate and a first trigger, wherein a frequency division trigger group is arranged between the first data selector and the second data selector; the signal selection end of the first data selector is connected with a frequency band selection signal, the input end of the first data selector is connected with the frequency division trigger group, and the output end of the first data selector is connected with the first input end of the first NAND gate; the second input end of the first NAND gate is connected with a frequency division mode control signal, and the output end of the first NAND gate is connected with the first end of the first trigger; the second end of the first trigger is connected with an input signal, and the input signal is connected with the frequency division trigger group; the signal selection end of the second data selector is connected with the frequency band selection signal, the input end of the second data selector is connected with the frequency division trigger group, and the output end of the second data selector is connected with the first input end of the second NAND gate; the second input end of the second NAND gate is connected with the third end of the first trigger, and the output end of the second NAND gate is connected with the frequency division trigger group; according to the frequency of the input signal, selecting different frequency band selection signals to realize the control of the frequency band switching of the broadband prescaler, so that the broadband prescaler works in different frequency division ratio modes; when the broadband prescaler works in the same frequency division ratio mode, the broadband prescaler is controlled to work in different frequency division modes by accessing different frequency division mode control signals.

In an embodiment of the present invention, the frequency division flip-flop group includes: at least two second flip-flops; the number of second flip-flops determines the division ratio mode in which the wideband prescaler operates.

In an embodiment of the present invention, the number of ports at the input ends of the first data selector and the second data selector is equal, and is at least two, and the number of ports at the signal selection ends of the first data selector and the second data selector is equal, and is at least one.

In an embodiment of the present invention, the frequency division flip-flop group includes: four second triggers are respectively: the first trigger, the second trigger, the third trigger and the fourth trigger; the number of ports of the input ends of the first data selector and the second data selector is two, the first input end and the second input end are respectively provided, and the number of ports of the signal selection ends of the first data selector and the second data selector is one; the first end of the first trigger is connected with the output end of the second NAND gate, the second end of the first trigger is respectively connected with the second end of the second trigger, the second end of the third trigger, the second end of the fourth trigger and the second end of the first trigger, and the input signals are commonly accessed, and the third end of the first trigger is connected with the first end of the second trigger; the third end of the second trigger II is connected with the first end of the second trigger III and the first input end of the second data selector respectively, and the fourth end of the second trigger II is connected with the first input end of the first data selector; the third end of the third trigger is connected with the first end of the fourth trigger; the third end of the second trigger IV is connected with the second input end of the second data selector, and the fourth end of the second trigger IV is connected with the second input end of the first data selector; when the frequency band selection signal is at a low level, the broadband prescaler operates in a 4/5 frequency division ratio mode, and when the broadband prescaler operates in the 4/5 frequency division ratio mode, the broadband prescaler operates in a 4 frequency division mode when the frequency division mode control signal is at a low level; when the frequency division mode control signal is at a high level, the broadband prescaler works in a frequency division mode of 5; when the frequency band selection signal is at a high level, the broadband prescaler works in an 8/9 frequency division ratio mode, and when the broadband prescaler works in the 8/9 frequency division ratio mode, the broadband prescaler works in an 8 frequency division mode when the frequency division mode control signal is at a low level; when the frequency division mode control signal is at a high level, the broadband prescaler operates in a frequency division 9 mode.

In an embodiment of the present invention, further includes: a post-stage circuit; the back-end circuit is connected with the fourth end of the first trigger.

As described above, the wideband prescaler of the present invention has the following advantages:

(1) Compared with the prior art, the invention realizes the switching of the frequency bands by adding two data selectors, thereby simplifying the complexity of the circuit, reducing the design difficulty of the circuit and effectively avoiding the reduction of the working speed of the circuit.

(2) The invention can realize different pre-frequency dividing ratios aiming at different frequency bands, and greatly expands the working frequency range of the broadband pre-frequency divider, thereby effectively ensuring that a post-stage circuit can still work continuously under the condition of wide frequency range and even work under the same frequency, and greatly enhancing the universality and applicability of the broadband pre-frequency divider without considering the frequency range in which the trigger can work under different input frequencies of the trigger.

Drawings

Fig. 1 is a circuit diagram of a wideband prescaler according to an embodiment of the present invention.

Fig. 2 is an equivalent circuit diagram of the wideband prescaler of the present invention operating in a divide ratio by 4/5 mode in one embodiment.

Fig. 3 is an equivalent circuit diagram of the wideband prescaler of the present invention operating in 8/9 division ratio mode in one embodiment.

Description of the reference numerals

A 1-divide flip-flop group; 2-post-stage circuits.

Detailed Description

The following specific examples are presented to illustrate the present invention, and those skilled in the art will readily appreciate the additional advantages and capabilities of the present invention as disclosed herein. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the illustrations, not according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Compared with the prior art, the broadband prescaler realizes the switching of frequency bands by adding two data selectors, thereby simplifying the complexity of the circuit, reducing the design difficulty of the circuit and effectively avoiding the reduction of the working speed of the circuit; the invention can realize different pre-frequency dividing ratios aiming at different frequency bands, and greatly expands the working frequency range of the broadband pre-frequency divider, thereby effectively ensuring that a post-stage circuit can still work continuously under the condition of wide frequency range and even work under the same frequency, and greatly enhancing the universality and applicability of the broadband pre-frequency divider without considering the frequency range in which the trigger can work under different input frequencies of the trigger.

As shown in fig. 1, in an embodiment, the wideband prescaler of the present invention includes a first data selector MUX1, a second data selector MUX2, a first NAND gate NAND1, a second NAND gate NAND2, and a first flip-flop DFF, and a frequency division flip-flop group 1 is disposed between the first data selector MUX1 and the second data selector MUX 2.

Specifically, the signal selection end of the first data selector MUX1 is connected to the band selection signal SW, the input end of the first data selector MUX1 is connected to the frequency division trigger group 1, and the output end of the first data selector MUX1 is connected to the first input end ① of the first NAND gate NAND 1; the second input end ② of the first NAND gate NAND1 is connected to a frequency division mode control signal MC, and the output end ③ of the first NAND gate NAND1 is connected to the first end ① of the first flip-flop DFF; the second end ② of the first flip-flop DFF is connected to an input signal FIN, and the input signal FIN is connected to the frequency-dividing flip-flop group 1; the signal selection end of the second data selector MUX2 is connected to the frequency band selection signal SW, the input end of the second data selector MUX2 is connected to the frequency division trigger group 1, and the output end of the second data selector MUX2 is connected to the first input end ① of the second NAND gate NAND 2; the second input ② of the second NAND gate NAND2 is connected to the third terminal ③ of the first flip-flop DFF, and the output ③ of the second NAND gate NAND2 is connected to the frequency dividing flip-flop group 1.

It should be noted that, according to the frequency of the input signal FIN, different band selection signals SW are selectively connected to realize the control of the band switching of the wideband prescaler, so that the wideband prescaler operates in different frequency division ratio modes.

Further, when the wideband prescaler works in the same frequency division ratio mode, the wideband prescaler is controlled to work in different frequency division modes by accessing different frequency division mode control signals.

In one embodiment, the frequency-dividing flip-flop group 1 includes at least two second flip-flops.

It should be noted that the number of the second flip-flops determines the frequency division ratio mode in which the wideband prescaler operates.

In an embodiment, the number of ports at the input ends of the first data selector MUX1 and the second data selector MUX2 is equal and at least two, and the number of ports at the signal selection ends of the first data selector MUX1 and the second data selector MUX2 is equal and at least one.

It should be noted that, when the number of ports at the input ends of the first data selector MUX1 and the second data selector MUX2 is two, that is, the first data selector MUX1 and the second data selector MUX2 are both two data selectors, that is, one input signal is selected from the two input signals as the output signal thereof and is output, at this time, the number of ports at the signal selection ends of the first data selector MUX1 and the second data selector MUX2 is one, that is, when the band selection signal SW accessed by the signal selection end is high level 1, one input signal is selected as the output signal thereof and is output, and when the band selection signal SW accessed by the signal selection end is low level 0, the other input signal is selected as the output signal thereof and is output; similarly, when the number of ports at the input ends of the first data selector MUX1 and the second data selector MUX2 is three, that is, the first data selector MUX1 and the second data selector MUX2 are one-out-of-three data selectors, that is, one input signal is selected from three input signals to be output as an output signal thereof, at this time, the number of ports at the signal selection ends of the first data selector MUX1 and the second data selector MUX2 is two, that is, the signals input by the two ports at the signal selection end are taken as the band selection signal SW, and when the signals input by the two ports at the signal selection end are 00 (SW signal is 00), the first input signal of the three input signals is selected to be output as an output signal; when the signals input by the two ports of the signal selection end are 01 (SW signals are 01), selecting a second input signal of the three input signals as an output signal and outputting the output signal; when the signals input by two ports of the signal selection end are 10 (the SW signal is 10), selecting a third input signal of the three input signals as an output signal and outputting the third input signal; similarly, by selecting different data selectors and combining with the second flip-flop in the frequency division flip-flop group 1, the switching of the frequency band of the wideband prescaler can be realized so that the wideband prescaler operates in different frequency division ratio modes.

As shown in fig. 1, in an embodiment, the frequency-dividing flip-flop group 1 includes four second flip-flops, which are a second flip-flop one DFF1, a second flip-flop two DFF2, a second flip-flop three DFF3, and a second flip-flop four DFF4, respectively; the number of ports at the input ends of the first data selector MUX1 and the second data selector MUX2 is two, namely a first input end ① and a second input end ②, and the number of ports at the signal selection ends of the first data selector MUX1 and the second data selector MUX2 is one.

Specifically, the first end ① of the second flip-flop-DFF 1 is connected to the output end ③ of the second NAND gate NAND2, the second end ② of the second flip-flop-DFF 1 is connected to the second end ② of the second flip-flop-DFF 2, the second end ② of the second flip-flop-DFF 3, the second end ② of the second flip-flop-four DFF4 and the second end ② of the first flip-flop-DFF, respectively, and the input signal FIN is commonly connected to the third end ③ of the second flip-flop-DFF 1 is connected to the first end ① of the second flip-flop-two DFF 2; the third terminal ③ of the second flip-flop two DFF2 is connected to the first terminal ① of the second flip-flop three DFF3 and the first input terminal ① of the second data selector MUX2, respectively, and the fourth terminal ④ of the second flip-flop two DFF2 is connected to the first input terminal ① of the first data selector MUX 1; a third terminal ③ of the second flip-flop three DFF3 is connected to a first terminal ① of the second flip-flop four DFF 4; the third terminal ③ of the second flip-flop quad DFF4 is connected to the second input terminal ② of the second data selector MUX2, and the fourth terminal ④ of the second flip-flop quad DFF4 is connected to the second input terminal ② of the first data selector MUX 1.

It should be noted that the wideband prescaler includes the basic units of the 4/5 frequency divider and the 8/9 frequency divider at the same time, and two data selectors MUX1 and MUX2, which are two alternative ones, are used to select whether the wideband prescaler works at the 4/5 frequency divider or at the 8/9 frequency divider during actual operation; specifically, by setting the two signals SW and MC to 00, 01, 10, 11 for the wideband prescaler, frequency division by 4, 5, or frequency division by 8, 9 can be achieved; when the highest frequency of the input signal FIN is smaller, the 4/5 frequency dividing function of the broadband prescaler is adopted; when the highest frequency of the input signal FIN is larger, the 8/9 frequency dividing function of the broadband prescaler is adopted, so that after the broadband prescaler prescales, the following stage circuit can adopt the same unit without redesigning to adapt to the wide working frequency range of the input signal, the design difficulty of the circuit is greatly reduced, and the circuit structure is simplified.

For example, when an input signal of 500M-6G is input and the frequency range is 500M-3G, the broadband prescaler adopts 4/5 frequency division, and the frequency of the input signal obtained by the later stage is 750M or 600M at the highest; when the frequency range is 3G-6G, the broadband prescaler adopts 8/9 frequency division, and the frequency of the input signal of the later stage is 750M or 666M at the highest.

Further, by expanding on the basis of the broadband prescaler, other frequency division ratio circuits can be realized.

It should be noted that, when the frequency band selection signal SW is at a low level 0, the wideband prescaler operates in a 4/5 frequency division ratio mode, and when the wideband prescaler operates in the 4/5 frequency division ratio mode, the wideband prescaler operates in a4 frequency division mode when the frequency division mode control signal is at a low level 0; when the frequency division mode control signal is high level 1, the broadband prescaler works in a frequency division mode of 5.

Specifically, when the SW signal is 0, the first data selector MUX1 selects the QB2 signal output from the fourth terminal of the second flip-flop two DFF2 to the first input terminal ① of the first NAND gate NAND1, and the second data selector MUX2 selects the signal Q2 output from the third terminal of the second flip-flop two DFF2 and inputs it to the first input terminal ① of the second NAND gate NAND2, at this time, the wideband frequency divider operates in the divide-by-4/5 mode, and the circuit at this time is equivalent to that shown in fig. 2.

It should be noted that, the second flip-flop DFF1, the second flip-flop DFF2, the first flip-flop DFF, the first NAND gate NAND1, and the second NAND gate NAND2 constitute one 4/5 prescaler unit.

Further, if the MC signal is set to 0, then the wideband prescaler is now operating in divide-by-4 mode; if the MC signal is set to 1, then the wideband prescaler is operating in divide-by-5 mode.

It should be noted that, when the band selection signal SW is at a high level 1, the wideband prescaler operates in a divide-by-8/9 ratio mode, and when the wideband prescaler operates in the divide-by-8/9 ratio mode, the wideband prescaler operates in a divide-by-8 mode when the divide-by-frequency mode control signal is at a low level 0; when the frequency division mode control signal is high level 1, the broadband prescaler works in a frequency division 9 mode.

Specifically, when the SW signal is 1, the first data selector MUX1 selects the QB4 signal output from the fourth terminal of the second flip-flop quad DFF4 to the second input terminal ② of the first NAND gate NAND1, and the second data selector MUX2 selects the signal Q4 output from the third terminal of the second flip-flop quad DFF4 and inputs it to the second input terminal ② of the second NAND gate NAND2, at this time, the wideband frequency divider operates in the divide-by-8/9 mode, and the circuit at this time is equivalent to that shown in fig. 3.

It should be noted that, the second flip-flop DFF1, the second flip-flop DFF2, the second flip-flop DFF3, the second flip-flop DFF4, the first flip-flop DFF, the first NAND gate NAND1, and the second NAND gate NAND2 constitute one 8/9 prescaler unit.

Further, if the MC signal is set to 0, then the wideband prescaler is operated in divide-by-8 mode; if M C signal is set to 1, then the wideband prescaler is now operating in divide-by-9 mode.

The circuit description of the two modes, namely the 4/5 frequency division mode and the 8/9 frequency division mode, can easily find the easily-expanded characteristic of the broadband prescaler, namely the 4/5 or 8/9 multi-band prescaler designed in the embodiment can be changed into prescaler with other values, such as 8/9 or 16/17, 16/17 or 32/33, even 4/5 or 32/33, by changing the number of the triggers existing between two ends of the data selector; in addition, by changing the data selector of one of two to the data selector of one of three, three different sets of prescaler ratios can also be implemented, such as: the pre-frequency dividing ratio of 4/5, 8/9 or 16/17 can be realized, and the working frequency range of the broadband pre-frequency divider is further expanded; similarly, the structure provided by the broadband prescaler can conveniently realize different prescaler ratios according to the needs, and the easily-expanded characteristic greatly realizes the application range of the circuit of the invention, and can greatly reduce the time and cost of circuit design.

In one embodiment, the circuit further comprises a post-stage circuit 2.

Specifically, the post-stage circuit 2 is connected to the fourth terminal ④ of the first flip-flop DFF.

It should be noted that, by the design of the broadband prescaler circuit structure, the post-stage circuit 2 can still be ensured to continue to operate under the condition of wide frequency range without redesigning the post-stage circuit 2.

In summary, compared with the prior art, the broadband prescaler provided by the invention has the advantages that the switching of the frequency bands is realized by adding two data selectors, the complexity of a circuit is simplified, the design difficulty of the circuit is reduced, and the reduction of the working speed of the circuit is effectively avoided; the invention can realize different pre-frequency dividing ratios aiming at different frequency bands, greatly expands the working frequency range of the broadband pre-frequency divider, thereby effectively ensuring that a post-stage circuit can still work continuously under the condition of wide frequency range and even work under the same frequency, and greatly enhancing the universality and applicability of the broadband pre-frequency divider without considering the frequency range in which the trigger can work under different input frequencies of the trigger; therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A wideband prescaler, comprising: a first data selector, a second data selector, a first NAND gate, a second NAND gate and a first trigger, wherein a frequency division trigger group is arranged between the first data selector and the second data selector;

The signal selection end of the first data selector is connected with a frequency band selection signal, the input end of the first data selector is connected with the frequency division trigger group, and the output end of the first data selector is connected with the first input end of the first NAND gate;

the second input end of the first NAND gate is connected with a frequency division mode control signal, and the output end of the first NAND gate is connected with the first end of the first trigger;

The second end of the first trigger is connected with an input signal, and the input signal is connected with the frequency division trigger group;

the signal selection end of the second data selector is connected with the frequency band selection signal, the input end of the second data selector is connected with the frequency division trigger group, and the output end of the second data selector is connected with the first input end of the second NAND gate;

The second input end of the second NAND gate is connected with the third end of the first trigger, and the output end of the second NAND gate is connected with the frequency division trigger group;

according to the frequency of the input signal, selecting and accessing the frequency band selection signal to realize the frequency band switching of the broadband prescaler, so that the broadband prescaler works in an adaptive frequency division ratio mode;

when the broadband prescaler works in the same frequency division ratio mode, the broadband prescaler is controlled to work in the adaptive frequency division mode by accessing the frequency division mode control signal.

2. The wideband prescaler of claim 1, wherein the set of divide-by flip-flops comprises: at least two second flip-flops; the number of second flip-flops determines the division ratio mode in which the wideband prescaler operates.

3. The wideband prescaler of claim 2, wherein the number of ports at the input of the first data selector and the second data selector are equal and are each at least two, and the number of ports at the signal select ends of the first data selector and the second data selector are equal and are each at least one.

4. The wideband prescaler of claim 3, wherein the set of divide-by flip-flops comprises: four second triggers are respectively: the first trigger, the second trigger, the third trigger and the fourth trigger; the number of ports of the input ends of the first data selector and the second data selector is two, the first input end and the second input end are respectively provided, and the number of ports of the signal selection ends of the first data selector and the second data selector is one;

The first end of the first trigger is connected with the output end of the second NAND gate, the second end of the first trigger is respectively connected with the second end of the second trigger, the second end of the third trigger, the second end of the fourth trigger and the second end of the first trigger, and the input signals are commonly accessed, and the third end of the first trigger is connected with the first end of the second trigger;

the third end of the second trigger II is connected with the first end of the second trigger III and the first input end of the second data selector respectively, and the fourth end of the second trigger II is connected with the first input end of the first data selector;

The third end of the third trigger is connected with the first end of the fourth trigger;

The third end of the second trigger IV is connected with the second input end of the second data selector, and the fourth end of the second trigger IV is connected with the second input end of the first data selector;

When the frequency band selection signal is at a low level, the broadband prescaler operates in a 4/5 frequency division ratio mode, and when the broadband prescaler operates in the 4/5 frequency division ratio mode, the broadband prescaler operates in a 4 frequency division mode when the frequency division mode control signal is at a low level; when the frequency division mode control signal is at a high level, the broadband prescaler works in a frequency division mode of 5;

When the frequency band selection signal is at a high level, the broadband prescaler works in an 8/9 frequency division ratio mode, and when the broadband prescaler works in the 8/9 frequency division ratio mode, the broadband prescaler works in an 8 frequency division mode when the frequency division mode control signal is at a low level; when the frequency division mode control signal is at a high level, the broadband prescaler operates in a frequency division 9 mode.

5. The wideband prescaler of claim 1, further comprising: a post-stage circuit; the back-end circuit is connected with the fourth end of the first trigger.