CN111934671B - Multi-frequency-point frequency eliminator and control circuit - Google Patents
Multi-frequency-point frequency eliminator and control circuit Download PDFInfo
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- CN111934671B CN111934671B CN202010958059.7A CN202010958059A CN111934671B CN 111934671 B CN111934671 B CN 111934671B CN 202010958059 A CN202010958059 A CN 202010958059A CN 111934671 B CN111934671 B CN 111934671B
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Abstract
The invention relates to a multi-frequency-point frequency divider and a control circuit, wherein a shift register consists of N shift triggers which are connected, the shift trigger which is reset to 1 is used as a first shift trigger, the input end of a first OR gate is respectively connected with the output end of the first shift trigger and the output end of an nth shift trigger, the output end of the first OR gate is connected with the control end of a multi-path selector, the input end of a clock output register is connected with the output end of the multi-path selector, the signal end of the clock output register and the signal end of each shift trigger in the shift register are respectively connected with a clock signal to be divided, and the signal output end of the clock output register outputs a frequency division signal which divides the clock signal to be divided by 1/N. The frequency division of the clock signal to be subjected to frequency division with the frequency division coefficient being prime number is realized, and the timing problem of the high-speed clock is effectively avoided.
Description
Technical Field
The invention relates to the technical field of frequency removal, in particular to a multi-frequency-point frequency remover and a control circuit.
Background
In general, the frequency divider is mainly designed by a counter, and can be an up counter or a down counter. And (4) reversing the output of the frequency eliminator at a fixed counting point to finish the frequency eliminating function. The traditional frequency eliminator has simple logic and strong expandability, and only the bit width of a counter needs to be modified when the frequency eliminating range is adjusted.
In the design of a daily clock architecture, the chip clock frequency points have very many requirements, sometimes in order to meet the requirements of all clock frequency points in a chip and avoid increasing the chip area and power consumption, a common method is generally adopted to find a common frequency point of the clock frequency points, namely, a common multiple of the frequency points. When the frequency points are many, the frequency of the common frequency point may be very high, even reaching more than 2G. When the required number of frequency dividers becomes large, the critical path delay of the frequency divider also becomes large. When the frequency is very high, every time a bit is added to the counter, timing can not be met, that is, clock control can not meet the frequency requirement.
In order to solve the timing problem of the high-speed clock, a two-stage frequency division architecture is usually adopted for a commonly used frequency divider based on a counter structure. However, if the frequency division coefficient is prime, the frequency division circuit cannot be used, so that the timing problem of the high-speed clock cannot be solved.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a multi-frequency divider and a control circuit thereof, so as to overcome the problem that the timing problem of a high-speed clock can not be solved because a frequency dividing circuit cannot be adopted if the frequency dividing coefficient is a prime number.
In order to achieve the purpose, the invention adopts the following technical scheme:
a multi-frequency divider is applied to a circuit for dividing N frequency, and comprises:
a shift register; the shift register consists of N connected shift triggers, and the shift trigger reset to 1 is used as the first shift trigger;
a first OR gate; the input end of the first OR gate is respectively connected with the output end of the first shift trigger and the output end of the nth shift trigger; wherein N is a prime number;
a multiplexer; the output end of the first OR gate is connected with the control end of the multiplexer;
a clock output register; the input end of the clock output register is connected with the output end of the multiplexer, and the first output end of the clock output register and the second output end of the clock output register are respectively connected with the input end of the multiplexer; the signal end of the clock output register and the signal end of each shift trigger in the shift register are respectively connected with a clock signal to be subjected to frequency division; and the signal output end of the clock output register outputs a frequency division signal for carrying out 1/N frequency division on the clock signal to be subjected to frequency division.
Further, in the above multifrequency divider, if the output of the first or gate is 1, the multiplexer gates the second output of the clock output register and the input of the clock output register;
and if the output of the output end of the first OR gate is 0, the multiplexer gates the first output end of the clock output register and the input end of the clock output register.
Further, in the multi-frequency divider, the clock output register comprises a first clock flip-flop;
the frequency-divided signal comprises a first frequency-divided signal;
the Q end of the first clock flip-flop is used as the first output end of the clock output register, the end of the first clock flip-flop is used as the second output end of the clock output register, the D end of the first clock flip-flop is used as the input end of the clock output register, and the Clk end of the first clock flip-flop is used as the signal end of the clock output register;
and the Q end of the first clock trigger is used as the signal output end of the clock output register and outputs the first frequency division signal for carrying out 1/N frequency division on the clock signal to be subjected to frequency division.
Further, in the multi-frequency divider, a duty ratio of the first divided signal is less than 50%.
Further, in the multi-frequency divider, the first clock trigger is a D-flip-flop.
Further, in the multi-frequency divider, the clock output register includes a second clock flip-flop, a third clock flip-flop, and a second or gate;
the frequency divided signal comprises a second frequency divided signal;
the Q end of the second clock flip-flop is used as the first output end of the clock output register, the end of the second clock flip-flop is used as the second output end of the clock output register, the D end of the second clock flip-flop is used as the input end of the clock output register, and the Clk end of the second clock flip-flop and the Clk end of the third clock flip-flop are used as the signal ends of the clock output register;
the Q end of the second clock trigger is also connected with the D end of the third clock trigger;
the input end of the second or gate is respectively connected with the Q end of the second clock trigger and the Q end of the third clock trigger, and the output end of the second or gate is used as the signal output end of the clock output register to output the second frequency dividing signal for dividing the frequency of the clock signal to be divided by 1/N.
Further, in the multi-frequency divider described above, the duty ratio of the second frequency-divided signal is 50%.
Further, in the multi-frequency divider, the second clock flip-flop and the third clock flip-flop are D flip-flops.
Further, in the above multifrequency point frequency divider, the output terminal of each shift flip-flop is connected to the input terminal of the next shift flip-flop, and the input terminal of the first shift flip-flop is connected to the output terminal of the nth shift flip-flop.
The invention also provides a control circuit comprising the multi-frequency-point frequency divider.
The invention relates to a multi-frequency-point frequency divider and a control circuit, which comprise a shift register, a first OR gate, a multiplexer and a clock output register. The shift register is composed of N shift triggers which are connected with each other, the shift trigger which is reset to 1 is used as a first shift trigger, the input end of a first OR gate is respectively connected with the output end of the first shift trigger and the output end of an nth shift trigger, the output end of the first OR gate is connected with the control end of a multiplexer, the input end of a clock output register is connected with the output end of the multiplexer, the first output end of the clock output register and the second output end of the clock output register are respectively connected with the input end of the multiplexer, the signal end of the clock output register and the signal end of each shift trigger in the shift register are respectively connected with a clock signal to be subjected to frequency division, and the signal output end of the clock output register outputs a frequency division signal which is subjected to 1/N frequency division on the clock signal to be subjected to frequency division. The frequency division of the clock signal to be subjected to frequency division with the frequency division coefficient being prime number is realized, and the timing problem of the high-speed clock is effectively avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of a multi-frequency divider according to an embodiment of the present invention;
FIG. 2 is a waveform diagram of one embodiment of the multi-frequency divider of the present invention;
FIG. 3 is a circuit diagram of another embodiment of the multi-frequency divider of the present invention;
FIG. 4 is a waveform diagram provided by another embodiment of the multi-frequency divider of the present invention;
fig. 5 is a circuit diagram of another embodiment of the multi-frequency divider of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail below. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without any inventive step, are within the scope of the present invention.
The multi-frequency divider of the present embodiment is applied to a frequency-dividing circuit of N, where N is a prime number. Fig. 1 is a circuit diagram of a multi-frequency divider according to an embodiment of the present invention. As shown in fig. 1, the present embodiment exemplifies the operation principle and operation process of the multi-frequency divider by taking a three-frequency dividing circuit as an example.
It should be noted that the working principle and the working process of other frequency dividing circuits are the same as those of the embodiment shown in fig. 1, and those skilled in the art can obtain the working principle and the working process of other frequency dividing circuits according to fig. 1 without any creative premise, and are not described herein.
As shown in fig. 1, the multi-frequency divider of the present embodiment includes a shift register 1, a first or gate 2, a multiplexer 3, and a clock output register 4.
The shift register 1 is composed of N connected shift flip-flops, only one shift flip-flop in the shift register 1 is reset to 1, and the rest shift flip-flops are reset to 0. The D terminal of the shift flip-flop is an input terminal, the Q terminal of the shift flip-flop is an output terminal, the Clk terminal of the shift flip-flop is a signal terminal, the shift flip-flop reset to 1 is marked as S in fig. 1, and the shift flip-flop reset to 0 is marked as R in fig. 1.
Taking the shift trigger reset to 1 as a first shift trigger, connecting the Q end of the first shift trigger with the D end of the next shift trigger, connecting the Q end of the next shift trigger with the D end of the next shift trigger, and according to the rule, connecting the Q end of the (N-1) th shift trigger with the D end of the Nth shift trigger, and connecting the Q end of the Nth shift trigger with the D end of the first shift trigger.
As shown in fig. 1, the Q terminal of the first shift flip-flop of this embodiment is connected to the D terminal of the second shift flip-flop, the Q terminal of the second shift flip-flop is connected to the D terminal of the third shift flip-flop, and the Q terminal of the third shift flip-flop is connected to the D terminal of the first shift flip-flop.
Fig. 2 is a waveform diagram of a multi-frequency divider according to an embodiment of the present invention.
The reset of the first shift flip-flop is 1, and the reset of the second shift flip-flop and the reset of the third shift flip-flop are 0, then the waveform reg0_ Q output by the Q terminal of the first shift flip-flop, the waveform reg1_ Q output by the Q terminal of the second shift flip-flop, and the waveform reg2_ Q output by the Q terminal of the third shift flip-flop are as shown in fig. 2.
The input of the first or gate 2 is connected to the output of the first shift flip-flop and the output of the nth shift flip-flop, respectively, wherein,
. The output of the first or-gate 2 is connected to the control terminal of the multiplexer 3. As shown in fig. 1, in the present embodiment, the output terminal of the first shift flip-flop and the output terminal of the second shift flip-flop are both connected to the input terminal of the first or gate 2. The waveform trig en output by the output of the first or-gate 2 is as shown in fig. 2.
The input end of the clock output register 4 is connected with the output end of the multiplexer 3, and the first output end of the clock output register 4 and the second output end of the clock output register 4 are respectively connected with the input end of the multiplexer 3; the signal end of the clock output register 4 and the signal end of each shift trigger in the shift register 1 are respectively connected to a clock signal to be subjected to frequency division, and the signal output end of the clock output register outputs a frequency division signal for performing 1/N frequency division on the clock signal to be subjected to frequency division.
If the output of the output end of the first or gate 2 is 1, the multiplexer 3 gates the second output end of the clock output register 4 and the input end of the clock output register 4, and inputs the content output by the second output end of the clock output register 4 into the clock output register 4; if the output of the output terminal of the first or gate 2 is 0, the multiplexer 3 gates the first output terminal of the clock output register 4 and the input terminal of the clock output register 4, and inputs the content output from the first output terminal of the clock output register 4 into the clock output register 4.
In a specific embodiment, as shown in fig. 1, the clock output register 4 of the multi-frequency divider of the present embodiment includes a first clock flip-flop 41, and the first clock flip-flop 41 is a D flip-flop.
The Q terminal of the first clock flip-flop 41 serves as the first output terminal of the clock output register 4, of the first clock flip-flop 41
Terminals as second output terminals of the clock output register 4, i.e. terminal Q of the first clock flip-flop 41 and terminal Q of the first clock flip-flop 41
The terminals are connected to the input terminals of the multiplexer 3, respectively. The D terminal of the first clock flip-flop 41 serves as an input terminal of the clock output register 4, i.e., the D terminal of the first clock flip-flop 41 is connected to the output terminal of the multiplexer 3. The Clk terminal of the first clock flip-flop 41 serves as the signal terminal of the clock output register 4, i.e. the Clk terminal of the first clock flip-flop 41 receives the clock signal to be divided.
The multiplexer 3 gates the first clock flip-flop 41 if the output at the output of the first OR-gate 2 is 1
Terminal and D terminal of first clock flip-flop 41; if the output of the first or gate 2 is 0, the multiplexer 3 gates the Q terminal of the first clock flip-flop 41 and the D terminal of the first clock flip-flop 41.
And the Q end of the first clock trigger is used as the signal output end of the clock output register and outputs a first frequency division signal for carrying out 1/N frequency division on the clock signal to be subjected to frequency division. In this embodiment, the Q terminal of the first clock flip-flop 41 outputs a first frequency-divided signal clk _ div obtained by dividing the clock signal to be frequency-divided by 1/3, a waveform diagram of the first frequency-divided signal clk _ div is shown in fig. 2, the output first frequency-divided signal clk _ div is 1/3% of the input clock signal to be frequency-divided, and the duty ratio is within 50%.
It should be noted that this embodiment can also be applied to a non-prime number frequency division circuit, where N = N/2 when the frequency division number is an even number, and when the frequency division number is an odd number of the non-prime number,
。
the multi-frequency divider of the present embodiment includes a shift register 1, a first or gate 2, a multiplexer 3, and a clock output register 4. The shift register 1 is composed of N shift triggers connected with each other, the shift trigger reset to 1 is used as a first shift trigger, the input end of a first OR gate 2 is respectively connected with the output end of the first shift trigger and the output end of an nth shift trigger, the output end of the first OR gate 2 is connected with the control end of a multiplexer 3, the input end of a clock output register 4 is connected with the output end of the multiplexer 3, the first output end of the clock output register 4 and the second output end of the clock output register 4 are respectively connected with the input end of the multiplexer 3, the signal end of the clock output register 4 and the signal end of each shift trigger in the shift register 1 are respectively connected with a clock signal to be subjected to frequency division, and the signal output end of the clock output register 4 outputs a frequency division signal for performing frequency division of the clock signal to be subjected to frequency division by 1/N. The frequency division of the clock signal to be subjected to frequency division with the frequency division coefficient being prime number is realized, and the timing problem of the high-speed clock is effectively avoided.
It should be noted that the duty ratio of the first frequency-divided signal clk _ div in the above embodiment is less than 50%. The scheme provides another embodiment to realize the generation of the clock signal with the duty ratio of 50%.
Fig. 3 is a circuit diagram of another embodiment of the multi-frequency divider of the present invention. As shown in fig. 3, the present embodiment also uses a three-frequency-division circuit as an example to illustrate the operation principle and the operation process of the multi-frequency-point frequency divider.
It should also be noted that the working principle and the working process of other frequency dividing circuits are the same as those of the embodiment shown in fig. 3, and those skilled in the art can obtain the working principle and the working process of other frequency dividing circuits according to fig. 3 without any creative premise, and details are not described here.
In addition, in the present embodiment, the connection manner and the working principle of the shift register 1, the first or gate 2 and the multiplexer 3 are the same as those in the previous embodiment, and a person skilled in the present embodiment may refer to the previous embodiment, which is not described herein again.
The clock output register 4 of the present embodiment comprises a second clock flip-flop 42, a third clock flip-flop 43 and a second or gate 44. The second clock flip-flop 42 and the third clock flip-flop 43 are both D flip-flops.
The Q terminal of the second clock flip-flop 42 being the first output terminal of the clock output register 4, the Q terminal of the second clock flip-flop 42
Terminals as second output terminal of the clock output register 4, i.e. terminal Q of the second clock flip-flop 42 and terminal Q of the second clock flip-flop 42
The terminals are connected to the input terminals of the multiplexer 3, respectively. The D terminal of the second clock flip-flop 42 serves as an input terminal of the clock output register 4, i.e. the D terminal of the second clock flip-flop 42Connected to the output of the multiplexer 3. Clk terminal of second clock flip-flop 42 and of third clock flip-flop 43
With terminals as signal terminals of the clocked output register 4, i.e. the Clk terminal of the second clock flip-flop 42 and the Clk terminal of the third clock flip-flop 43
The terminals are respectively connected with clock signals to be divided.
The multiplexer 3 gates the second clocked flip-flop 42 if the output at the output of the first or-gate 2 is 1
Terminal and D terminal of second clock flip-flop 42; if the output of the first or gate 2 is 0, the multiplexer 3 gates the Q terminal of the second clock flip-flop 42 and the D terminal of the second clock flip-flop 42.
Fig. 4 is a waveform diagram of another embodiment of the multi-frequency divider of the present invention.
The waveform clk _ neg output at the Q terminal of the third clocked flip-flop 43 is as shown in fig. 3.
The Q terminal of the second clock flip-flop 42 is further connected to the D terminal of the third clock flip-flop 43, the input terminals of the second or gate 44 are respectively connected to the Q terminal of the second clock flip-flop 42 and the Q terminal of the third clock flip-flop 43, and the output terminal of the second or gate 44 serves as the clock output register signal output terminal to output a second frequency-divided signal obtained by frequency-dividing the clock signal to be frequency-divided by 1/N. In this embodiment, the output end of the second or gate 44 outputs a second frequency-divided signal clk _ out obtained by dividing the clock signal to be frequency-divided by 1/3, the waveform of the second frequency-divided signal clk _ out is shown in fig. 4, the output second frequency-divided signal clk _ out is 1/3 of the input clock signal to be frequency-divided, and the duty ratio is 50%.
For any prime number N frequency division circuit, the critical path delays (critical path delays) are Dck2q + Dor + Dsel2z + Dsetup;
wherein:
dck2Q is CK-TO-Q delay of the shift register, i.e., the delay from the Clk terminal of the shift flip-flop TO the Q terminal of the shift flip-flop;
dor is the in-to-out delay of or gate, i.e., the delay from the input of the OR gate to the output of the OR gate;
dsel2z is the sel-to-z delay of mux, i.e., the delay from the input of the multiplexer to the output of the multiplexer;
dsetup is the setup time of the shift register.
Therefore, the critical path delay of the circuit cannot increase along with the increase of the frequency dividing coefficient, so that the sign-off frequency point is reduced, and the circuit is more suitable for scenes which need high speed and have large frequency dividing coefficients.
It should be noted that this embodiment can also be applied to a non-prime number frequency division circuit, where N = N/2 when the frequency division number is an even number, and when the frequency division number is an odd number of the non-prime number,
。
the multi-frequency-point frequency divider realizes frequency division of a clock signal to be divided with a frequency division coefficient being prime number, and effectively avoids timing problem of a high-speed clock.
Fig. 5 is a circuit diagram of another embodiment of the multi-frequency divider of the present invention. As shown in fig. 5, in a specific embodiment, the Clk _ in clock frequency is 2.4G, the Clk _ out needs to have clock frequency points of 800M, 480M, and 343M, a frequency divider circuit of 3/5/7 can be separately built, and the Clk glich-free mux is used as a clock switching circuit.
The invention also provides a control circuit which comprises the multi-frequency-point frequency eliminator of the embodiment. The control circuit of the embodiment realizes frequency division of the clock signal to be divided with the frequency division coefficient being prime number, and effectively avoids timing problem of the high-speed clock.
For a specific implementation of the control circuit provided in the embodiment of the present application, reference may be made to the implementation of the multi-frequency divider in any of the above embodiments, and details are not described here.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (8)
1. A multi-frequency divider, for use in a divide-by-N circuit, comprising:
a shift register; the shift register consists of N connected shift triggers, and the shift trigger reset to 1 is used as the first shift trigger;
a first OR gate; the input end of the first OR gate is respectively connected with the output end of the first shift trigger and the output end of the nth shift trigger; wherein, N is a prime number,
；
a multiplexer; the output end of the first OR gate is connected with the control end of the multiplexer;
a clock output register; the input end of the clock output register is connected with the output end of the multiplexer, and the first output end of the clock output register and the second output end of the clock output register are respectively connected with the input end of the multiplexer; the signal end of the clock output register and the signal end of each shift trigger in the shift register are respectively connected with a clock signal to be subjected to frequency division; the signal output end of the clock output register outputs a frequency division signal for carrying out 1/N frequency division on the clock signal to be subjected to frequency division;
wherein the clock output register comprises a first clock flip-flop; the frequency-divided signal comprises a first frequency-divided signal; the Q end of the first clock trigger is used as the first output end of the clock output register, and the Q end of the first clock trigger is used as the first output end of the clock output register
The end is used as a second output end of the clock output register, the D end of the first clock trigger is used as an input end of the clock output register, and the Clk end of the first clock trigger is used as a signal end of the clock output register; the Q end of the first clock trigger is used as the signal output end of the clock output register and outputs the first frequency division signal for carrying out 1/N frequency division on the clock signal to be subjected to frequency division; or
The clock output register comprises a second clock trigger, a third clock trigger and a second OR gate; the frequency divided signal comprises a second frequency divided signal; the Q end of the second clock trigger is used as the first output end of the clock output register, and the Q end of the second clock trigger is used as the first output end of the clock output register
The end is used as the second output end of the clock output register, the D end of the second clock trigger is used as the input end of the clock output register, the Clk end of the second clock trigger and the Clk end of the third clock triggerAs the signal end of the clock output register; the Q end of the second clock trigger is also connected with the D end of the third clock trigger; the input end of the second or gate is respectively connected with the Q end of the second clock trigger and the Q end of the third clock trigger, and the output end of the second or gate is used as the signal output end of the clock output register to output the second frequency dividing signal for dividing the frequency of the clock signal to be divided by 1/N.
2. The multiple frequency divider of claim 1, wherein the multiplexer gates the second output of the clocked output register and the input of the clocked output register if the output of the first or gate is 1;
and if the output of the output end of the first OR gate is 0, the multiplexer gates the first output end of the clock output register and the input end of the clock output register.
3. The multi-frequency divider of claim 1, wherein a duty cycle of the first divided signal is less than 50%.
4. The multiple frequency divider of claim 1, wherein the first clock flip-flop is a D flip-flop.
5. The multi-frequency divider of claim 1, wherein the second divided signal has a duty cycle of 50%.
6. The multiple frequency divider of claim 1, wherein the second clock flip-flop and the third clock flip-flop are both D flip-flops.
7. The multi-frequency divider of claim 1, wherein an output of each shift flip-flop is connected to an input of a subsequent shift flip-flop, and wherein an input of the first shift flip-flop is connected to an output of an nth shift flip-flop.
8. A control circuit comprising the multi-frequency divider of any one of claims 1-7.
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