CN112506087A - FPGA acceleration system and method, electronic device, and computer-readable storage medium - Google Patents
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Abstract
The embodiment of the invention provides an FPGA (field programmable gate array) acceleration system and method, electronic equipment and a computer readable storage medium. In the system, a control module and a plurality of execution modules for executing different operations are arranged in an FPGA, wherein the control module is used for analyzing a received instruction and generating scheduling information, and the scheduling information comprises an execution module required to execute the instruction and an operation sequence of the execution module; the execution module is used for executing operation according to the scheduling information generated by the control module. The embodiment of the invention controls and schedules each execution module in the FPGA to execute the operation by analyzing the received instruction so as to flexibly realize acceleration.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to an FPGA acceleration system and method, an electronic device, and a computer-readable storage medium.
Background
As a Programmable logic device, a Field-Programmable Gate Array (FPGA) can be reconfigured to various required functions because it can be reprogrammed according to different needs after being manufactured. In the prior art, by utilizing such characteristics of the FPGA, a complex SQL instruction can be executed by each IP core (i.e., execution module), thereby accelerating the database.
When using an FPGA for database acceleration, acceleration of different functions such as compression, decompression, filtering, projection, hashing, etc. can be provided by setting different IP cores (i.e., execution modules) in the FPGA.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems: in the prior art, for different SQL instructions, different execution modules need to be configured and different processes need to be executed by the FPGA, and thus various functions cannot be flexibly implemented.
Disclosure of Invention
The embodiment of the invention provides an FPGA (field programmable gate array) acceleration system and method, electronic equipment and a computer readable storage medium, aiming at solving the defects of inflexible function realization and low system performance in the prior art.
In order to achieve the above object, an embodiment of the present invention provides an FPGA acceleration system, in which a control module and a plurality of execution modules for executing different operations are disposed inside an FPGA,
the control module is used for analyzing the received instruction and generating scheduling information, wherein the scheduling information comprises an execution module required to execute the instruction and an operation sequence of the execution module;
the execution module is used for executing operation according to the scheduling information generated by the control module.
The embodiment of the invention also provides an FPGA acceleration method, wherein a plurality of execution modules for executing different operations are arranged in the FPGA, and the method comprises the following steps:
analyzing a received instruction to generate scheduling information, wherein the scheduling information comprises an execution module required to execute the instruction and an operation sequence of the execution module;
and controlling the execution module to execute the operation according to the scheduling information.
The embodiment of the present invention further provides an electronic device, which is used for an FPGA acceleration system, wherein a plurality of execution modules for executing different operations are arranged inside an FPGA, and the electronic device includes:
a memory for storing a program;
a processor for executing the program stored in the memory for:
analyzing a received instruction to generate scheduling information, wherein the scheduling information comprises an execution module required to execute the instruction and an operation sequence of the execution module;
and controlling the execution module to execute the operation according to the scheduling information.
The embodiment of the present invention further provides a computer-readable storage medium, which is used for an FPGA acceleration system, wherein a plurality of execution modules for executing different operations are arranged inside the FPGA, a computer program is stored on the computer-readable storage medium, and when being executed by a processor, the computer program implements:
analyzing a received instruction to generate scheduling information, wherein the scheduling information comprises an execution module required to execute the instruction and an operation sequence of the execution module;
and controlling the execution module to execute the operation according to the scheduling information.
The FPGA acceleration system and method, the electronic device and the computer readable storage medium provided by the embodiment of the invention control and schedule each execution module in the FPGA to execute the operation by analyzing the received instruction so as to flexibly realize acceleration.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a system block diagram of an embodiment of an FPGA acceleration system provided by the present invention;
FIG. 2 is a system block diagram of another embodiment of an FPGA acceleration system provided by the present invention;
FIG. 3 is a system block diagram of an embodiment of an FPGA acceleration system provided by the present invention;
FIG. 4 is a flowchart of an embodiment of an FPGA acceleration method provided by the present invention;
FIG. 5 is a flowchart of another embodiment of an FPGA acceleration method provided by the present invention;
fig. 6 is a schematic structural diagram of an embodiment of an electronic device provided in the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the prior art, the acceleration of the database can be implemented by different execution modules (IP cores) provided in the FPGA. However, for SQL instructions generated by the CPU, the FPGA needs to configure different execution modules and execute different processes, and thus cannot flexibly implement various functions.
Aiming at the defects of the prior art, the application provides an FPGA acceleration scheme, and the main principle is as follows: the FPGA is provided with a control module, and the control module is used for analyzing the instruction generated by the CPU so as to analyze an execution module required for executing the instruction and an execution sequence of each execution module, so that each execution module is controlled and scheduled according to an analysis result to execute the instruction, and the acceleration of the database is realized.
The above embodiments are illustrations of technical principles of the embodiments of the present invention, and specific technical solutions of the embodiments of the present invention are further described in detail below by using a plurality of embodiments.
Example one
Fig. 1 is a system block diagram of an embodiment of an FPGA acceleration system provided in the present invention. As shown in fig. 1, in the FPGA acceleration system provided in the embodiment of the present invention, a control module 11 and a plurality of execution modules 13 for executing different operations are arranged inside an FPGA.
The control module 11 is configured to analyze a received instruction and generate scheduling information, where the scheduling information includes execution modules that need to be scheduled to execute the instruction and operation sequences of the execution modules; the execution module 13 is configured to execute an operation according to the scheduling information generated by the control module 11.
In the embodiment of the present invention, when the FPGA is used in a database acceleration scenario, the FPGA may be set on a computing node in the database, and the control module 11 may be set inside the FPGA, for example, a microprocessor may be set inside the FPGA, and a monitor (monitor) responsible for controlling and scheduling each execution module may be run on the microprocessor. When the CPU of the compute node generates an instruction, the control module 11 analyzes the instruction to generate scheduling information for scheduling the execution module in the FPGA. Specifically, the scheduling information may include information of execution modules required to be scheduled to execute the instruction and an operation sequence of the execution modules to perform respective operations. In addition, the CPU sends the target data processed by the instruction to a memory module (e.g., DDR DRAM)12 of the FPGA for storage. Under the control of the control module 11, the relevant execution module 13 reads data from the storage module 12 and executes the respective operations in the order of operations in the schedule information.
According to the FPGA acceleration system provided by the embodiment of the invention, the control module is arranged in the FPGA to analyze the received instruction, so that each execution module in the FPGA is controlled and scheduled to execute the operation, and the acceleration of the database can be flexibly realized.
Example two
Fig. 2 is a system block diagram of another embodiment of the FPGA acceleration system provided in the present invention. As shown in fig. 2, on the basis of the embodiment shown in fig. 1, the storage module 12 may also be configured to store intermediate data generated by the execution module 13 executing the operation.
In the embodiment of the invention, in the Host (Host), the CPU is respectively connected with the Memory (Memory) and the Storage (Storage). The interface of the FPGA is connected with the CPU through a PCIE bus. In the FPGA, each execution module 13 executes operations according to the scheduling information under the control of the control module 11, and intermediate data (i.e., input and output data of each execution module) generated in the execution process can be stored in the storage module 12 arranged inside the FPGA, so as to reduce data interaction between the FPGA and the CPU, reduce participation of the CPU, and improve system performance.
Specifically, in the embodiment of the present invention, each execution module 13 may establish a corresponding memory pool (memory pool) on the storage module 12, and the control module 11 manages the memory pools through a linked list. Index numbers can be set for the data stored in the storage module 12, and each execution module 13 can call the relevant data through the index numbers to avoid data migration between the execution modules 13.
Further, the control module 11 may be further configured to query a pre-stored correspondence table between a plurality of instructions and the scheduling information, and obtain the scheduling information corresponding to the received instruction.
In the embodiment of the present invention, a correspondence table between a plurality of different instructions and different scheduling information may be stored in advance, and in the correspondence table, the different instructions correspond to different execution sequences of the execution modules. After receiving the instruction, the control module 11 may query the corresponding relationship table to obtain scheduling information corresponding to the received instruction. And acquiring the execution sequence of the corresponding execution module by matching the instructions.
Furthermore, the FPGA acceleration system provided in the embodiment of the present invention may further include a communication module. The communication module is arranged in the FPGA and can be used for transmitting instructions and data with a host.
In addition, the communication module may adopt a Remote Procedure Call (RPC) protocol for communication, and implement direct processing of a Remote SQL instruction through communication across servers (computing nodes) to implement computing resource sharing.
The FPGA acceleration system provided by the embodiment of the invention controls and schedules each execution module in the FPGA to execute the operation by analyzing the received instruction so as to flexibly realize acceleration; in addition, intermediate data generated by each execution module in the execution process is stored in the FPGA, so that the participation of a CPU is reduced, and the system new energy is improved; meanwhile, the processing of the remote instruction is realized by arranging the communication module with the remote process calling function, so that the sharing of computing resources is realized.
EXAMPLE III
Fig. 3 is a system block diagram of an embodiment of an FPGA acceleration system provided in the present invention. As shown in fig. 3, in the embodiment of the present invention, the FPGA is connected to the Host (Host) through the PCIE bus. Based on the improvement of the FPGA performance and the development of the chip process, the current FPGA has the capability of independently completing the processing of the complex SQL instruction, and therefore, a plurality of IP cores, such as execution modules of compression, decompression, filtering (filter), aggregation (aggr), hash (hash), sorting (sort), grouping (group by), table join (join), projection (proj), and the like, may be disposed in the FPGA, and a microprocessor capable of controlling and scheduling each execution module is disposed.
When the host generates control information, the control information is sent to the microprocessor in the FPGA through the PCIE, and the microprocessor analyzes the control information to generate scheduling information for scheduling each execution module. Specifically, the scheduling information may include information of execution modules that need to be scheduled to execute the control information and an operation sequence for the execution modules to execute respective operations, so that the SQL instruction is executed optimally.
In addition, in order to minimize data interaction between the host and the FPGA, the host may store all data input or output by each execution module in the DDR DRAM in the FPGA. Under the control of the microprocessor, the relevant execution module reads data from the DDR DRAM and executes the respective operations according to the operation sequence in the scheduling information.
Specifically, in the embodiment of the present invention, each execution module may establish a corresponding memory pool (memory pool) on the DDR DRAM, and manage the memory pools by a linked list. Index numbers can be set for data stored in the DDR DRAM, and each execution module can call related data through the index numbers so as to avoid data migration among the execution modules.
In the embodiment of the invention, the microprocessor can set two modes, namely a matching mode and a calculating mode. Under the matching mode, the microprocessor prestores SQL instructions which can be supported, processes the matched SQL instructions, and transmits specific processing instructions to each execution module; in the computing mode, the complex SQL instruction requires the microprocessor to issue a control instruction according to the intermediate result and control the execution sequence of each execution module.
According to the FPGA acceleration system provided by the embodiment of the invention, the microprocessor is arranged in the FPGA to analyze the received control information, so that each execution module in the FPGA is controlled and scheduled to execute the operation, and the database acceleration of the host can be flexibly realized.
Example four
Fig. 4 is a flowchart of an embodiment of the FPGA acceleration method provided in the present invention, and an execution subject of the method may be the FPGA acceleration system, or may be a device or a chip integrated on the system. As shown in fig. 4, the FPGA acceleration method provided in the embodiment of the present invention includes the following steps:
s301, analyzing the received command to generate scheduling information.
In the embodiment of the invention, when the FPGA is used in a database acceleration scene, the FPGA can be set on a computation node in the database, and a plurality of execution modules for executing different operations are arranged inside the FPGA. When the CPU of a compute node generates an instruction, the instruction may be analyzed to generate scheduling information for scheduling execution modules in the FPGA. Specifically, the scheduling information includes an execution module and an operation sequence of the execution module, which are required to be scheduled to execute the instruction.
And S302, controlling the execution module to execute the operation according to the scheduling information.
In the embodiment of the invention, the CPU sends the target data processed by the instruction to an FPGA (such as a DDR DRAM) for storage. And the related execution module reads the related data according to the scheduling information and executes respective operations according to the operation sequence in the scheduling information.
According to the FPGA acceleration method provided by the embodiment of the invention, the received instruction is analyzed to control and schedule each execution module in the FPGA to execute the operation, so that the acceleration of the database can be flexibly realized.
EXAMPLE five
Fig. 5 is a flowchart of another embodiment of the FPGA acceleration method provided in the present invention. As shown in fig. 5, on the basis of the embodiment shown in fig. 4, the FPGA acceleration method provided in this embodiment may further include the following steps:
s401, inquiring a corresponding relation table of a plurality of prestored instructions and scheduling information, and acquiring scheduling information corresponding to the received instructions.
In the embodiment of the present invention, a correspondence table between a plurality of different instructions and different scheduling information may be stored in advance, and in the correspondence table, the different instructions correspond to different execution sequences of the execution modules. After receiving the instruction, the corresponding relation table may be queried to obtain scheduling information corresponding to the received instruction. And acquiring the execution sequence of the corresponding execution module by matching the instructions.
S402, controlling the execution module to execute the operation according to the scheduling information.
In the embodiment of the invention, each execution module executes operation according to the scheduling information, and intermediate data (namely, input and output data of each execution module) generated in the execution process can be stored in the FPGA, so that the data interaction of the FPGA on the CPU is reduced, the participation of the CPU is reduced, and the system new energy is improved.
Specifically, in the embodiment of the present invention, each execution module may establish a corresponding memory pool (memory pool) on a DDR DRAM of the FPGA, and manage the memory pools by a linked list. Index numbers can be set for data stored in the DDR DRAM, and each execution module can call related data through the index numbers so as to avoid data migration among the execution modules.
In addition, in real time, the invention can also adopt RPC protocol to communicate with the host, and realize the direct processing of the remote SQL instruction through the communication of the cross server (computing node), so as to realize the sharing of computing resources.
According to the FPGA acceleration method provided by the embodiment of the invention, the received instruction is analyzed to control and schedule each execution module in the FPGA to execute the operation, so that the acceleration is flexibly realized; in addition, intermediate data generated by each execution module in the execution process is stored in the FPGA, so that the participation of a CPU is reduced, and the system new energy is improved; meanwhile, the remote instruction is processed by adopting a remote procedure call protocol, so that the sharing of computing resources is realized.
EXAMPLE six
The internal functions and structures of the FPGA acceleration are described above, and the system can be implemented as an electronic device in which a plurality of execution modules for executing different operations are provided. Fig. 6 is a schematic structural diagram of an embodiment of an electronic device provided in the present invention. As shown in fig. 6, the electronic device includes a memory 51 and a processor 52.
The memory 51 stores programs. In addition to the above-described programs, the memory 51 may also be configured to store other various data to support operations on the electronic device. Examples of such data include instructions for any application or method operating on the electronic device, contact data, phonebook data, messages, pictures, videos, and so forth.
The memory 51 may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
A processor 52, coupled to the memory 51, for executing programs stored in the memory 51 for:
analyzing the received instruction to generate scheduling information, wherein the scheduling information comprises execution modules required to execute the instruction and operation sequences of the execution modules;
and controlling the execution module to execute the operation according to the scheduling information.
Further, as shown in fig. 6, the electronic device may further include: communication components 53, power components 54, audio components 55, display 56, and other components. Only some of the components are schematically shown in fig. 6, and the electronic device is not meant to include only the components shown in fig. 6.
The communication component 53 is configured to facilitate wired or wireless communication between the electronic device and other devices. The electronic device may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 53 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 53 further comprises a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
A power supply component 54 provides power to the various components of the electronic device. The power components 54 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for an electronic device.
The audio component 55 is configured to output and/or input audio signals. For example, the audio component 55 includes a Microphone (MIC) configured to receive external audio signals when the electronic device is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal may further be stored in the memory 51 or transmitted via the communication component 53. In some embodiments, audio assembly 55 also includes a speaker for outputting audio signals.
The display 56 includes a screen, which may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (13)
1. An FPGA accelerating system is characterized in that a control module and a plurality of execution modules for executing different operations are arranged in the FPGA,
the control module is used for analyzing the received instruction and generating scheduling information, wherein the scheduling information comprises an execution module required to execute the instruction and an operation sequence of the execution module;
the execution module is used for executing operation according to the scheduling information generated by the control module.
2. The FPGA acceleration system of claim 1, further comprising: and the storage module is used for storing the intermediate data generated by the execution module in the operation.
3. The FPGA acceleration system according to claim 2, wherein a memory pool corresponding to the execution module is provided in the storage module, data stored in the memory pool has an index number, and the execution module calls related data through the index number.
4. The FPGA acceleration system of claim 1, wherein the control module is further configured to query a table of correspondence between a plurality of pre-stored instructions and scheduling information, and obtain the scheduling information corresponding to the received instruction.
5. The FPGA acceleration system of claim 1, further comprising:
and the communication module is arranged in the FPGA and used for transmitting instructions and data.
6. The FPGA acceleration system of claim 5, characterized in that the communication module communicates with the host using a remote procedure call protocol.
7. An FPGA acceleration method, wherein a plurality of execution modules for executing different operations are arranged inside the FPGA, and the method comprises the following steps:
analyzing a received instruction to generate scheduling information, wherein the scheduling information comprises an execution module required to execute the instruction and an operation sequence of the execution module;
and controlling the execution module to execute the operation according to the scheduling information.
8. The FPGA acceleration method of claim 7, characterized in that intermediate data generated by the execution of the operations by the execution module are stored in the FPGA.
9. The FPGA acceleration method of claim 8, characterized in that the stored data have an index number by which the execution module invokes the relevant data.
10. The FPGA acceleration method of claim 7, characterized in that, analyzing the received command to generate scheduling information comprises:
and inquiring a corresponding relation table of a plurality of prestored instructions and scheduling information to obtain the scheduling information corresponding to the received instructions.
11. The FPGA acceleration method of claim 7, characterized in that the FPGA communicates with a host using a remote procedure call protocol.
12. An electronic device is used for an FPGA acceleration system, a plurality of execution modules used for executing different operations are arranged inside an FPGA, and the electronic device is characterized by comprising:
a memory for storing a program;
a processor for executing the program stored in the memory for:
analyzing a received instruction to generate scheduling information, wherein the scheduling information comprises an execution module required to execute the instruction and an operation sequence of the execution module;
and controlling the execution module to execute the operation according to the scheduling information.
13. A computer-readable storage medium for an FPGA acceleration system, the FPGA having a plurality of execution modules disposed therein for performing different operations, a computer program stored on the computer-readable storage medium, the computer program when executed by a processor implementing:
analyzing a received instruction to generate scheduling information, wherein the scheduling information comprises an execution module required to execute the instruction and an operation sequence of the execution module;
and controlling the execution module to execute the operation according to the scheduling information.
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