CN112470274B

CN112470274B - Architecture, structure, method and memory array for 3D FeRAM

Info

Publication number: CN112470274B
Application number: CN202080003086.7A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2023-10-10
Anticipated expiration: 2040-10-23
Also published as: CN112470274A; WO2022082750A1

Abstract

A three-dimensional memory architecture includes a top cell array of memory cells, a bottom cell array of memory cells, a plurality of word lines coupled to the array, and a plurality of word line decoders coupled to the word lines and operable to selectively activate the word lines. A plurality of word line decoders extend from a first edge of the bottom cell array and from a second edge of the bottom cell array, the second edge being opposite the first edge, wherein the plurality of word line decoders include a first portion of the word line decoders and a second portion of the word line decoders, and wherein the first portion of the word line decoders are moved relative to the second portion of the word line decoders in a direction parallel, or substantially parallel, to the first edge and the second edge.

Description

Architecture, structure, method and memory array for 3D FeRAM

Technical Field

The present disclosure relates generally to three-dimensional electronic memories including ferroelectric random access memories, and more particularly to increasing the density of memory cells in three-dimensional cross-point memories.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar processing and fabrication techniques become challenging and costly. In this way, the storage density of the planar memory cell approaches the upper limit.

Ferroelectric random access memory (FeRAM) uses planar transistors as selection devices for ferroelectric memory cells to form a two-dimensional memory array. FeRAM is a random access memory similar to Dynamic Random Access Memory (DRAM), but FeRAM uses memory cells with ferroelectric capacitors instead of dielectric capacitors to store data. FeRAM may reduce power usage, have faster write performance, and good read and write endurance (e.g., from about 1010 to about 1014 cycles, possibly as DRAM or flash), and good data retention.

Conventional ferams use parallel capacitor memory cells that require large dimensions (typically cell sizes greater than 15F 2) to achieve adequate capacitance variation. As a result, the memory bit area is large and the data storage density is low and cannot compete with the mainstream memory technology. Three-dimensional (3D) memory architecture can address density limitations in planar memory cells. The single capacitor FeRAM cell is a 1t1c FeRAM cell.

Disclosure of Invention

The following summary is included to provide a basic understanding of aspects and features of the disclosure. This summary is not an extensive overview and, as such, is not intended to identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a generalized format.

In one aspect, a new cell structure for a 3D ferroelectric memory cell is presented to increase data storage density and reduce memory bit cost. In the current new cell structure, a cross-point array is employed with parallel Bit Lines (BL) and perpendicular Word Lines (WL). The memory cells may be controlled by vertical transistors to an effective cell size of 4F2 on a single stack (deck), or to an effective cell size of 2F2 on two stacks, where F is the minimum processing size. In another aspect, the memory cells may be controlled by a container type FeRAM memory cell such as a container capacitor (container capacitor) to reduce the footprint of each individual memory cell in order to increase the memory bit density. Additional layers of FeRAM cells may be further added on top to further increase the memory bit density.

The container-type memory cell using FeRAM allows a smaller unit memory cell size. The cross-point architecture and vertical transistors achieve an effective cell size of 4F2 on each stack. The architecture achieves an effective cell size of 2F2 for two stacks of FeRAM memory cells and 1F2 for four stacks of FeRAM cells. The 3D FeRAM architecture with shared common substrate or bit lines increases memory bit density and reduces silicon cost.

A cross-point architecture for implementing a 3D FeRAM memory array includes a vertical transistor select device and a top cell stack of a single capacitor FeRAM cell on top of a bottom cell stack of a single capacitor FeRAM cell. The vertical transistor select device achieves a cross-point array and an effective cell size per stack 4F 2. The plurality of FeRAM cells are container capacitors that achieve an effective cell size of 4F 2. The top cell stack and the bottom cell stack share a common substrate or common bit line.

The three-dimensional memory array includes a top cell array of memory cells, a bottom cell array of memory cells, a common substrate between the top cell array and the bottom cell array, a plurality of word lines coupled to the top cell array and to the bottom cell array, two sets of bit lines including a set of top cell bit lines coupled to the top cell array and a set of bottom cell bit lines coupled to the bottom cell array. A plurality of word lines and the set of bit lines form an array of intersection points. A plurality of FeRAM cells are in a top cell array and a bottom cell array. The plurality of word lines of the top cell array may be parallel to the plurality of word lines of the bottom cell array. The set of bit lines may be perpendicular to the plurality of word lines.

The three-dimensional FeRAM memory cell includes a vertical ferroelectric memory cell container and a vertical select transistor. A vertical ferroelectric memory cell container may be disposed above the vertical selection transistor. The vertical ferroelectric memory cell container is a container capacitor.

The method for manufacturing the three-dimensional memory array comprises the following steps: forming a first set of parallel bit lines for the bottom stack; forming an array of vertical transistors; inserting FeRAM memory cells over the vertical transistors; forming a common substrate on the FeRAM unit; and forming a top stack of memory cells by forming a second set of parallel bit lines for the top stack and forming an array of vertical transistors.

Drawings

The foregoing aspects, features and advantages of the present disclosure will be further understood when considering the following description with reference to exemplary embodiments and the accompanying drawings in which like reference numerals refer to like elements. In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, aspects of the present disclosure are not intended to be limited to the specific terminology used.

Fig. 1 is an isometric view of a section of a prior art planar memory cell.

Fig. 2 is a plan view of a section of a conventional planar memory cell.

Fig. 3A and 3B are plan views of sections of a three-dimensional cross-point memory according to an embodiment.

Fig. 4 is a plan view of a section of a memory array of the three-dimensional cross-point memory according to the embodiments of fig. 3A and 3B.

Fig. 5A and 5B are plan views of sections of a three-dimensional cross-point memory according to additional embodiments.

Fig. 6 is a plan view of a section of a memory of the three-dimensional cross-point memory according to the embodiments of fig. 5A and 5B.

Fig. 7 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 8 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 9 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 10 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 11 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 12 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Detailed Description

The technology is applied to the field of three-dimensional memories. Fig. 1 shows a general example of a planar memory cell. Specifically, fig. 1 is a plan view of a conventional ferroelectric random access memory (FeRAM) cell. The memory cell 10 includes a FeRAM cell 11 attached to a vertical transistor 14. The memory cell includes a vertical transistor 14 extending from a substrate 12. The memory cell may further include a bit line (not shown) extending in the Y direction and a word line 13 extending in the X direction. Regardless, individual memory cells can be accessed by selectively activating the word lines and bit lines corresponding to the cells.

To selectively activate the word lines and bit lines, the memory includes a word line decoder and a bit line decoder. The word line decoder is coupled to the word lines through word line contacts and is used to decode word line addresses such that a particular word line is activated when addressed. Similarly, a bit line decoder is coupled to the bit lines through bit line contacts and is used to decode bit line addresses such that a particular bit line is activated when addressed. The locations of the word line decoders and contacts and the locations of the bit line decoders and contacts are also discussed in connection with fig. 2.

Fig. 2 is a plan view of a section of a planar memory of prior art construction. The figure depicts the section as seen in the Z (depth) direction. The segment includes word lines 13 extending in the X (horizontal) direction, bit lines 15 extending in the Y (vertical) direction and corresponding to memory cells (not shown). Word lines, top cell bit lines, and bottom cell bit lines (not shown) are typically formed according to a 20nm/20nm line/space (L/S) pattern and on a silicon substrate.

Developers of the present technology have recognized disadvantages caused by existing constructions and have provided the present technology in view of such disadvantages.

Fig. 3A and 3B are plan views of sections of a three-dimensional cross-point memory according to an embodiment. Fig. 4 is a plan view of a section of a memory array of the three-dimensional cross-point memory according to the embodiments of fig. 3A and 3B.

Fig. 3A illustrates a vertical single capacitor 100 according to an embodiment of the present disclosure. The vertical single capacitor 100 includes a top cell stack 111 and a bottom cell stack 112. The top unit stack 111 and the bottom unit stack 112 are attached at the common substrate 104. The common substrate 104 may be a common electrode. The vertical single capacitor includes a vertical transistor 105, and the vertical transistor 105 can select and access a ferroelectric (FeRAM) memory cell 103. The FeRAM memory unit 103 is attached to the vertical transistor 105 at one end and to the common substrate 104 at the other end. The vertical transistor 105 is attached to the bit line 101 at one end, and the bit line 101 extends in the X direction. The word line 102 may be stacked on the vertical transistor 105 in the Y direction such that the word line 102 is perpendicular to the bit line 101. The ferroelectric memory cell 103 may be a capacitor. Ferroelectric memory cell 103 with a capacitor can reduce the cell area to the effective cell size of 2F2 for two stacks of FeRAM cells or 1F2 for four stacks of FeRAM cells, where F is the minimum process size. The bottom cell stack 112 may be attached to the complementary metal oxide semiconductor 106. Fig. 3B shows a vertical single capacitor 100 according to the embodiment shown in fig. 3A in a three-dimensional view.

Fig. 4 is a plan view of a section of a memory array of the three-dimensional cross-point memory according to the embodiments of fig. 3A and 3B. FIG. 4 shows a memory array 400 in a two stack configuration. As can be seen in fig. 4, the first stack 413 is configured similar to the second stack 414. The first stack 413 as described herein may also be applied to the second stack 414. The memory array 400 of a single capacitor 100 may be implemented as a cross-point architecture. The memory array 400 includes word lines 402 extending in the Y direction and bit lines 401 extending in the X direction. FeRAM unit 403 may be implemented in memory array 400. As described in fig. 3A and 3B, feRAM cell 403 is present in both top cell stack 411 and bottom cell stack 412. The top unit stack 411 and the bottom unit stack 412 are attached at the common substrate 404. The first stack 413 may be parallel to the second stack 414, or the first stack 413 may be perpendicular to the second stack 414.

Fig. 5A and 5B are plan views of sections of a three-dimensional cross-point memory according to additional embodiments. Fig. 6 is a plan view of a section of a memory of the three-dimensional cross-point memory according to the embodiments of fig. 5A and 5B.

Fig. 5A shows a vertical single capacitor 200 according to an additional embodiment of the present disclosure. The vertical single capacitor 200 includes a top cell stack 211 and a bottom cell stack 212. The top cell stack 211 and the bottom cell stack 212 are attached at a common bit line 201, the bit line 201 extending in the X-direction. The top cell stack 211 and the bottom cell stack 212 share common substrates 204a and 204b, and the common substrates 204a and 204b may be connected or individually biased. The vertical single capacitor includes a vertical transistor 205 that can select and access the ferroelectric (FeRAM) memory cell 103.FeRAM memory cell 203 is attached at one end to vertical transistor 205 and at the other end to common bit line 201. The vertical transistors 205 of the top cell stack 211 are attached at one end to the common substrate 204a, while the vertical transistors 205 of the bottom cell stack 212 are attached at one end to the common substrate 204b. The common substrates 204a, 204b may be common electrodes. The word line 202 may be stacked on the vertical transistor 205 in the Y direction such that the word line 202 is perpendicular to the bit line 201. The ferroelectric memory cell 203 may be a container capacitor. Ferroelectric memory cell 203 with a capacitor can reduce the cell area to the effective cell size of 2F2 for two stacks of FeRAM cells or 1F2 for four stacks of FeRAM cells, where F is the minimum process size. The bottom cell stack 212 may be attached to the complementary metal oxide semiconductor 206. Fig. 5B shows a vertical single capacitor 200 according to the embodiment shown in fig. 5A in a three-dimensional view.

Fig. 6 is a plan view of a section of a memory array of the three-dimensional cross-point memory according to the embodiment of fig. 5A and 5B. FIG. 6 illustrates a storage array 600 in a two stack configuration. As can be seen in fig. 6, the first stack 613 is configured similar to the second stack 614. The first stack 613 as described herein may also be applied to the second stack 614. The memory array 600 of a single capacitor 200 may be implemented as a cross-point architecture. The memory array 600 includes word lines 602 extending in the Y direction and bit lines 601 extending in the X direction. FeRAM unit 603 may be implemented in memory array 600. As shown in fig. 5A and 5B, feRAM unit 603 exists in both top unit stack 611 and bottom unit stack 612. The top cell stack 611 and the bottom cell stack 612 are attached at a common bit line 601. The first stack 613 and the second stack 614 include a common substrate 604a at one end and a common substrate 604b at the other end. The word lines of the first stack 613 and the word lines of the second stack 614 may be parallel in both stacks and perpendicular to the common bit line 601.

Fig. 7 to 12 show a method for manufacturing a three-dimensional vertical single capacitor according to fig. 3A, 3B and 4. A method for fabricating a three-dimensional vertical single capacitor according to another embodiment is shown. In fig. 7, parallel bit lines 101 are formed for the bottom stack 112. As can be seen in fig. 8, parallel word lines 102 for the bottom stack 112 are formed such that the parallel word lines 102 are perpendicular to the bit lines 101 and form a cross-point array. The word line 102 may be doped with a polymer. In fig. 9, holes are formed in the parallel word lines 102 by various processes (e.g., etching). To form the holes, the word lines are etched through the polymer. Once the holes are etched through the polymer, gate oxides are formed and then polysilicon channel dielectrophoresis. Thus, vertical transistor 105 is inserted into parallel word line 102. As can be seen in fig. 10, feRAM cells 103 are attached on top of each vertical transistor 105 to establish an electrical connection. As can be seen in fig. 11, the common substrate 104 is then placed on top of the FeRAM unit. The common substrate is a common electrode. In fig. 12, a top stack 111 is formed in a similar manner as described above with respect to bottom stack 112, forming FeRAM cells in a similar cross-point array accessed by a vertical transistor select device.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the foregoing operations need not be performed in the exact order described above. Rather, the steps may be processed in a different order (e.g., inverted or simultaneously). Unless otherwise indicated, steps may also be omitted. In addition, clauses of the examples described herein that are provided to phrase "for example," "including," etc. should not be construed as limiting the claimed subject matter to the particular examples; rather, this example is intended to be illustrative of only one of many possible embodiments. Furthermore, the same reference numbers in different drawings may identify the same or similar elements.

Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A cross-point architecture for implementing a 3D FeRAM memory array, comprising:

a top cell stack of a single capacitor FeRAM cell, the top cell stack being on top of a bottom cell stack of a single capacitor FeRAM cell;

a vertical transistor select device;

wherein the vertical transistor select device achieves a cross-point array and an effective cell size of 4F2 per stack;

wherein the plurality of FeRAM cells are container capacitors that achieve an effective cell size of the 4F 2; and is also provided with

Wherein the top cell stack and the bottom cell stack share a common substrate or common bit line.

2. The cross-point architecture of claim 1 wherein the single capacitor FeRAM cell is a 1t1c FeRAM cell.

3. A three-dimensional memory array, comprising:

a top cell array of memory cells;

a bottom cell array of memory cells;

a common substrate or a common bit line between the top cell array and the bottom cell array;

a plurality of word lines coupled to the top cell array and to the bottom cell array;

two sets of bit lines including a set of top cell bit lines coupled to the top cell array and a set of bottom cell bit lines coupled to the bottom cell array;

the plurality of word lines and the group of bit lines form a cross point array; and

a plurality of FeRAM cells in the top cell array and the bottom cell array.

4. The three-dimensional memory array of claim 3, wherein the plurality of word lines of the top cell array are parallel to the plurality of word lines of the bottom cell array.

5. The three-dimensional memory array of claim 4, wherein the set of bit lines is perpendicular to the plurality of word lines.

6. The three-dimensional memory array of claim 3, further comprising a plurality of vertical select transistors, wherein the plurality of vertical select transistors and the set of bit lines access the plurality of FeRAM cells.

7. The three-dimensional storage array of claim 3, further comprising:

a vertical ferroelectric memory cell container; and

a vertical selection transistor is used to select the transistor,

wherein the vertical ferroelectric memory cell container is disposed above the vertical selection transistor.

8. The three-dimensional memory array of claim 7, wherein the vertical ferroelectric memory cell container is a container capacitor.

9. A method of fabricating a three-dimensional memory array, comprising:

forming a first set of parallel bit lines for the bottom stack;

forming an array of vertical transistors;

inserting FeRAM memory cells over the vertical transistors;

forming a common substrate on the FeRAM unit; and

the top stack of memory cells is formed by forming a second set of parallel bit lines for the top stack and forming an array of vertical transistors.