WO2023115418A1

WO2023115418A1 - Ferroelectric memory and electronic device

Info

Publication number: WO2023115418A1
Application number: PCT/CN2021/140629
Authority: WO
Inventors: 殷士辉; 景蔚亮; 黄凯亮; 卜思童; 王正波; 许俊豪
Original assignee: 华为技术有限公司
Priority date: 2021-12-22
Filing date: 2021-12-22
Publication date: 2023-06-29
Also published as: CN116686403A

Abstract

The embodiments of the present application relate to the technical field of memories. Provided are a ferroelectric memory and an electronic device, by means of which the area of a storage unit can be reduced. A storage unit in the ferroelectric memory comprises a read transistor, a pre-charging transistor and a capacitor bank, wherein a first electrode of the read transistor is electrically connected to a first bit line, and a second electrode thereof is electrically connected to a source line; a first electrode of the pre-charging transistor is electrically connected to a gate electrode of the read transistor, a second electrode thereof is electrically connected to a second bit line, and a gate electrode thereof is electrically connected to a control line; the first electrode of the read transistor and the first electrode of the pre-charging transistor are both arranged at the sides of the respective second electrodes in a first direction; a semiconductor layer of the read transistor comprises a first portion, a semiconductor layer of the pre-charging transistor comprises a second portion, and the first portion and the second portion both extend in the first direction; the capacitor bank comprises a first capacitor and a second capacitor, which are stacked; and the first capacitor and the second capacitor are electrically connected to the gate electrode of the read transistor, the first capacitor is further electrically connected to a first word line, and the second capacitor is further electrically connected to a second word line.

Description

一种铁电存储器及电子设备A kind of ferroelectric memory and electronic equipment

技术领域technical field

本申请涉及存储器技术领域，尤其涉及一种铁电存储器及电子设备。The present application relates to the technical field of memory, in particular to a ferroelectric memory and electronic equipment.

背景技术Background technique

随着智能信息技术在人类社会中各个方向的应用，半导体计算芯片得到了蓬勃的发展。当前大量的计算芯片基于冯诺依曼架构，即存储单元与计算单元在物理上是分离的，大量的数据需要在存储单元与计算单元之间进行交换。尽管互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)器件物理尺寸逐渐微缩，芯片的计算性能不断提高，但大量应用于内存的动态随机存取存储器(dynamic random access memory，DRAM)的读取和写入的提升速率远远小于计算性能的提升，导致目前的计算芯片存在越来越严重的冯诺依曼瓶颈，半导体计算芯片的计算性能受到冯诺依曼瓶颈的显著影响，因此需要提升内存的存取速率和容量。With the application of intelligent information technology in all directions in human society, semiconductor computing chips have developed vigorously. At present, a large number of computing chips are based on the Von Neumann architecture, that is, the storage unit and the computing unit are physically separated, and a large amount of data needs to be exchanged between the storage unit and the computing unit. Although the physical size of complementary metal oxide semiconductor (CMOS) devices is gradually shrinking and the computing performance of chips is continuously improving, the reading and processing of dynamic random access memory (DRAM), which is widely used in memory, The improvement rate of writing is much smaller than the improvement of computing performance, which leads to more and more serious Von Neumann bottlenecks in current computing chips. The computing performance of semiconductor computing chips is significantly affected by Von Neumann bottlenecks, so it is necessary to improve memory access rate and capacity.

近年来，DRAM中的铁电存储器因其具有存储数据非易失，且存取速率快的特点，受到了广泛的关注。但是，当前的铁电存储器大多为平面结构，受器件物理尺寸和特性的影响，平面结构的铁电存储器的缩放速度逐渐放缓，存储密度难以进一步提升，因此提升铁电存储器的存储密度和容量是目前铁电存储器的发展难点。In recent years, ferroelectric memory in DRAM has received extensive attention because of its non-volatile data storage and fast access speed. However, most of the current ferroelectric memories have a planar structure. Due to the influence of the physical size and characteristics of the device, the scaling speed of the planar ferroelectric memory gradually slows down, and it is difficult to further increase the storage density. Therefore, the storage density and capacity of the ferroelectric memory are increased. It is the difficulty in the development of ferroelectric memory at present.

发明内容Contents of the invention

本申请的实施例提供一种铁电存储器及电子设备，可以解决铁电存储器中存储单元的面积大，铁电存储器的存储密度和容量低的问题。Embodiments of the present application provide a ferroelectric memory and electronic equipment, which can solve the problems of large storage unit area and low storage density and capacity of the ferroelectric memory.

为达到上述目的，本申请采用如下技术方案：In order to achieve the above object, the application adopts the following technical solutions:

第一方面，提供一种铁电存储器，该铁电存储器包括：阵列分布的多个存储单元、多条第一位线、多条第二位线、多条第一字线、多条第二字线、多条源线以及多条控制线；多个存储单元中的每个存储单元包括：读取晶体管、预充晶体管和至少一个电容组；读取晶体管的第一极与第一位线电连接，读取晶体管的第二极与源线电连接；读取晶体管的第一极设置在读取晶体管的第二极沿第一方向的一侧，读取晶体管的半导体层包括第一部分，第一部分沿第一方向延伸；读取晶体管的第一极和读取晶体管的第二极中一个为源极，另一个为漏极；预充晶体管的第一极与读取晶体管的栅极电连接，预充晶体管的第二极与第二位线电连接，预充晶体管的栅极与控制线电连接；预充晶体管的第一极设置在预充晶体管的第二极沿第一方向的一侧，预充晶体管的半导体层包括第二部分，第二部分沿第一方向延伸；预充晶体管的第一极和第二极中一个为源极，另一个为漏极；上述至少一个电容组中的每个电容组包括沿第一方向层叠设置且电连接的第一电容和第二电容；第一电容的第一电极板和第二电容的第一电极板均与读取晶体管的栅极以及预充晶体管的第一极电连接，第一电容的第二电极板与第一字线电连接，第二电容的第二电极板与第二字线电连接。In a first aspect, a ferroelectric memory is provided, which includes: a plurality of memory cells distributed in an array, a plurality of first bit lines, a plurality of second bit lines, a plurality of first word lines, a plurality of second A word line, a plurality of source lines and a plurality of control lines; each storage unit in the plurality of storage units includes: a read transistor, a precharge transistor and at least one capacitor group; the first pole of the read transistor and the first bit line Electrically connected, the second pole of the read transistor is electrically connected to the source line; the first pole of the read transistor is arranged on one side of the second pole of the read transistor along the first direction, and the semiconductor layer of the read transistor includes a first part, The first part extends along the first direction; one of the first pole of the read transistor and the second pole of the read transistor is a source, and the other is a drain; the first pole of the precharge transistor is connected to the gate electrode of the read transistor connected, the second pole of the precharge transistor is electrically connected to the second bit line, and the gate of the precharge transistor is electrically connected to the control line; the first pole of the precharge transistor is arranged on the side of the second pole of the precharge transistor along the first direction On one side, the semiconductor layer of the pre-charge transistor includes a second portion, and the second portion extends along the first direction; one of the first pole and the second pole of the pre-charge transistor is a source electrode, and the other is a drain electrode; the at least one capacitor Each capacitor group in the group includes a first capacitor and a second capacitor that are stacked and electrically connected along the first direction; the first electrode plate of the first capacitor and the first electrode plate of the second capacitor are both connected to the gate of the read transistor pole and the first pole of the precharge transistor are electrically connected, the second electrode plate of the first capacitor is electrically connected with the first word line, and the second electrode plate of the second capacitor is electrically connected with the second word line.

以第一方向为竖直方向，垂直于第一方向的方向为水平方向为例，相对于平面晶体管中第一极和第二极沿水平方向同层设置，且半导体层沿水平方向延伸而言，由于本申请中读取晶体管的第一极设置在读取晶体管的第二极沿竖直方向的一侧，且读取晶体管的半导体层包括第一部分，第一部分沿竖直方向延伸，因此读取晶体管在水平方向上的尺寸较小，从而可以使得存储单元的尺寸减小。同样的，由于预充晶体管的第一极设置在预充晶体管的第二极沿竖直方向的一侧，且预充晶体管的半导体层包括第二部分，第二部分沿竖直方向延伸，因此预充晶体管在水平方向上的尺寸较小，从而可以使得存储单元的尺寸较小。此外，第一电容和第二电容沿竖直方向层叠设置，因而在水平方向上，可以减小第一电容和第二电容所占的面积，进而可以进一步减小存储单元所占的面积。综上，由于本申请提供的铁电存储器中存储单元所占的面积减小，因而可以提高铁电存储器的存储密度和容量。Taking the first direction as the vertical direction and the direction perpendicular to the first direction as the horizontal direction as an example, compared to the planar transistor in which the first pole and the second pole are arranged in the same layer along the horizontal direction, and the semiconductor layer extends along the horizontal direction , since the first pole of the read transistor is arranged on one side of the second pole of the read transistor in the vertical direction in the present application, and the semiconductor layer of the read transistor includes a first portion extending in the vertical direction, the read The size of the transistor in the horizontal direction is smaller, so that the size of the memory cell can be reduced. Likewise, since the first pole of the pre-charge transistor is arranged on one side of the second pole of the pre-charge transistor along the vertical direction, and the semiconductor layer of the pre-charge transistor includes a second portion extending in the vertical direction, therefore The size of the pre-charge transistor is smaller in the horizontal direction, so that the size of the memory cell can be made smaller. In addition, the first capacitor and the second capacitor are stacked vertically, so in the horizontal direction, the area occupied by the first capacitor and the second capacitor can be reduced, and the area occupied by the storage unit can be further reduced. To sum up, since the area occupied by the storage unit in the ferroelectric memory provided by the present application is reduced, the storage density and capacity of the ferroelectric memory can be improved.

在一种可能的实施方式中，读取晶体管和预充晶体管沿第一方向层叠设置。In a possible implementation manner, the read transistor and the precharge transistor are stacked along the first direction.

由于预充晶体管沿第一方向与读取晶体管层叠设置，以第一方向为竖直方向，垂直于第一方向的方向为水平方向为例，因此在水平方向上，可以减小预充晶体管和读取晶体管所占的面积，进而可以减小存储单元所占的面积。Since the pre-charge transistor is stacked with the read transistor along the first direction, taking the first direction as the vertical direction and the direction perpendicular to the first direction as the horizontal direction as an example, in the horizontal direction, the pre-charge transistor and the read transistor can be reduced The area occupied by the read transistor can further reduce the area occupied by the memory cell.

在一种可能的实施方式中，存储单元还包括浮空栅电极；浮空栅电极的部分用于作为电容组中第一电容的第一电极板和第二电容的第一电极板；读取晶体管的栅极以及预充晶体管的第一极均与浮空栅电极电连接。In a possible implementation manner, the memory cell further includes a floating gate electrode; a part of the floating gate electrode is used as the first electrode plate of the first capacitor in the capacitor bank and the first electrode plate of the second capacitor; Both the gate of the transistor and the first pole of the pre-charge transistor are electrically connected to the floating gate electrode.

相对于分别单独设置第一电容的第一电极板和第二电容的第一电极板，在本申请中，通过设置浮空栅电极，并利用浮空栅电极的部分作为电容组中第一电容的第一电极板和第二电容的第一电极板，这样可以简化存储单元的结构。在此基础上，相对于额外设置连接部将浮空栅电极与读取晶体管的栅极以及预充晶体管的第一极电连接而言，利用浮空栅电极本身与读取晶体管的栅极以及预充晶体管的第一极电连接可以进一步简化存储单元的结构。Compared with separately setting the first electrode plate of the first capacitor and the first electrode plate of the second capacitor separately, in this application, by setting the floating gate electrode and using the part of the floating gate electrode as the first capacitor in the capacitor group The first electrode plate of the capacitor and the first electrode plate of the second capacitor can simplify the structure of the memory cell. On this basis, compared to additionally providing a connecting portion to electrically connect the floating gate electrode with the gate of the read transistor and the first electrode of the pre-charge transistor, using the floating gate electrode itself to connect with the gate of the read transistor and the first electrode of the pre-charge transistor The electrical connection of the first electrode of the pre-charge transistor can further simplify the structure of the memory cell.

在一种可能的实施方式中，第一字线与浮空栅电极相交，第一字线与浮空栅电极相交的部分用于作为第一电容的第二电极板；和/或，第二字线与浮空栅电极相交，第二字线与浮空栅电极相交的部分用于作为第二电容的第二电极板。In a possible implementation manner, the first word line intersects with the floating gate electrode, and the part where the first word line intersects with the floating gate electrode is used as a second electrode plate of the first capacitor; and/or, the second The word line intersects with the floating gate electrode, and the part where the second word line intersects with the floating gate electrode is used as a second electrode plate of the second capacitor.

利用第一字线的部分作为第一电容的第二电极板，这样无需单独制作第一电容的第二电极板，从而可以简化存储单元的结构。同样的，利用第二字线的部分作为第二电容的第二电极板，这样无需单独制作第二电容的第二电极板，从而可以简化存储单元的结构。Using part of the first word line as the second electrode plate of the first capacitor does not need to separately manufacture the second electrode plate of the first capacitor, thereby simplifying the structure of the memory cell. Similarly, using the part of the second word line as the second electrode plate of the second capacitor does not need to separately manufacture the second electrode plate of the second capacitor, thereby simplifying the structure of the memory cell.

在一种可能的实施方式中，读取晶体管为垂直沟道晶体管，和/或，预充晶体管为垂直沟道晶体管；垂直沟道晶体管的栅极包括栅基底、以及与栅基底接触且沿第一方向延伸的栅极柱，垂直沟道晶体管的第一极和垂直沟道晶体管的第二极设置在垂直沟道晶体管的栅基底沿第一方向的同一侧；垂直沟道晶体管的半导体层至少设置在栅极柱的侧面，垂直沟道晶体管的第一极和第二极分别与垂直沟道晶体管的半导体层接触；垂直沟道晶体管还包括：栅介质层以及第一绝缘介质层；栅介质层设置在垂直沟道晶体管的半导体层和垂直沟道晶体管的栅极之间；第一绝缘介质层设置在垂直沟道晶体管的第一极和第二极之间。In a possible implementation manner, the read transistor is a vertical channel transistor, and/or the prefill transistor is a vertical channel transistor; the gate of the vertical channel transistor includes a gate substrate, and is in contact with the gate substrate and along the The gate column extending in one direction, the first pole of the vertical channel transistor and the second pole of the vertical channel transistor are arranged on the same side of the gate base of the vertical channel transistor along the first direction; the semiconductor layer of the vertical channel transistor is at least It is arranged on the side of the gate column, and the first pole and the second pole of the vertical channel transistor are respectively in contact with the semiconductor layer of the vertical channel transistor; the vertical channel transistor also includes: a gate dielectric layer and a first insulating dielectric layer; a gate dielectric layer The layer is arranged between the semiconductor layer of the vertical channel transistor and the gate of the vertical channel transistor; the first insulating medium layer is arranged between the first pole and the second pole of the vertical channel transistor.

由于垂直沟道晶体管相对于平面晶体管的面积较小，因而当读取晶体管和/或预充晶体管为垂直沟道晶体管时，可以减小存储单元所占的面积。Since the area of the vertical channel transistor is smaller than that of the planar transistor, when the read transistor and/or the precharge transistor is a vertical channel transistor, the area occupied by the memory cell can be reduced.

在一种可能的实施方式中，读取晶体管为环栅晶体管，和/或，预充晶体管为环栅晶体管；环栅晶体管的栅极设置在环栅晶体管的第一极和环栅晶体管的第二极之间；环栅晶体管还包括：第一绝缘介质层、第二绝缘介质层以及栅介质层；第一绝缘介质层设置在环栅晶体管的第一极和环栅晶体管的栅极之间；第二绝缘介质层设置在环栅晶体管的第二极与环栅晶体管的栅极之间；环栅晶体管的半导体层依次贯穿环栅晶体管的第一极、环栅晶体管的第一绝缘介质层、环栅晶体管的栅极、环栅晶体管的第二绝缘介质层以及环栅晶体管的第二极；环栅晶体管的第一极和环栅晶体管的第二极分别与环栅晶体管的半导体层接触；环栅晶体管的栅介质层设置在环栅晶体管的半导体层和环栅晶体管的栅极之间。In a possible implementation manner, the read transistor is a gate-around transistor, and/or the precharge transistor is a gate-around transistor; the gate of the gate-around transistor is set at the first pole of the gate-around transistor and the second Between the two poles; the surrounding gate transistor also includes: a first insulating dielectric layer, a second insulating dielectric layer and a gate dielectric layer; the first insulating dielectric layer is arranged between the first pole of the surrounding gate transistor and the gate of the surrounding gate transistor The second insulating medium layer is arranged between the second pole of the surrounding gate transistor and the gate of the surrounding gate transistor; the semiconductor layer of the surrounding gate transistor passes through the first pole of the surrounding gate transistor and the first insulating medium layer of the surrounding gate transistor in sequence , the gate of the surrounding gate transistor, the second insulating medium layer of the surrounding gate transistor and the second pole of the surrounding gate transistor; the first pole of the surrounding gate transistor and the second pole of the surrounding gate transistor are respectively in contact with the semiconductor layer of the surrounding gate transistor ; The gate dielectric layer of the gate-around transistor is arranged between the semiconductor layer of the gate-around transistor and the gate of the gate-around transistor.

由于环栅晶体管相对于平面晶体管的面积较小，因而当读取晶体管和/或预充晶体管为环栅晶体管时，可以减小存储单元所占的面积。Since the area of the gate-around transistor is smaller than that of the planar transistor, when the read transistor and/or the precharge transistor is a gate-around transistor, the area occupied by the memory unit can be reduced.

在一种可能的实施方式中，多条源线和多条第一位线相交。此处，可以是源线和第一位线在同一平面上的投影相互垂直，也可以是源线和第一位线在同一平面上的投影之间的夹角为锐角。In a possible implementation manner, multiple source lines intersect with multiple first bit lines. Here, the projections of the source line and the first bit line on the same plane may be perpendicular to each other, or the angle between the projections of the source line and the first bit line on the same plane may be an acute angle.

可以根据需要灵活地设置源线和第一位线的相对位置，进而可以降低***电路的设计难度。The relative positions of the source line and the first bit line can be flexibly set according to needs, thereby reducing the difficulty of designing peripheral circuits.

在一种可能的实施方式中，多条源线和多条第一位线相互平行。In a possible implementation manner, the multiple source lines and the multiple first bit lines are parallel to each other.

在一种可能的实施方式中，与同一个存储单元电连接的第一位线和第二位线电连接。在此情况下，可以通过一个电压端同时向第一位线和第二位线提供电压，这样可以简化铁电存储器的结构。In a possible implementation manner, the first bit line electrically connected to the same memory cell is electrically connected to the second bit line. In this case, voltages can be supplied to the first bit line and the second bit line simultaneously through one voltage terminal, which can simplify the structure of the ferroelectric memory.

在一种可能的实施方式中，与同一个存储单元电连接的第一位线和第二位线相互不电连接。在此情况下，可以通过两个电压端分别向第一位线和第二位线提供电压，施加到第一位线上的电压和施加到第二位线上的电压可以相同，也可以不相同。In a possible implementation manner, the first bit line and the second bit line electrically connected to the same memory cell are not electrically connected to each other. In this case, voltages can be provided to the first bit line and the second bit line respectively through the two voltage terminals, and the voltage applied to the first bit line and the voltage applied to the second bit line can be the same or not. same.

由于施加到第一位线上的电压和施加到第二位线上的电压可以灵活进行调整，从而提高了铁电存储器应用的灵活性。Since the voltage applied to the first bit line and the voltage applied to the second bit line can be flexibly adjusted, the application flexibility of the ferroelectric memory is improved.

在一种可能的实施方式中，多条源线和多条第一位线相互平行，读取晶体管的第一极相对于读取晶体管的第二极靠近预充晶体管，且沿第一方向，第一位线设置在源线和第二位线之间。In a possible implementation manner, the multiple source lines and the multiple first bit lines are parallel to each other, the first pole of the read transistor is closer to the precharge transistor relative to the second pole of the read transistor, and along the first direction, The first bit line is disposed between the source line and the second bit line.

由于沿第一方向，第一位线设置在源线和第二位线之间，这样在第一位线和第二位线通过位线接触通孔电连接时，设置位线接触通孔时无需避让源线，从而降低了铁电存储器的设计难度。Since the first bit line is arranged between the source line and the second bit line along the first direction, when the first bit line and the second bit line are electrically connected through the bit line contact via hole, when the bit line contact via hole is set There is no need to avoid the source line, thereby reducing the design difficulty of the ferroelectric memory.

在一种可能的实施方式中，第一电容和第二电容还包括设置在第一电极板和第二电极板之间的铁电材料。在第一电容和第二电容的第一电极板和第二电极板之间的绝缘材料为铁电材料的情况下，第一电容和第二电容为铁电电容，这样一来，存储单元可以基于铁电电容的特性存储信息。In a possible implementation manner, the first capacitor and the second capacitor further include a ferroelectric material disposed between the first electrode plate and the second electrode plate. In the case that the insulating material between the first electrode plate and the second electrode plate of the first capacitor and the second capacitor is a ferroelectric material, the first capacitor and the second capacitor are ferroelectric capacitors, so that the storage unit can Information is stored based on the properties of the ferroelectric capacitor.

在一种可能的实施方式中，多条第一位线和多条第二位线相互平行，多条第一字线、多条第二字线以及多条控制线相互平行，多条第一位线和多条第一字线相交。这样可以同时制作多条第一位线和多条第二位线，同时制作多条第一字线、多条第二字线以及多条控制线。In a possible implementation manner, the multiple first bit lines and the multiple second bit lines are parallel to each other, the multiple first word lines, the multiple second word lines and the multiple control lines are parallel to each other, and the multiple first The bit line intersects the plurality of first word lines. In this way, a plurality of first bit lines and a plurality of second bit lines can be manufactured simultaneously, and a plurality of first word lines, a plurality of second word lines and a plurality of control lines can be manufactured simultaneously.

第二方面，提供一种电子设备，该电子设备包括印刷电路板以及上述第一方面提供的铁电存储器；其中，铁电存储器和印刷电路板电连接。该电子设备具有与上述第一方面提供的铁电存储器相同的技术效果，可以参考上述第一方面的相关描述，此处不再赘述。According to a second aspect, an electronic device is provided, which includes a printed circuit board and the ferroelectric memory provided in the first aspect above; wherein, the ferroelectric memory is electrically connected to the printed circuit board. The electronic device has the same technical effect as that of the ferroelectric memory provided by the first aspect above, and reference may be made to the relevant description of the first aspect above, and details will not be repeated here.

附图说明Description of drawings

图1为本申请的实施例提供的一种电子设备的结构示意图；FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

图2为本申请的另一实施例提供的一种电子设备的结构示意图；FIG. 2 is a schematic structural diagram of an electronic device provided by another embodiment of the present application;

图3a为相关技术提供的一种存储单元的电路结构图；Fig. 3a is a circuit structure diagram of a memory cell provided by the related art;

图3b为相关技术提供的另一种存储单元的电路结构图；Fig. 3b is a circuit structure diagram of another memory cell provided by the related art;

图3c为相关技术提供的又一种存储单元的电路结构图；Fig. 3c is a circuit structure diagram of another storage unit provided by the related art;

图3d为相关技术提供的又一种存储单元的电路结构图；Fig. 3d is a circuit structure diagram of another storage unit provided by the related art;

图4a为本申请的实施例提供的一种铁电存储器的结构示意图；FIG. 4a is a schematic structural diagram of a ferroelectric memory provided by an embodiment of the present application;

图4b为图4a中沿AA向的剖面示意图；Fig. 4b is a schematic cross-sectional view along AA in Fig. 4a;

图4c为图4a所示的铁电存储器中一个存储单元对应的电路结构示意图；Fig. 4c is a schematic diagram of a circuit structure corresponding to a memory cell in the ferroelectric memory shown in Fig. 4a;

图5a为本申请的实施例提供的一种垂直沟道晶体管的结构示意图；FIG. 5a is a schematic structural diagram of a vertical channel transistor provided by an embodiment of the present application;

图5b为本申请的另一实施例提供的一种垂直沟道晶体管的结构示意图；FIG. 5b is a schematic structural diagram of a vertical channel transistor provided by another embodiment of the present application;

图5c为本申请的又一实施例提供的一种垂直沟道晶体管的结构示意图；FIG. 5c is a schematic structural diagram of a vertical channel transistor provided by another embodiment of the present application;

图5d为本申请的又一实施例提供的一种垂直沟道晶体管的结构示意图；FIG. 5d is a schematic structural diagram of a vertical channel transistor provided by another embodiment of the present application;

图6a为本申请的另一实施例提供的一种铁电存储器的结构示意图；Fig. 6a is a schematic structural diagram of a ferroelectric memory provided by another embodiment of the present application;

图6b为图6a中沿BB向的剖面示意图；Figure 6b is a schematic cross-sectional view along the BB direction in Figure 6a;

图7为本申请的实施例提供的一种环栅晶体管的结构示意图；FIG. 7 is a schematic structural diagram of a gate-all-around transistor provided by an embodiment of the present application;

图8为本申请的实施例提供的一种铁电存储器的剖面结构示意图；FIG. 8 is a schematic cross-sectional structure diagram of a ferroelectric memory provided by an embodiment of the present application;

图9为本申请的另一实施例提供的一种铁电存储器的剖面结构示意图；FIG. 9 is a schematic cross-sectional structure diagram of a ferroelectric memory provided by another embodiment of the present application;

图10a为本申请实施例提供的铁电存储器中一个存储单元在垂直第一方向X的平面上的俯视结构示意图；Fig. 10a is a schematic top view of a memory cell in a ferroelectric memory provided by an embodiment of the present application on a plane perpendicular to the first direction X;

图10b为相关技术提供的铁电存储器中一个存储单元在垂直于第一方向X的平面上的俯视结构示意图；Fig. 10b is a schematic top view structure diagram of a memory cell in a ferroelectric memory provided by the related art on a plane perpendicular to the first direction X;

图11a为本申请的又一实施例提供的一种铁电存储器的结构示意图；Fig. 11a is a schematic structural diagram of a ferroelectric memory provided by another embodiment of the present application;

图11b为图11a中沿CC向的剖面示意图。Fig. 11b is a schematic cross-sectional view along CC direction in Fig. 11a.

附图标记：1-电子设备；10-铁电存储器；11-存储装置；12-处理器；13-输入设备；14-输出设备；15-中框；16-后壳；17-显示屏；100-存储单元；101-第一极；102-第二极；103-栅极；104-半导体层；105-栅介质层；106-第一绝缘介质层；107-电容组；108-位线接触通孔；109-浮空栅电极；110-第一绝缘介质层；111-外存储器；112-内存储器；121-运算器；122-控制器；150-承载板；151-边框；1031-栅基底；1032-栅极柱；1071-第一电极板；1072-第二电极板；1073-绝缘材料。Reference signs: 1-electronic equipment; 10-ferroelectric memory; 11-storage device; 12-processor; 13-input device; 14-output device; 15-middle frame; 16-rear shell; 17-display screen; 100-memory unit; 101-first pole; 102-second pole; 103-gate; 104-semiconductor layer; 105-gate dielectric layer; 106-first insulating dielectric layer; 107-capacitor group; 108-bit line Contact through hole; 109-floating gate electrode; 110-first insulating medium layer; 111-external memory; 112-internal memory; 121-calculator; 122-controller; 1032-gate column; 1071-first electrode plate; 1072-second electrode plate; 1073-insulating material.

具体实施方式Detailed ways

下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。The following will describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them.

以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。Hereinafter, the terms "first", "second" and the like are used for convenience of description only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first", "second", etc. may expressly or implicitly include one or more of that feature. In the description of the present application, unless otherwise specified, "plurality" means two or more.

在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。In the embodiments of the present application, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

在本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。In this embodiment of the application, "and/or" describes the association relationship of associated objects, indicating that there may be three kinds of relationships, for example, A and/or B, which may mean: A exists alone, A and B exist simultaneously, and there exists alone In the case of B, where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship.

本申请的实施例提供一种电子设备，该电子设备例如可以为手机(mobile phone)、平板电脑(pad)、个人数字助理(personal digital assistant，PDA)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、充电家用小型电器(例如豆浆机、扫地机器人)、无人机、雷达、航空航天设备和车载设备等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。本申请实施例对电子设备的具体形式不作特殊限制。Embodiments of the present application provide an electronic device, which can be, for example, a mobile phone, a tablet computer (pad), a personal digital assistant (personal digital assistant, PDA), a TV, a smart wearable product (for example, a smart watch) , smart bracelet), virtual reality (virtual reality, VR) terminal equipment, augmented reality (augmented reality, AR) terminal equipment, charging small household appliances (such as soybean milk machine, sweeping robot), drones, radar, aerospace equipment and different types of user equipment or terminal equipment such as vehicle equipment; the electronic equipment may also be network equipment such as a base station. The embodiment of the present application does not specifically limit the specific form of the electronic device.

图1为本申请实施例示例性的提供的一种电子设备的架构示意图。如图1所示，该电子设备1包括：存储装置11、处理器12、输入设备13、输出设备14等部件。本领域技术人员可以理解到，图1中示出的电子设备的结构并不构成对该电子设备1的限定，该电子设备1可以包括比如图1所示的部件更多或更少的部件，或者可以组合如图1所示的部件中的某些部件，或者可以与如图1所示的部件布置不同。FIG. 1 is a schematic structural diagram of an electronic device exemplarily provided by an embodiment of the present application. As shown in FIG. 1 , the electronic device 1 includes components such as a storage device 11 , a processor 12 , an input device 13 , and an output device 14 . Those skilled in the art can understand that the structure of the electronic device shown in FIG. 1 does not constitute a limitation to the electronic device 1, and the electronic device 1 may include more or less components than those shown in FIG. 1 , Or some of the components shown in FIG. 1 may be combined, or the arrangement of components may be different from that shown in FIG. 1 .

存储装置11用于存储软件程序以及模块。存储装置11主要包括存储程序区和存储数据区，其中，存储程序区可存储操作***、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备的使用所创建的数据(比如音频数据、图像数据、电话本等)等。此外，存储装置11包括外存储器111和内存储器112。外存储器111和内存储器112存储的数据可以相互传输。外存储器111例如可以包括硬盘、U盘、软盘等。内存储器112例如可以包括随机存储器、只读存储器等。其中，随机存储器例如可以包括铁电存储器、相变存储器或磁性存储器等。目前，铁电存储器(ferroelectric random access memory，FeRAM)因其具有存储数据非易失，且存取速率快的特点，因而随机存储器常采用铁电存储器。The storage device 11 is used to store software programs and modules. The storage device 11 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program required by a function (such as a sound playback function, an image playback function, etc.); Data created by the use of electronic devices (such as audio data, image data, phonebook, etc.), etc. Furthermore, the storage device 11 includes an external memory 111 and an internal memory 112 . The data stored in the external memory 111 and the internal memory 112 can be transferred to each other. The external storage 111 may include, for example, a hard disk, a U disk, a floppy disk, and the like. The internal memory 112 may include, for example, random access memory, read-only memory, and the like. Wherein, the random access memory may include, for example, a ferroelectric memory, a phase change memory, or a magnetic memory. At present, ferroelectric random access memory (FeRAM) is often used in random access memory because of its non-volatile storage data and fast access speed.

处理器12是该电子设备1的控制中心，利用各种接口和线路连接整个电子设备1的各个部分，通过运行或执行存储在存储装置11内的软件程序和/或模块，以及调用存储在存储装置11内的数据，执行电子设备1的各种功能和处理数据，从而对电子设备1进行整体监控。可选的，处理器12可以包括一个或多个处理单元。例如，处理器12可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。例如，处理器12可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作***、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器12中。上述的应用处理器例如可以为中央处理器(central processing unit，CPU)。图1中以处理器12为CPU为例，CPU可以包括运算器121和控制器122。运算器121获取内存储器112存储的数据，并对内存储器112存储的数据进行处理，处理后的结果通常送回内存储器112。控制器122可以控制运算器121对数据进行处理，控制器122还可以控制外存储器置111和内存储器112存储数据或读取数据。The processor 12 is the control center of the electronic device 1. It uses various interfaces and lines to connect various parts of the entire electronic device 1. By running or executing software programs and/or modules stored in the storage device 11, and calling the The data in the device 11 executes various functions of the electronic device 1 and processes data, so as to monitor the electronic device 1 as a whole. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU) and the like. Wherein, different processing units may be independent devices, or may be integrated in one or more processors. For example, the processor 12 may integrate an application processor and a modem processor, wherein the application processor mainly processes operating systems, user interfaces, and application programs, and the modem processor mainly processes wireless communications. It can be understood that the modem processor may not be integrated into the processor 12 . The aforementioned application processor may be, for example, a central processing unit (central processing unit, CPU). In FIG. 1 , the processor 12 is taken as a CPU as an example, and the CPU may include a computing unit 121 and a controller 122 . The arithmetic unit 121 acquires the data stored in the internal memory 112 and processes the data stored in the internal memory 112 , and the processed result is usually sent back to the internal memory 112 . The controller 122 can control the arithmetic unit 121 to process data, and the controller 122 can also control the external memory device 111 and the internal memory 112 to store data or read data.

输入设备13用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。示例的，输入设备13可以包括触摸屏以及其他输入设备。触摸屏，也称为触摸面板，可收集用户在触摸屏上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触摸屏上或在触摸屏附近的操作)，并根据预先设定的程式驱动相应的连接装置。上述处理器12中的控制器122还可以控制输入设备13接收输入的信号或不接收输入的信号。此外，输入设备13接收到的输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入可以存储在内存储器112中。The input device 13 is used to receive input numbers or character information, and generate key signal input related to user settings and function control of the electronic device. Exemplarily, the input device 13 may include a touch screen and other input devices. The touch screen, also known as the touch panel, can collect the user's touch operation on or near the touch screen (such as the user's operation on the touch screen or near the touch screen with any suitable object or accessory such as a finger, stylus), and according to the preset The program drives the corresponding connected device. The controller 122 in the processor 12 may also control the input device 13 to receive an input signal or not to receive an input signal. In addition, the number or character information received by the input device 13 and the key signal input related to the user setting and function control of the electronic device can be stored in the internal memory 112 .

输出设备14用于输出输入设备13的输入，并存储在内存储器112中的数据对应的信号。例如，输出设备14输出声音信号或视频信号。上述处理器12中的控制器122还可以控制输出设备14输出信号或不输出信号。The output device 14 is used to output the input of the input device 13 and the signal corresponding to the data stored in the internal memory 112 . For example, the output device 14 outputs a sound signal or a video signal. The controller 122 in the above-mentioned processor 12 can also control the output device 14 to output a signal or not to output a signal.

需要说明的是，图1中的粗箭头用于表示数据的传输，粗箭头的方向表示数据传输的方向。例如，输入设备13和内存储器112之间的单箭头表示输入设备13接收到的数据向内存储器112传输。又例如，运算器121和内存储器112之间的双箭头表示内存储器112存储的数据可以向运算器121传输，且运算器121处理后的数据可以向内存储器112传输。图1中的细箭头表示控制器122可以控制的部件。示例的，控制器122可以对外存储器置111、内存储器112、运算器121、输入设备13和输出设备14等进行控制。It should be noted that the thick arrows in FIG. 1 are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, a single arrow between the input device 13 and the internal memory 112 indicates that the data received by the input device 13 is transmitted to the internal memory 112 . For another example, the double arrow between the computing unit 121 and the internal storage 112 indicates that the data stored in the internal storage 112 can be transmitted to the computing unit 121 , and the data processed by the computing unit 121 can be transmitted to the internal storage 112 . Thin arrows in FIG. 1 indicate components that the controller 122 can control. For example, the controller 122 may control the external memory device 111, the internal memory 112, the computing unit 121, the input device 13, the output device 14, and the like.

为了方便进一步对电子设备1的结构进行说明，以下以电子设备1为手机为例进行示例性介绍。如图2所示，电子设备1还可以包括中框15、后壳16以及显示屏17。后壳16和显示屏17分别位于中框15的两侧，且中框15和显示屏17设置于后壳16内。中框15包括用于承载显示屏17的承载板150，以及绕承载板150一周的边框151。电子设备1还可以包括设置于承载板150朝向后壳16的表面上的印刷电路板(printed circuit boards，PCB)，电子设备1中的一些电子器件例如上述的铁电存储器10可以设置于印刷电路板上；其中，铁电存储器10和印刷电路板电连接。In order to facilitate further description of the structure of the electronic device 1 , the following takes the electronic device 1 as a mobile phone as an example for an exemplary introduction. As shown in FIG. 2 , the electronic device 1 may further include a middle frame 15 , a rear case 16 and a display screen 17 . The rear case 16 and the display screen 17 are respectively located on two sides of the middle frame 15 , and the middle frame 15 and the display screen 17 are arranged in the rear case 16 . The middle frame 15 includes a supporting plate 150 for carrying the display screen 17 , and a frame 151 around the supporting plate 150 . The electronic device 1 may also include a printed circuit board (printed circuit boards, PCB) disposed on the surface of the carrier plate 150 facing the rear case 16, and some electronic devices in the electronic device 1 such as the above-mentioned ferroelectric memory 10 may be disposed on the printed circuit boards. on the board; wherein, the ferroelectric memory 10 is electrically connected to the printed circuit board.

目前，铁电存储器因其具有存储数据非易失，且存取速率快的特点，因而得到了广泛的应用例如用于作为内存储器112。铁电存储器10包括阵列分布的多个存储单元，相关技术提供的存储单元的结构包括以下几种：At present, the ferroelectric memory has been widely used, for example, as the internal memory 112 because of its characteristics of storing data in a non-volatile manner and having a fast access rate. The ferroelectric memory 10 includes a plurality of memory cells distributed in an array, and the structure of the memory cells provided by the related art includes the following types:

第一种，存储单元包括基于铁电电容(ferro electric capacitor)的电路结构，如图3a所示，该存储单元具有1T1C(1-transistor-1-capacitor)结构，即一个存储单元包括一个铁电电容C和一个晶体管T，晶体管T的源极与位线(bit line，BL)电连接，漏极与铁电电容C的一个电极板电连接，栅极与字线(word line，WL)电连接，铁电电容C的另一个电极板与板线(plate line，PL)电连接。图3a所示的存储单元存储信息的读取基于铁电电容的极化翻转电流，然而为了产生足够大的读取电流，存储单元中的铁电电容C需要具有较大的尺寸，这就导致存储单元的物理尺寸难以进一步微缩，从而限制了铁电存储器的存储密度的提升。The first type, the memory cell includes a circuit structure based on ferroelectric capacitor (ferro electric capacitor), as shown in Figure 3a, the memory cell has a 1T1C (1-transistor-1-capacitor) structure, that is, a memory cell includes a ferroelectric Capacitor C and a transistor T, the source of the transistor T is electrically connected to the bit line (bit line, BL), the drain is electrically connected to an electrode plate of the ferroelectric capacitor C, and the gate is electrically connected to the word line (WL) The other electrode plate of the ferroelectric capacitor C is electrically connected to the plate line (PL). The reading of the stored information in the memory cell shown in Figure 3a is based on the polarization reversal current of the ferroelectric capacitor. However, in order to generate a sufficiently large read current, the ferroelectric capacitor C in the memory cell needs to have a larger size, which leads to The physical size of the storage unit is difficult to shrink further, thus limiting the improvement of the storage density of the ferroelectric memory.

第二种，存储单元包括基于铁电场效应晶体管(ferroelectric field-effect transistor，FeFET)的电路结构，如图3b所示，该存储单元包括铁电场效应晶体管T，铁电场效应晶体管T的源极与源线(source line，SL)电连接，漏极与位线BL电连接，栅极与字线WL电连接，铁电场效应晶体管T的栅介质层(也可以称为铁电层)的材料为铁电材料例如二氧化铪(HfO ₂)等。铁电场效应晶体管T通过电压脉冲改变铁电层的极性存储数据，并通过读取晶体管的源漏电流来得到存储数据，其读取机制为非破坏性，并具有较高的密度。然而，由于铁电场效应晶体管T中铁电层的界面层因素，因而其数据开关特性较差。 In the second type, the memory cell includes a circuit structure based on a ferroelectric field-effect transistor (ferroelectric field-effect transistor, FeFET). As shown in FIG. The source line (source line, SL) is electrically connected, the drain is electrically connected to the bit line BL, and the gate is electrically connected to the word line WL. The material of the gate dielectric layer (also called a ferroelectric layer) of the ferroelectric field effect transistor T is Ferroelectric materials such as hafnium dioxide (HfO ₂ ) and the like. The ferroelectric field effect transistor T stores data by changing the polarity of the ferroelectric layer through voltage pulses, and obtains the stored data by reading the source and drain currents of the transistor. The read mechanism is non-destructive and has a high density. However, due to the interface layer factor of the ferroelectric layer in the ferroelectric field effect transistor T, its data switching characteristics are poor.

第三种，存储单元包括基于铁电存储晶体管(ferroelectric memory field-effect transistor，FeMFET)的电路结构，如图3c所示，该存储单元包括晶体管T和铁电电容C，该晶体管T是常规晶体管，不是铁电场效应晶体管，晶体管T的栅极与铁电电容C的一个电极板电连接，源极与源线SL电连接，漏极与位线BL电连接，铁电电容C的另一个电极板与字线WL电连接。基于铁电存储晶体管的存储单元结合了基于铁电电容的存储单元(即上述第一种存储单元)以及基于铁电场效应晶体管的存储单元(即上述第二种存储单元)的优点，使得基于铁电存储晶体管的电路结构的存储单元既具有较好的数据开关特性，又具有较好的尺寸微缩能力。然而，在读操作时，晶体管T的栅极和铁电电容C的电极板连接处形成的浮空节点A存在漏电流，而且在写操作过程中，基于晶体管T和铁电电容C的连接关系，由于铁电电容C会分压，因此需要字线WL提供较高的写操作电压。The third type, the memory cell includes a circuit structure based on a ferroelectric memory field-effect transistor (FeMFET), as shown in Figure 3c, the memory cell includes a transistor T and a ferroelectric capacitor C, and the transistor T is a conventional transistor , not a ferroelectric field effect transistor, the gate of the transistor T is electrically connected to one electrode plate of the ferroelectric capacitor C, the source is electrically connected to the source line SL, the drain is electrically connected to the bit line BL, and the other electrode of the ferroelectric capacitor C The plate is electrically connected to the word line WL. The storage unit based on the ferroelectric storage transistor combines the advantages of the storage unit based on the ferroelectric capacitor (that is, the first storage unit) and the storage unit based on the ferroelectric field effect transistor (that is, the second storage unit above), so that the storage unit based on ferroelectric The storage unit with the circuit structure of the electric storage transistor not only has better data switching characteristics, but also has better size reduction capability. However, during the read operation, there is a leakage current at the floating node A formed at the connection between the gate of the transistor T and the electrode plate of the ferroelectric capacitor C, and during the write operation, based on the connection relationship between the transistor T and the ferroelectric capacitor C, Since the ferroelectric capacitor C divides the voltage, the word line WL needs to provide a higher write operation voltage.

第四种，存储单元包括基于2T1C(2-transistor-1-capacitor)的电路结构，此时，存储单元也可以称为增益单元(gain cell)，如图3d所示，该存储单元包括第一晶体管T1、第二晶体管T2和铁电电容C，第一晶体管T1的源极与源线SL电连接，漏极与接地端GND电连接，栅极与铁电电容C的一个电极板电连接，铁电电容的另一个电极板与字线WL电连接，第二晶体管T2的源极与第一晶体管T1的栅极电连接，漏极与位线BL电连接，栅极与板线PL电连接。基于2T1C的存储单元具有与基于铁电存储晶体管的存储单元(即上述第三种存储单元)类似的优点，但是在写操作时，由于没有铁电电容C的分压，写操作电压较低，而在读操作时，通过引入额外的第一晶体管(也可以称为预充晶体管)T1，浮空节点A的电位可在读操作之前被设定至固定值，从而可以避免存储信息的流失。然而，由于引入了额外的预充晶体管T1，因而导致基于2T1C的存储单元的单比特面积较大，从而导致存储密度较低。Fourth, the storage unit includes a circuit structure based on 2T1C (2-transistor-1-capacitor), at this time, the storage unit can also be called a gain cell (gain cell), as shown in Figure 3d, the storage unit includes the first The transistor T1, the second transistor T2 and the ferroelectric capacitor C, the source of the first transistor T1 is electrically connected to the source line SL, the drain is electrically connected to the ground terminal GND, and the gate is electrically connected to an electrode plate of the ferroelectric capacitor C, The other electrode plate of the ferroelectric capacitor is electrically connected to the word line WL, the source of the second transistor T2 is electrically connected to the gate of the first transistor T1, the drain is electrically connected to the bit line BL, and the gate is electrically connected to the plate line PL . The memory cell based on 2T1C has similar advantages to the memory cell based on the ferroelectric storage transistor (that is, the third memory cell mentioned above), but during the write operation, since there is no voltage division of the ferroelectric capacitor C, the write operation voltage is low, In the read operation, by introducing an additional first transistor (also called a pre-charge transistor) T1, the potential of the floating node A can be set to a fixed value before the read operation, thereby avoiding the loss of stored information. However, due to the introduction of an additional pre-charge transistor T1, the 2T1C-based memory cell has a larger single-bit area, resulting in a lower storage density.

为了解决上述相关技术提供的铁电存储器中存储单元的面积较大，存储密度较低的问题，本申请实施例还提供一种铁电存储器，该铁电存储器可以应用于上述的电子设备1中，例如可以作为上述电子设备1中的内部存储器112。以下通过几个具体的实施例对本申请提供的铁电存储器的结构进行示例性介绍。In order to solve the problem of large storage unit area and low storage density in the ferroelectric memory provided by the above-mentioned related technology, the embodiment of the present application also provides a ferroelectric memory, which can be applied to the above-mentioned electronic device 1 , for example, can be used as the internal memory 112 in the above-mentioned electronic device 1 . The structure of the ferroelectric memory provided by the present application will be exemplarily introduced below through several specific embodiments.

实施例一Embodiment one

在本实施例一中，如图4a、图4b和图4c所示，铁电存储器10包括：阵列分布的多个存储单元100、多条平行排列的第一位线BL、多条平行排列的第二位线BL＇、多条平行排列的第一字线WL、多条平行排列的第二字线WL＇、多条平行排列的源线SL以及多条平行排列的控制线(control line，CL)。In the first embodiment, as shown in FIG. 4a, FIG. 4b and FIG. 4c, the ferroelectric memory 10 includes: a plurality of memory cells 100 distributed in an array, a plurality of first bit lines BL arranged in parallel, and a plurality of first bit lines BL arranged in parallel. The second bit line BL', a plurality of first word lines WL arranged in parallel, a plurality of second word lines WL' arranged in parallel, a plurality of source lines SL arranged in parallel, and a plurality of control lines (control lines, CL).

图4a为铁电存储器10的立体结构示意图，图4b为图4a中沿AA向的剖面示意图，图4c为图4a所示的铁电存储器10中一个存储单元100的电路结构示意图。4a is a schematic perspective view of the three-dimensional structure of the ferroelectric memory 10, FIG. 4b is a schematic cross-sectional view along AA in FIG. 4a, and FIG. 4c is a schematic circuit structure diagram of a memory cell 100 in the ferroelectric memory 10 shown in FIG.

在一些示例中，如图4a所示，多条第一位线BL和多条第二位线BL＇相互平行，多条第一字线WL、多条第二字线WL＇以及多条控制线CL相互平行，多条第一位线BL和多条第一字线WL相交。In some examples, as shown in FIG. 4a, a plurality of first bit lines BL and a plurality of second bit lines BL' are parallel to each other, a plurality of first word lines WL, a plurality of second word lines WL' and a plurality of control The lines CL are parallel to each other, and the plurality of first bit lines BL and the plurality of first word lines WL intersect.

上述“多条第一位线BL和多条第一字线WL相交”，可以是第一位线BL和第一字线WL在同一平面上的投影相互垂直，也可以是第一位线BL和第一字线WL在同一平面上的投影之间的夹角为锐角。The above-mentioned "multiple first bit lines BL intersect with multiple first word lines WL" may mean that the projections of the first bit lines BL and the first word lines WL on the same plane are perpendicular to each other, or that the first bit lines BL The included angle with the projection of the first word line WL on the same plane is an acute angle.

在本实施例一中，多条源线SL和多条第一位线BL相交。此处，可以是源线SL和第一位线BL在同一平面上的投影相互垂直，也可以是源线SL和第一位线BL在同一平面上的投影之间的夹角为锐角。In the first embodiment, multiple source lines SL intersect with multiple first bit lines BL. Here, the projections of the source line SL and the first bit line BL on the same plane may be perpendicular to each other, or the included angle between the projections of the source line SL and the first bit line BL on the same plane may be an acute angle.

上述存储单元100包括读取晶体管(sense transistor，STR)、预充晶体管(precharge transistor，PTR)以及至少一个电容组。The above storage unit 100 includes a sense transistor (sense transistor, STR), a precharge transistor (precharge transistor, PTR) and at least one capacitor bank.

上述读取晶体管STR包括第一极、第二极和栅极(gate，G)，读取晶体管STR的第一极与第一位线BL电连接，读取晶体管STR的第二极与源线SL电连接，读取晶体管STR的栅极与预充晶体管PTR的第一极电连接；其中，读取晶体管STR的第一极和读取晶体管STR的第二极中一个为源极(source，S)，一个为漏极(drain，D)。The read transistor STR includes a first pole, a second pole and a gate (gate, G), the first pole of the read transistor STR is electrically connected to the first bit line BL, and the second pole of the read transistor STR is connected to the source line SL is electrically connected, and the gate of the read transistor STR is electrically connected to the first pole of the precharge transistor PTR; wherein, one of the first pole of the read transistor STR and the second pole of the read transistor STR is a source (source, S), one is the drain (drain, D).

此处，可以是读取晶体管STR的第一极为源极，读取晶体管STR的第二极为漏极；也可以是读取晶体管STR的第一极为漏极，读取晶体管STR的第二极为源极。Here, the first pole of the read transistor STR may be the source, and the second pole of the read transistor STR may be the drain; or the first pole of the read transistor STR may be the drain, and the second pole of the read transistor STR may be the source pole.

此外，读取晶体管STR可以是N型晶体管，也可以是P型晶体管。In addition, the reading transistor STR may be an N-type transistor or a P-type transistor.

需要说明的是，在一些示例中，第一位线BL的部分可以用于作为读取晶体管STR的第一极，在此情况下，可以简化铁电存储器10的结构；在另一些示例中，第一位线BL和读取晶体管STR的第一极是单独制作的两个部分。同样的，在一些示例中，源线SL的部分用于作为读取晶体管STR的第二极，在此情况下，可以简化铁电存储器10的结构；在另一些示例中，源线SL和读取晶体管STR的第二极是单独制作的两个部分。It should be noted that, in some examples, part of the first bit line BL can be used as the first pole of the read transistor STR, in this case, the structure of the ferroelectric memory 10 can be simplified; in other examples, The first bit line BL and the first pole of the read transistor STR are two parts made separately. Similarly, in some examples, part of the source line SL is used as the second pole of the read transistor STR, in this case, the structure of the ferroelectric memory 10 can be simplified; in other examples, the source line SL and the read transistor STR The second pole of the transistor STR is two parts made separately.

如图5a所示，读取晶体管STR为垂直沟道晶体管(channel all around transistor，CAA transistor)，读取晶体管STR的第一极101设置在读取晶体管STR的第二极102沿第一方向X的一侧；在一些示例中，读取晶体管STR的第一极101和读取晶体管STR的第二极102沿第一方向X层叠设置。垂直沟道晶体管的栅极103包括栅基底1031、以及与栅基底1031接触且沿第一方向X延伸的栅极柱1032，垂直沟道晶体管的第一极101和垂直沟道晶体管的第二极102设置在垂直沟道晶体管的栅基底1031沿第一方向X的同一侧。在一些示例中，垂直沟道晶体管的栅基底1031与垂直沟道晶体管的栅极柱1032垂直设置。As shown in Figure 5a, the read transistor STR is a vertical channel transistor (channel all around transistor, CAA transistor), the first pole 101 of the read transistor STR is arranged on the second pole 102 of the read transistor STR along the first direction X In some examples, the first pole 101 of the read transistor STR and the second pole 102 of the read transistor STR are stacked along the first direction X. The gate 103 of the vertical channel transistor includes a gate substrate 1031, and a gate column 1032 that is in contact with the gate substrate 1031 and extends along the first direction X, the first pole 101 of the vertical channel transistor and the second pole of the vertical channel transistor 102 is disposed on the same side along the first direction X as the gate substrate 1031 of the vertical channel transistor. In some examples, the gate base 1031 of the vertical channel transistor is vertically disposed with the gate pillar 1032 of the vertical channel transistor.

请继续参考图5a，上述垂直沟道晶体管还包括：半导体层104、栅介质层105以及第一绝缘介质层106；半导体层104包括第一部分，第一部分沿第一方向X延伸；垂直沟道晶体管的半导体层104至少设置在栅极柱1032的侧面，垂直沟道晶体管的第一极101和垂直沟道晶体管的第二极102分别与垂直沟道晶体管的半导体层104接触；垂直沟道晶体管的栅介质层105设置在垂直沟道晶体管的半导体层104和垂直沟道晶体管的栅极103之间，用于将垂直沟道晶体管的半导体层104和垂直沟道晶体管的栅极103隔开；垂直沟道晶体管的第一绝缘介质层106设置在垂直沟道晶体管的第一极101和垂直沟道晶体管的第二极102之间，用于将垂直沟道晶体管的第一极101和垂直沟道晶体管的第二极102隔开。Please continue to refer to FIG. 5a, the above-mentioned vertical channel transistor further includes: a semiconductor layer 104, a gate dielectric layer 105, and a first insulating dielectric layer 106; the semiconductor layer 104 includes a first part, and the first part extends along the first direction X; the vertical channel transistor The semiconductor layer 104 of the vertical channel transistor is disposed at least on the side of the gate column 1032, and the first pole 101 of the vertical channel transistor and the second pole 102 of the vertical channel transistor are respectively in contact with the semiconductor layer 104 of the vertical channel transistor; The gate dielectric layer 105 is arranged between the semiconductor layer 104 of the vertical channel transistor and the gate 103 of the vertical channel transistor, and is used to separate the semiconductor layer 104 of the vertical channel transistor from the gate 103 of the vertical channel transistor; The first insulating medium layer 106 of the channel transistor is arranged between the first pole 101 of the vertical channel transistor and the second pole 102 of the vertical channel transistor, for connecting the first pole 101 of the vertical channel transistor to the vertical channel The second poles 102 of the transistors are spaced apart.

在一些示例中，如图5b所示，垂直沟道晶体管的半导体层104仅包括第一部分，第一部分沿第一方向X延伸，即垂直沟道晶体管的半导体层104只设置在栅极柱1032的侧面。在另一些示例中，垂直沟道晶体管的半导体层104不仅包括第一部分，还包括其它部分。例如，如图5c所示，垂直沟道晶体管的半导体层104不仅设置在栅极柱1032的侧面，垂直沟道晶体管的半导体层104还由栅极柱1032的侧面延伸至栅极柱1032远离栅基底1031的一侧。又例如，如图5d所示，垂直沟道晶体管的半导体层104不仅设置在栅极柱1032的侧面，垂直沟道晶体管的半导体层104还由栅极柱1032的侧面延伸至栅基底1031的表面。又例如，如图5a所示，垂直沟道晶体管的半导体层104不仅设置在栅极柱1032的侧面，垂直沟道晶体管的半导体层104还由栅极柱1032的侧面延伸至栅极柱1032远离栅基底1031的一侧、以及由栅极柱1032的侧面延伸至栅基底1031的表面。In some examples, as shown in FIG. 5b, the semiconductor layer 104 of the vertical channel transistor only includes a first portion, and the first portion extends along the first direction X, that is, the semiconductor layer 104 of the vertical channel transistor is only disposed on the gate pillar 1032. side. In other examples, the semiconductor layer 104 of the vertical channel transistor includes not only the first portion but also other portions. For example, as shown in FIG. 5c, the semiconductor layer 104 of the vertical channel transistor is not only disposed on the side of the gate column 1032, the semiconductor layer 104 of the vertical channel transistor also extends from the side of the gate column 1032 to the gate column 1032 away from the gate. One side of the base 1031. For another example, as shown in FIG. 5d, the semiconductor layer 104 of the vertical channel transistor is not only disposed on the side of the gate pillar 1032, but the semiconductor layer 104 of the vertical channel transistor also extends from the side of the gate pillar 1032 to the surface of the gate substrate 1031. . For another example, as shown in FIG. 5a, the semiconductor layer 104 of the vertical channel transistor is not only disposed on the side of the gate column 1032, but the semiconductor layer 104 of the vertical channel transistor also extends from the side of the gate column 1032 to the gate column 1032 away from One side of the gate substrate 1031 extends from the side of the gate pillar 1032 to the surface of the gate substrate 1031 .

在此基础上，垂直沟道晶体管的半导体层104可以绕栅极柱1032的侧面设置一圈，包围栅极柱1032的侧面；垂直沟道晶体管的半导体层104也可以设置在栅极柱1032的侧面，但未包围栅极柱1032的侧面。On this basis, the semiconductor layer 104 of the vertical channel transistor can be arranged around the side of the gate column 1032 to surround the side of the gate column 1032; the semiconductor layer 104 of the vertical channel transistor can also be arranged on the side of the gate column 1032 sides, but not surrounding the sides of gate pillar 1032 .

上述栅介质层105的材料和第一绝缘介质层106的材料例如可以为二氧化硅(SiO ₂)、氧化铝(Al ₂O ₃)、二氧化铪(HfO ₂)、氧化锆(ZrO ₂)、二氧化钛(TiO ₂)、三氧化二钇(Y ₂O ₃)和氮化硅(Si ₃N ₄)等绝缘材料中的一种或多种。 The material of the gate dielectric layer 105 and the first insulating dielectric layer 106 can be, for example, silicon dioxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ). One or more of insulating materials such as titanium dioxide (TiO ₂ ), yttrium trioxide (Y ₂ O ₃ ) and silicon nitride (Si ₃ N ₄ ).

上述栅极103、第一极101和第二极102的材料均为导电材料，例如金属材料。示例的，栅极103、第一极101和第二极102的材料可以为氮化钛(TiN)、钛(Ti)、金(Au)、钨(W)、钼(Mo)、氧化铟锡(In-Ti-O，ITO)、铝(Al)、铜(Cu)、钌(Ru)、银(Ag)等导电材料中的一种或多种。The materials of the gate 103 , the first electrode 101 and the second electrode 102 are all conductive materials, such as metal materials. For example, the materials of the gate 103, the first pole 101 and the second pole 102 can be titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide One or more of conductive materials such as (In-Ti-O, ITO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), etc.

上述半导体层104的材料例如可以为硅(Si)、多晶硅(poly-Si，p-Si)、非晶硅(amorphous-Si，a-Si)、铟镓锌氧化物(In-Ga-Zn-O，IGZO)多元化合物、氧化锌(ZnO)、ITO、二氧化钛(TiO ₂)、二硫化钼(MoS ₂)等半导体材料中的一种或多种。 The material of the semiconductor layer 104 can be, for example, silicon (Si), polysilicon (poly-Si, p-Si), amorphous silicon (amorphous-Si, a-Si), indium gallium zinc oxide (In-Ga-Zn- One or more of semiconductor materials such as O, IGZO) compound, zinc oxide (ZnO), ITO, titanium dioxide (TiO ₂ ), molybdenum disulfide (MoS ₂ ), etc.

本申请实施例以第一方向X为竖直方向X，垂直于第一方向X的方向为水平方向为例，相对于平面晶体管中的第一极101和第二极102同层设置，也即平面晶体管的第一极101和第二极102沿水平方向同层设置，且平面晶体管的半导体层104沿水平方向延伸而言，由于本实施例一中，读取晶体管STR为垂直沟道晶体管，读取晶体管STR的第一极101设置在读取晶体管STR的第二极102沿竖直方向X的一侧，且读取晶体管STR的半导体层104包括第一部分，第一部分沿竖直方向X延伸，因此读取晶体管STR在水平方向上的尺寸较小，从而可以使得存储单元100的尺寸减小。In the embodiment of the present application, the first direction X is the vertical direction X, and the direction perpendicular to the first direction X is the horizontal direction as an example. Compared with the first pole 101 and the second pole 102 in the planar transistor, they are arranged on the same layer, that is, The first pole 101 and the second pole 102 of the planar transistor are arranged on the same layer along the horizontal direction, and the semiconductor layer 104 of the planar transistor extends along the horizontal direction, since in the first embodiment, the reading transistor STR is a vertical channel transistor, The first pole 101 of the read transistor STR is disposed on one side of the second pole 102 of the read transistor STR along the vertical direction X, and the semiconductor layer 104 of the read transistor STR includes a first portion extending along the vertical direction X , so the size of the read transistor STR in the horizontal direction is smaller, so that the size of the memory cell 100 can be reduced.

上述预充晶体管PTR包括第一极、第二极和栅极，预充晶体管PTR的第一极与读取晶体管STR的栅极电连接，预充晶体管PTR的第二极与第二位线BL＇电连接，预充晶体管PTR的栅极与控制线CL电连接；其中，预充晶体管PTR的第一极和预充晶体管PTR的第二极中一个为源极S，另一个为漏极D。The above-mentioned pre-filling transistor PTR includes a first pole, a second pole and a gate, the first pole of the pre-filling transistor PTR is electrically connected to the gate of the read transistor STR, and the second pole of the pre-filling transistor PTR is connected to the second bit line BL 'Electrically connected, the gate of the pre-charge transistor PTR is electrically connected to the control line CL; wherein, one of the first pole of the pre-charge transistor PTR and the second pole of the pre-charge transistor PTR is the source S, and the other is the drain D .

此处，可以是预充晶体管PTR的第一极为源极，预充晶体管PTR的第二极为漏极；也可以是预充晶体管PTR的第一极为漏极，预充晶体管PTR的第二极为源极。Here, the first pole of the precharge transistor PTR can be the source, and the second pole of the precharge transistor PTR can be the drain; it can also be the first pole of the precharge transistor PTR, and the second pole of the precharge transistor PTR can be the source. pole.

此外，预充晶体管PTR可以是N型晶体管，也可以是P型晶体管。In addition, the precharge transistor PTR may be an N-type transistor or a P-type transistor.

需要说明的是，在一些示例中，第二位线BL＇的部分用于作为预充晶体管PTR的第二极，在此情况下，可以简化铁电存储器10的结构；在另一些示例中，第二位线BL＇和预充晶体管PTR的第二极是单独制作的两个部分。It should be noted that, in some examples, part of the second bit line BL' is used as the second pole of the precharge transistor PTR, in this case, the structure of the ferroelectric memory 10 can be simplified; in other examples, The second bit line BL' and the second pole of the precharge transistor PTR are two parts made separately.

如图5a所示，预充晶体管PTR为垂直沟道晶体管，预充晶体管PTR的第一极101设置在预充晶体管PTR的第二极102沿第一方向X的一侧；在一些示例中，预充晶体管PTR的第一极101和预充晶体管PTR的第二极102沿第一方向X层叠设置，预充晶体管PTR的半导体层104包括第二部分，第二部分沿第一方向X延伸。在预充晶体管PTR为垂直沟道晶体管的情况下，预充晶体管PTR可以参考上述读取晶体管STR的结构，此处不再赘述。As shown in FIG. 5a, the precharge transistor PTR is a vertical channel transistor, and the first pole 101 of the precharge transistor PTR is arranged on one side of the second pole 102 of the precharge transistor PTR along the first direction X; in some examples, The first pole 101 of the precharge transistor PTR and the second pole 102 of the precharge transistor PTR are stacked along the first direction X, and the semiconductor layer 104 of the precharge transistor PTR includes a second portion extending along the first direction X. In the case that the pre-charge transistor PTR is a vertical channel transistor, the pre-charge transistor PTR can refer to the structure of the read transistor STR above, which will not be repeated here.

需要说明的是，读取晶体管STR的结构和预充晶体管PTR的结构可以相同，也可以不相同。It should be noted that the structures of the read transistor STR and the precharge transistor PTR may be the same or different.

本申请实施例以第一方向X为竖直方向X，垂直于第一方向X的方向为水平方向为例，相对于平面晶体管中的第一极101和第二极102沿水平方向同层设置，且平面晶体管的半导体层104沿水平方向延伸而言，由于本实施例一中，预充晶体管PTR为垂直沟道晶体管，预充晶体管PTR的第一极101设置在预充晶体管PTR的第二极102沿竖直方向的一侧，且预充晶体管PTR的半导体层104包括第二部分，第二部分沿竖直方向延伸，因此预充晶体管PTR在水平方向上的尺寸较小，从而可以使得存储单元100的尺寸较小。In the embodiment of the present application, the first direction X is the vertical direction X, and the direction perpendicular to the first direction X is the horizontal direction as an example. Compared with the first pole 101 and the second pole 102 in the planar transistor, they are arranged in the same layer along the horizontal direction. , and the semiconductor layer 104 of the planar transistor extends in the horizontal direction, since in the first embodiment, the pre-charge transistor PTR is a vertical channel transistor, the first pole 101 of the pre-charge transistor PTR is arranged on the second electrode of the pre-charge transistor PTR One side of the pole 102 in the vertical direction, and the semiconductor layer 104 of the pre-charge transistor PTR includes a second portion extending in the vertical direction, so the size of the pre-charge transistor PTR in the horizontal direction is relatively small, so that The storage unit 100 is small in size.

在此基础上，上述预充晶体管PTR沿第一方向X可以与读取晶体管STR层叠设置，也可以不与读取晶体管STR层叠设置。On this basis, the above-mentioned pre-charge transistor PTR may be stacked with the read transistor STR along the first direction X, or may not be stacked with the read transistor STR.

此处，沿第一方向X，可以是预充晶体管PTR设置在上方，读取晶体管STR设置在下方，即先制作读取晶体管STR，再制作预充晶体管PTR；也可以是预充晶体管PTR设置在下方，读取晶体管STR设置在上方，即先制作预充晶体管PTR，再制作读取晶体管STR。Here, along the first direction X, the precharge transistor PTR can be arranged at the top, and the read transistor STR can be arranged at the bottom, that is, the read transistor STR is fabricated first, and then the precharge transistor PTR is fabricated; or the precharge transistor PTR can be arranged At the bottom, the read transistor STR is arranged at the top, that is, the precharge transistor PTR is fabricated first, and then the read transistor STR is fabricated.

在预充晶体管PTR沿第一方向X与读取晶体管STR层叠设置的情况下，读取晶体管STR和预充晶体管PTR沿第一方向X的投影可以是完全重叠，也可以部分重叠。In the case where the pre-charge transistor PTR is stacked with the read transistor STR along the first direction X, the projections of the read transistor STR and the pre-charge transistor PTR along the first direction X can be completely overlapped or partially overlapped.

以第一方向X为竖直方向X，垂直于第一方向X的方向为水平方向为例，相对于预充晶体管PTR和读取晶体管STR沿水平方向设置而言，由于本实施例一中，预充晶体管PTR沿竖直方向X与读取晶体管STR层叠设置，即预充晶体管PTR与读取晶体管STR进行三维堆叠，因此在水平方向上，可以减小预充晶体管PTR和读取晶体管STR所占的面积，进而可以减小存储单元100所占的面积。Taking the first direction X as the vertical direction X, and the direction perpendicular to the first direction X as the horizontal direction as an example, compared to the arrangement of the pre-charge transistor PTR and the read transistor STR along the horizontal direction, since in the first embodiment, The precharge transistor PTR is stacked with the read transistor STR along the vertical direction X, that is, the precharge transistor PTR and the read transistor STR are three-dimensionally stacked, so in the horizontal direction, the burden of the precharge transistor PTR and the read transistor STR can be reduced. The area occupied by the storage unit 100 can be further reduced.

如图4b所示，上述至少一个电容组107中的每个电容组107包括沿第一方向X 层叠设置且电连接的第一电容C1和第二电容C2；第一电容C1和第二电容C2均包括第一电极板1071和第二电极板1072，第一电容C1和第二电容C2还包括设置在第一电极板1071和第二电极板1072之间的绝缘材料1073。在本实施例一中，设置在第一电极板1071和第二电极板1072之间的绝缘材料1073为铁电材料，在此情况下，第一电容C1和第二电容C2为铁电电容，这样一来，本实施例一提供的铁电存储器10中的存储单元100可以基于铁电电容的特性来存储信息。As shown in FIG. 4b, each capacitor group 107 in the at least one capacitor group 107 includes a first capacitor C1 and a second capacitor C2 that are stacked and electrically connected along the first direction X; the first capacitor C1 and the second capacitor C2 Both include a first electrode plate 1071 and a second electrode plate 1072 , and the first capacitor C1 and the second capacitor C2 further include an insulating material 1073 disposed between the first electrode plate 1071 and the second electrode plate 1072 . In the first embodiment, the insulating material 1073 disposed between the first electrode plate 1071 and the second electrode plate 1072 is a ferroelectric material, in this case, the first capacitor C1 and the second capacitor C2 are ferroelectric capacitors, In this way, the storage unit 100 in the ferroelectric memory 10 provided in Embodiment 1 can store information based on the characteristics of the ferroelectric capacitor.

上述第一电容C1的第一电极板1071和第二电容C2的第一电极板1071均与读取晶体管STR的栅极以及预充晶体管PTR的第一极101电连接，第一电容C1的第二电极板1072与第一字线WL电连接，第二电容C2的第二电极板与第二字线WL＇电连接。Both the first electrode plate 1071 of the first capacitor C1 and the first electrode plate 1071 of the second capacitor C2 are electrically connected to the gate of the read transistor STR and the first pole 101 of the pre-charge transistor PTR, and the first electrode plate 101 of the first capacitor C1 The second electrode plate 1072 is electrically connected to the first word line WL, and the second electrode plate of the second capacitor C2 is electrically connected to the second word line WL′.

应当理解到，对于一个存储单元100中电容组107的数量不进行限定，可以是一个，也可以是两个或两个以上。在此基础上，对于不同存储单元100中电容组107的数量可以相同，也可以不相同。存储单元100中电容组107的数量越多，存储单元100存储的信息的比特数越多。It should be understood that the number of capacitor banks 107 in one storage unit 100 is not limited, and may be one, or two or more. On this basis, the number of capacitor banks 107 in different storage units 100 may be the same or different. The more the number of capacitor banks 107 in the storage unit 100 is, the more bits of information stored in the storage unit 100 will be.

可以理解的是，与存储单元100电连接的第一字线WL和第二字线WL＇的条数与存储单元100中电容组107的数量相同。It can be understood that the number of the first word lines WL and the second word lines WL′ electrically connected to the memory unit 100 is the same as the number of the capacitor banks 107 in the memory unit 100 .

在此基础上，在一些示例中，存储单元100还可以包括第三电容C3，第三电容C3的位置以及连接关系可以与第一电容C1或第二电容C2相同。On this basis, in some examples, the storage unit 100 may further include a third capacitor C3, and the position and connection relationship of the third capacitor C3 may be the same as that of the first capacitor C1 or the second capacitor C2.

基于上述可知，本申请提供的存储单元100为2TnC存储单元，即每个存储单元100包括2个晶体管(即预充晶体管PTR和读取晶体管STR)和n个电容。Based on the above, it can be seen that the memory cells 100 provided in the present application are 2TnC memory cells, that is, each memory cell 100 includes 2 transistors (ie, a precharge transistor PTR and a read transistor STR) and n capacitors.

需要说明的是，由于第一电容C1的第一电极板1071和第二电容C2的第一电极板1071均与读取晶体管STR的栅极以及预充晶体管PTR的第一极101电连接，因而在一些示例中，第一电容C1的第一电极板1071和第二电容C2的第一电极板1071可以共用。It should be noted that since both the first electrode plate 1071 of the first capacitor C1 and the first electrode plate 1071 of the second capacitor C2 are electrically connected to the gate of the read transistor STR and the first pole 101 of the pre-charge transistor PTR, thus In some examples, the first electrode plate 1071 of the first capacitor C1 and the first electrode plate 1071 of the second capacitor C2 can be shared.

基于此，在一些示例中，如图4b所示，上述存储单元100还包括浮空栅电极(floating gate，FG)109；浮空栅电极109的部分用于作为电容组107中第一电容C1的第一电极板1071和第二电容C2的第一电极板1071，且读取晶体管STR的栅极103以及预充晶体管PTR的第一极101均与浮空栅电极109电连接。Based on this, in some examples, as shown in FIG. 4b, the memory cell 100 further includes a floating gate electrode (floating gate, FG) 109; a part of the floating gate electrode 109 is used as the first capacitor C1 in the capacitor group 107 The first electrode plate 1071 of the second capacitor C2 and the first electrode plate 1071 of the second capacitor C2, and the gate 103 of the reading transistor STR and the first electrode 101 of the pre-charging transistor PTR are all electrically connected to the floating gate electrode 109 .

此处，浮空栅电极109的部分除了作为电容组107中第一电容C1的第一电极板1071和第二电容C2的第一电极板1071外，浮空栅电极109还用于起连接作用，用于将多个电容组107电连接在一起，并将多个电容组107中第一电容C1的第一电极板1071和第二电容C2的第一电极板1071与读取晶体管STR的栅极103以及预充晶体管PTR的第一极101电连接在一起。Here, apart from the part of the floating gate electrode 109 serving as the first electrode plate 1071 of the first capacitor C1 and the first electrode plate 1071 of the second capacitor C2 in the capacitor group 107, the floating gate electrode 109 is also used for connecting , used to electrically connect a plurality of capacitor groups 107 together, and connect the first electrode plate 1071 of the first capacitor C1 and the first electrode plate 1071 of the second capacitor C2 in the plurality of capacitor groups 107 to the gate of the read transistor STR The pole 103 and the first pole 101 of the pre-charge transistor PTR are electrically connected together.

另外，在一些示例中，浮空栅电极109的部分还可以用于作为读取晶体管STR的栅极103。在一些示例中，浮空栅电极109的部分还可以用于作为预充晶体管PTR的第一极101。Additionally, in some examples, part of the floating gate electrode 109 may also be used as the gate 103 of the read transistor STR. In some examples, part of the floating gate electrode 109 may also be used as the first pole 101 of the pre-charge transistor PTR.

相对于分别单独设置第一电容C1的第一电极板1071和第二电容C2的第一电极板1071，在本实施例中，通过设置浮空栅电极109，并利用浮空栅电极109的部分作为电容组107中第一电容C1的第一电极板1071和第二电容C2的第一电极板1071，这样可以简化存储单元100的结构。在此基础上，相对于额外设置连接部将浮空栅电极109与读取晶体管STR的栅极103以及预充晶体管PTR的第一极101电连接而言，利用浮空栅电极109本身与读取晶体管STR的栅极103以及预充晶体管PTR的第一极101电连接可以进一步简化存储单元100的结构。Compared with separately setting the first electrode plate 1071 of the first capacitor C1 and the first electrode plate 1071 of the second capacitor C2, in this embodiment, by setting the floating gate electrode 109 and using the part of the floating gate electrode 109 As the first electrode plate 1071 of the first capacitor C1 and the first electrode plate 1071 of the second capacitor C2 in the capacitor group 107, the structure of the memory unit 100 can be simplified. On this basis, compared to additionally providing a connecting portion to electrically connect the floating gate electrode 109 with the gate 103 of the read transistor STR and the first electrode 101 of the pre-charge transistor PTR, using the floating gate electrode 109 itself to connect with the read The structure of the memory cell 100 can be further simplified by electrically connecting the gate 103 of the transistor STR and the first electrode 101 of the precharge transistor PTR.

在此基础上，在存储单元100包括浮空栅电极109的情况下，在一些示例中，上述第一字线WL与浮空栅电极109相交，第一字线WL与浮空栅电极109相交的部分用于作为第一电容C1的第二电极板1072。利用第一字线WL的部分作为第一电容C1的第二电极板1072，这样无需单独制作第一电容C1的第二电极板1072，从而可以简化存储单元100的结构。On this basis, when the memory cell 100 includes the floating gate electrode 109, in some examples, the first word line WL intersects the floating gate electrode 109, and the first word line WL intersects the floating gate electrode 109 A part of is used as the second electrode plate 1072 of the first capacitor C1. Using part of the first word line WL as the second electrode plate 1072 of the first capacitor C1 does not need to separately manufacture the second electrode plate 1072 of the first capacitor C1, thereby simplifying the structure of the memory cell 100 .

此处，第一字线WL与浮空栅电极109在垂直于第一方向X的平面上的投影可以是相互垂直，也可以是两者之间的夹角为锐角。Here, the projections of the first word line WL and the floating gate electrode 109 on a plane perpendicular to the first direction X may be perpendicular to each other, or the angle between them may be an acute angle.

在另一些示例中，第一电容C1的第二电极板1072和第一字线WL是分别制作的两个部分。In some other examples, the second electrode plate 1072 of the first capacitor C1 and the first word line WL are two parts fabricated separately.

同样的，在存储单元100包括浮空栅电极109的情况下，在一些示例中，上述第二字线WL＇与浮空栅电极109相交，第二字线WL＇与浮空栅电极109相交的部分用于作为第二电容C2的第二电极板1072。利用第二字线WL＇的部分作为第二电容C2的第二电极板1072，这样无需单独制作第二电容C2的第二电极板1072，从而可以简化存储单元100的结构。Similarly, in the case that the memory cell 100 includes the floating gate electrode 109, in some examples, the above-mentioned second word line WL' intersects the floating gate electrode 109, and the second word line WL' intersects the floating gate electrode 109 A part of is used as the second electrode plate 1072 of the second capacitor C2. Using part of the second word line WL' as the second electrode plate 1072 of the second capacitor C2 does not need to separately manufacture the second electrode plate 1072 of the second capacitor C2, thereby simplifying the structure of the memory cell 100 .

此处，第二字线WL＇与浮空栅电极109在垂直于第一方向X的平面上的投影可以是相互垂直，也可以是两者之间的夹角为锐角。Here, the projections of the second word line WL′ and the floating gate electrode 109 on a plane perpendicular to the first direction X may be perpendicular to each other, or the angle between them may be an acute angle.

在另一些示例中，第二电容C2的第二电极板1072和第二字线WL＇是分别制作的两个部分。In some other examples, the second electrode plate 1072 of the second capacitor C2 and the second word line WL' are two parts fabricated separately.

以第一方向X为竖直方向X，垂直于第一方向X的方向为水平方向为例，相对于第一电容C1和第二电容C2沿水平方向同层设置而言，由于本实施例一中，第一电容C1和第二电容C2沿竖直方向X层叠设置，即第一电容C1和第二电容C2进行三维堆叠，因而在水平方向上，可以减小第一电容C1和第二电容C2所占的面积，进而可以进一步减小存储单元100所占的面积。Taking the first direction X as the vertical direction X, and the direction perpendicular to the first direction X as the horizontal direction as an example, compared to the arrangement of the first capacitor C1 and the second capacitor C2 in the same layer along the horizontal direction, due to the first Among them, the first capacitor C1 and the second capacitor C2 are stacked along the vertical direction X, that is, the first capacitor C1 and the second capacitor C2 are three-dimensionally stacked, so in the horizontal direction, the first capacitor C1 and the second capacitor can be reduced The area occupied by C2 can further reduce the area occupied by the storage unit 100 .

可以理解的是，对于电容组107中沿第一方向X层叠设置的第一电容C1和第二电容C2而言，可以是沿第一方向X，第一电容C1和第二电容C2完全重叠；也可以是沿第一方向X，第一电容C1和第二电容C2部分重叠。It can be understood that, for the first capacitor C1 and the second capacitor C2 stacked along the first direction X in the capacitor group 107, along the first direction X, the first capacitor C1 and the second capacitor C2 completely overlap; It may also be that along the first direction X, the first capacitor C1 and the second capacitor C2 partially overlap.

在沿第一方向X，第一电容C1和第二电容C2完全重叠的情况下，在垂直于第一方向X的平面上，可以进一步减小第一电容C1和第二电容C2所占的面积，进而可以进一步减小存储单元100所占的面积。In the case that the first capacitor C1 and the second capacitor C2 completely overlap along the first direction X, on a plane perpendicular to the first direction X, the area occupied by the first capacitor C1 and the second capacitor C2 can be further reduced , so that the area occupied by the memory unit 100 can be further reduced.

应当理解到，每条第一位线BL和每条第二位线BL＇可以与沿第一位线BL和第二位线BL＇的延伸方向排列的m个存储单元100电连接；其中，m≥1，m为正整数。每条第一字线WL、每条第二字线WL＇以及每条控制线CL可以与沿第一字线WL、第二字线WL＇以及控制线CL的延伸方向排列的p个存储单元100电连接；其中，p≥1，p为正整数。It should be understood that each first bit line BL and each second bit line BL' may be electrically connected to m memory cells 100 arranged along the extending direction of the first bit line BL and the second bit line BL'; wherein, m≥1, m is a positive integer. Each first word line WL, each second word line WL' and each control line CL can be associated with p memory cells arranged along the extending direction of the first word line WL, the second word line WL' and the control line CL 100 electrical connections; wherein, p≥1, p is a positive integer.

需要说明的是，在一些示例中，与同一个存储单元100电连接的第一位线BL和第二位线BL＇电连接。在此情况下，可以通过一个电压端同时向第一位线BL和第二位线BL＇提供电压，这样可以简化铁电存储器10的结构。It should be noted that, in some examples, the first bit line BL and the second bit line BL' electrically connected to the same memory cell 100 are electrically connected. In this case, voltages can be supplied to the first bit line BL and the second bit line BL' simultaneously through one voltage terminal, which can simplify the structure of the ferroelectric memory 10 .

在另一些示例中，与同一个存储单元100电连接的第一位线BL和第二位线BL＇相互不电连接。在此情况下，可以通过两个电压端分别向第一位线BL和第二位线BL＇提供电压，施加到第一位线BL上的电压和施加到第二位线BL＇上的电压可以相同，也可以不相同。由于施加到第一位线BL上的电压和施加到第二位线BL＇上的电压可以灵活进行调整，从而提高了铁电存储器10应用的灵活性。In some other examples, the first bit line BL and the second bit line BL' electrically connected to the same memory cell 100 are not electrically connected to each other. In this case, voltages can be supplied to the first bit line BL and the second bit line BL' respectively through two voltage terminals, the voltage applied to the first bit line BL and the voltage applied to the second bit line BL' Can be the same or different. Since the voltage applied to the first bit line BL and the voltage applied to the second bit line BL' can be flexibly adjusted, the application flexibility of the ferroelectric memory 10 is improved.

在与同一个存储单元100电连接的第一位线BL和第二位线BL＇电连接的情况下，如图4b所示，第一位线BL和第二位线BL＇可以通过位线接触通孔(BL pickup)108电连接。在此基础上，与同一个存储单元100电连接的第一位线BL和第二位线BL＇可以每间隔一段距离通过位线接触通孔108电连接，示例的，与同一个存储单元100电连接的第一位线BL和第二位线BL＇可以每间隔t个存储单元100通过位线接触通孔108电连接在一起。In the case where the first bit line BL and the second bit line BL' are electrically connected to the same memory cell 100, as shown in FIG. 4b, the first bit line BL and the second bit line BL' can pass through the bit line Contact vias (BL pickups) 108 are electrically connected. On this basis, the first bit line BL and the second bit line BL' electrically connected to the same memory cell 100 can be electrically connected through bit line contact vias 108 at intervals, for example, the same memory cell 100 The electrically connected first bit line BL and the second bit line BL′ can be electrically connected together through the bit line contact via hole 108 at intervals of t memory cells 100 .

基于上述，以下以一个存储单元100为例对铁电存储器10的写操作过程和读操作过程进行详细说明。Based on the above, the writing operation process and the reading operation process of the ferroelectric memory 10 will be described in detail below by taking one memory cell 100 as an example.

写操作过程：参考图4c，以在第一电容C1中存储逻辑信息为例，向与待写入存储单元100电连接的控制线CL提供控制信号，控制预充晶体管PTR导通；若向与待写入存储单元100电连接的第二位线BL＇施加电压0，向与待写入第一电容C1电连接的第一字线WL施加电压Vdd，则可以写入第一逻辑信息例如“0”；若向与待写入存储单元100电连接的第二位线BL＇提供电压Vdd，向与待写入第一电容C1电连接的第一字线WL施加电压0，则可以写入第二逻辑信息“1”。Writing operation process: Referring to FIG. 4c, taking the storage of logic information in the first capacitor C1 as an example, a control signal is provided to the control line CL electrically connected to the storage unit 100 to be written to control the conduction of the pre-charge transistor PTR; The voltage 0 is applied to the second bit line BL' electrically connected to the memory cell 100 to be written, and the voltage Vdd is applied to the first word line WL electrically connected to the first capacitor C1 to be written, so that the first logic information such as " 0"; if a voltage Vdd is provided to the second bit line BL' electrically connected to the memory cell 100 to be written, and a voltage 0 is applied to the first word line WL electrically connected to the first capacitor C1 to be written, then it is possible to write The second logic information is "1".

读操作过程：参考图4c，以读取第一电容C1中存储的逻辑信息为例，向与待读取存储单元100电连接的控制线CL提供控制信号，控制预充晶体管PTR导通，向与待读取存储单元100电连接的第二位线BL＇提供电压1/2Vdd，并通过预充晶体管PTR将电压1/2Vdd预充到预充晶体管PTR的第一极和读取晶体管STR的栅极；向与待读取第一电容C1电连接的第一字线WL施加电压Vdd，其它第一字线WL以及所有的第二字线WL＇施加接地电压。由于若第一电容C1中存储的是第一逻辑信息例如“0”，则第一电容C1的第一电极板的电压会降低，即预充晶体管PTR的第一极与读取晶体管STR的栅极的电压会降低，小于1/2Vdd；若第一电容C1中存储的是第二逻辑信息例如“1”，则第一电容C1的第一电极板的电压保持在1/2Vdd，即预充晶体管PTR的第一极与读取晶体管STR的栅极的电压保持在1/2Vdd，由于读取晶体管STR的栅极电压的变化会影响源线SL上的电流，因而向与待读取存储单元100电连接的第一位线BL提供第一电压，通过读取与待读取存储单元100电连接的源线SL的电流，便可以确定第一电容C1中存储的是第一逻辑信息例如“0”，还是第二逻辑信息例如“1”。Read operation process: Referring to FIG. 4c, taking reading the logic information stored in the first capacitor C1 as an example, a control signal is provided to the control line CL electrically connected to the storage unit 100 to be read, and the pre-charge transistor PTR is controlled to be turned on, and the The second bit line BL' electrically connected to the memory cell 100 to be read provides a voltage of 1/2Vdd, and precharges the voltage 1/2Vdd to the first electrode of the precharge transistor PTR and the terminal of the read transistor STR through the precharge transistor PTR. Gate: applying a voltage Vdd to the first word line WL electrically connected to the first capacitor C1 to be read, and applying a ground voltage to the other first word lines WL and all the second word lines WL'. If the first logic information such as "0" is stored in the first capacitor C1, the voltage of the first electrode plate of the first capacitor C1 will decrease, that is, the first pole of the precharge transistor PTR and the gate of the read transistor STR The voltage of the first electrode plate of the first capacitor C1 will be reduced to less than 1/2Vdd; if the second logic information such as "1" is stored in the first capacitor C1, the voltage of the first electrode plate of the first capacitor C1 will remain at 1/2Vdd, that is, pre-charge The voltage of the first electrode of the transistor PTR and the gate of the read transistor STR is maintained at 1/2Vdd, because the change of the gate voltage of the read transistor STR will affect the current on the source line SL, thus to the memory cell to be read The first bit line BL electrically connected to 100 provides the first voltage, and by reading the current of the source line SL electrically connected to the memory cell 100 to be read, it can be determined that the storage in the first capacitor C1 is the first logic information such as " 0", or second logic information such as "1".

在本实施例一中，由于读取晶体管STR和预充晶体管PTR均为垂直沟道晶体管，读取晶体管STR的第一极101设置在读取晶体管STR的第二极102沿第一方向X的一侧，预充晶体管PTR的第一极101设置在预充晶体管PTR的第二极102沿第一方向X的一侧，且读取晶体管STR的半导体层104包括第一部分，第一部分沿第一方向X延伸，预充晶体管PTR的半导体层104包括第二部分，第二部分沿第一方向X延伸，此外，第一电容C1和第二电容C2沿第一方向X层叠设置，因而在垂直于第一方向X的平面上，可以有效地减小存储单元100所占的面积，从而可以提高铁电存储器10的存储密度和容量。In the first embodiment, since both the read transistor STR and the precharge transistor PTR are vertical channel transistors, the first pole 101 of the read transistor STR is set at the position of the second pole 102 of the read transistor STR along the first direction X. On one side, the first pole 101 of the pre-charge transistor PTR is arranged on the side of the second pole 102 of the pre-charge transistor PTR along the first direction X, and the semiconductor layer 104 of the read transistor STR includes a first portion, and the first portion is along the first direction X. The semiconductor layer 104 of the pre-charge transistor PTR includes a second portion, and the second portion extends along the first direction X. In addition, the first capacitor C1 and the second capacitor C2 are stacked along the first direction X, so that they are vertical to On the plane of the first direction X, the area occupied by the memory unit 100 can be effectively reduced, thereby increasing the storage density and capacity of the ferroelectric memory 10 .

实施例二Embodiment two

实施例二与实施例一的区别之处在于，预充晶体管PTR的结构不相同，在实施例一中，预充晶体管PTR为垂直沟道晶体管；在实施例二中，预充晶体管PTR为环栅晶体管(gate all around transistor，GAA transistor)。The difference between the second embodiment and the first embodiment is that the structure of the pre-charge transistor PTR is different. In the first embodiment, the pre-charge transistor PTR is a vertical channel transistor; in the second embodiment, the pre-charge transistor PTR is a ring Gate transistor (gate all around transistor, GAA transistor).

本实施例二提供的铁电存储器10，如图6a和图6b所示，铁电存储器10包括：阵列分布的多个存储单元100、多条平行排列的第一位线BL、多条平行排列的第二位线BL＇、多条平行排列的第一字线WL、多条平行排列的第二字线WL＇、多条平行排列的源线SL以及多条平行排列的控制线CL；存储单元100包括读取晶体管STR、预充晶体管PTR以及至少一个电容组107。本实施例二仅对与实施例一不相同的部分进行介绍，相同的部分可以参考上述实施例一，此处不再赘述。The ferroelectric memory 10 provided in the second embodiment, as shown in Figure 6a and Figure 6b, the ferroelectric memory 10 includes: a plurality of memory cells 100 distributed in an array, a plurality of first bit lines BL arranged in parallel, a plurality of parallel arranged The second bit line BL', a plurality of first word lines WL arranged in parallel, a plurality of second word lines WL' arranged in parallel, a plurality of source lines SL arranged in parallel, and a plurality of control lines CL arranged in parallel; The unit 100 includes a read transistor STR, a precharge transistor PTR and at least one capacitor bank 107 . The second embodiment only introduces the parts that are different from the first embodiment, and the same parts can refer to the first embodiment above, and will not be repeated here.

图6a为实施例二提供的铁电存储器10的立体结构示意图，图6b为图6a中沿BB向的剖面示意图。FIG. 6a is a schematic perspective view of the three-dimensional structure of the ferroelectric memory 10 provided in Embodiment 2, and FIG. 6b is a schematic cross-sectional view along the direction BB in FIG. 6a.

在本实施例二中，上述预充晶体管PTR为环栅晶体管，如图7所示，预充晶体管PTR包括第一极101、第二极102和栅极103，预充晶体管PTR的第一极与读取晶体管STR的栅极103电连接，预充晶体管PTR的第二极102与第二位线BL＇电连接，预充晶体管PTR的栅极103与控制线CL电连接；其中，预充晶体管PTR的第一极101和预充晶体管PTR的第二极102中一个为源极S，一个为漏极D。预充晶体管PTR的第一极101设置在预充晶体管PTR的第二极102沿第一方向X的一侧；在一些示例中，预充晶体管PTR的第一极101和预充晶体管PTR的第二极102沿第一方向X层叠设置；预充晶体管PTR的栅极103设置在预充晶体管PTR的第一极101和预充晶体管PTR的第二极102之间。In the second embodiment, the above-mentioned precharge transistor PTR is a gate-around transistor. As shown in FIG. 7, the precharge transistor PTR includes a first pole 101, a second pole 102, and a gate 103. It is electrically connected to the gate 103 of the read transistor STR, the second pole 102 of the precharge transistor PTR is electrically connected to the second bit line BL', and the gate 103 of the precharge transistor PTR is electrically connected to the control line CL; wherein, the precharge One of the first pole 101 of the transistor PTR and the second pole 102 of the pre-charge transistor PTR is a source S, and the other is a drain D. The first pole 101 of the precharge transistor PTR is arranged on one side of the second pole 102 of the precharge transistor PTR along the first direction X; Diodes 102 are stacked along the first direction X; the gate 103 of the pre-charging transistor PTR is set between the first pole 101 of the pre-charging transistor PTR and the second pole 102 of the pre-charging transistor PTR.

此处，可以是预充晶体管PTR的第一极101为源极S，预充晶体管PTR的第二极102为漏极D；也可以是预充晶体管PTR的第一极101为漏极D，预充晶体管PTR的第二极102为源极S。Here, the first pole 101 of the precharge transistor PTR may be the source S, and the second pole 102 of the precharge transistor PTR may be the drain D; or the first pole 101 of the precharge transistor PTR may be the drain D, The second pole 102 of the precharge transistor PTR is the source S.

请继续参考图7，上述环栅晶体管还包括：第一绝缘介质层106、第二绝缘介质层110、半导体层104以及栅介质层105；环栅晶体管的第一绝缘介质层106设置在环栅晶体管的第一极101和环栅晶体管的栅极103之间；环栅晶体管的第二绝缘介质层110设置在环栅晶体管的第二极102与环栅晶体管的栅极103之间；环栅晶体管的半导体层104包括第二部分，第二部分沿第一方向X延伸；环栅晶体管的半导体层104依次贯穿环栅晶体管的第一极101、环栅晶体管的第一绝缘介质层103、环栅晶体管的栅极103、环栅晶体管的第二绝缘介质层110以及环栅晶体管的第二极102；环栅晶体管的第一极101和环栅晶体管的第二极102分别与环栅晶体管的半导体层104接触，环栅晶体管的栅介质层105设置在环栅晶体管的半导体层104和环栅晶体管的栅极103之间。Please continue to refer to FIG. 7, the above-mentioned gate-all-around transistor also includes: a first insulating dielectric layer 106, a second insulating dielectric layer 110, a semiconductor layer 104, and a gate dielectric layer 105; the first insulating dielectric layer 106 of the gate-all-round transistor is arranged on the Between the first pole 101 of the transistor and the gate 103 of the gate-around transistor; the second insulating medium layer 110 of the gate-around transistor is arranged between the second pole 102 of the gate-around transistor and the gate 103 of the gate-around transistor; The semiconductor layer 104 of the transistor includes a second part, and the second part extends along the first direction X; the semiconductor layer 104 of the gate-around transistor sequentially penetrates through the first pole 101 of the gate-around transistor, the first insulating medium layer 103 of the gate-around transistor, the ring The gate 103 of the gate transistor, the second insulating medium layer 110 of the gate-around transistor, and the second pole 102 of the gate-around transistor; the first pole 101 of the gate-around transistor and the second pole 102 of the gate-around transistor are respectively connected with the gate-around transistor The semiconductor layer 104 is in contact, and the gate dielectric layer 105 of the gate-around transistor is disposed between the semiconductor layer 104 of the gate-around transistor and the gate 103 of the gate-around transistor.

在本实施例中，环栅晶体管的半导体层104可以只包括第二部分，第二部分沿第一方向X延伸。In this embodiment, the semiconductor layer 104 of the gate-all-around transistor may only include the second portion, and the second portion extends along the first direction X.

可以理解的是，在存储单元100包括浮空栅电极109的情况下，预充晶体管PTR的半导体层104和浮空栅电极109之间可以设置绝缘层，以将半导体层104和浮空栅电极109间隔开。It can be understood that, in the case that the memory cell 100 includes a floating gate electrode 109, an insulating layer may be provided between the semiconductor layer 104 and the floating gate electrode 109 of the prefill transistor PTR, so that the semiconductor layer 104 and the floating gate electrode 109 spaced apart.

此处，环栅晶体管的栅极103的材料、环栅晶体管的第一极101的材料、环栅晶体管的第二极102的材料、环栅晶体管的栅介质层105的材料以及环栅晶体管的半导体层104的材料可以参考上述实施例一，此处不再赘述。Here, the material of the gate 103 of the surrounding gate transistor, the material of the first pole 101 of the surrounding gate transistor, the material of the second pole 102 of the surrounding gate transistor, the material of the gate dielectric layer 105 of the surrounding gate transistor, and the material of the surrounding gate transistor For the material of the semiconductor layer 104, reference may be made to the first embodiment above, which will not be repeated here.

在本实施例二中，读取晶体管STR为垂直沟道晶体管，可以参考上述实施例一有关垂直沟道晶体管的相关描述，此处不再赘述。In the second embodiment, the reading transistor STR is a vertical channel transistor, and reference may be made to the relevant description of the vertical channel transistor in the first embodiment above, and details are not repeated here.

在此基础上，上述预充晶体管PTR沿第一方向X可以与读取晶体管STR层叠设置，也可以不与读取晶体管STR层叠设置。在预充晶体管PTR沿第一方向X与读取晶体管STR层叠设置的情况下，在垂直于第一方向X的方向上，可以减小预充晶体管PTR和读取晶体管STR所占的面积，进而可以减小存储单元100所占的面积。On this basis, the above-mentioned pre-charge transistor PTR may be stacked with the read transistor STR along the first direction X, or may not be stacked with the read transistor STR. In the case where the precharge transistor PTR is stacked with the read transistor STR along the first direction X, in the direction perpendicular to the first direction X, the area occupied by the precharge transistor PTR and the read transistor STR can be reduced, thereby The area occupied by the memory cell 100 can be reduced.

以第一方向X为竖直方向X，垂直于第一方向X的方向为水平方向为例，相对于平面晶体管中的第一极101和第二极102沿水平方向同层设置，且半导体层104沿水平方向延伸而言，在本实施例二中，由于预充晶体管PTR为环栅晶体管，环栅晶体管的第一极101和环栅晶体管的第二极102沿竖直方向X层叠设置，且环栅晶体管的半导体层104包括第二部分，第二部分沿竖直方向X延伸，因而预充晶体管PTR在水平方向X上的尺寸较小，从而可以使得存储单元100的尺寸较小，进而可以提高铁电存储器10的存储密度和容量。Taking the first direction X as the vertical direction X, and the direction perpendicular to the first direction X as the horizontal direction as an example, the first pole 101 and the second pole 102 in the planar transistor are arranged in the same layer along the horizontal direction, and the semiconductor layer 104 extending along the horizontal direction, in the second embodiment, since the pre-charge transistor PTR is a gate-around transistor, the first pole 101 of the gate-around transistor and the second pole 102 of the gate-around transistor are stacked along the vertical direction X, And the semiconductor layer 104 of the gate-around transistor includes a second part, and the second part extends along the vertical direction X, so the size of the pre-charge transistor PTR in the horizontal direction X is relatively small, so that the size of the memory cell 100 can be made small, and further The storage density and capacity of the ferroelectric memory 10 can be increased.

在此基础上，在预充晶体管PTR为环栅晶体管的情况下，由于环栅晶体管的栅极103设置在环栅晶体管的第一极101和环栅晶体管的第二极102之间，而环栅晶体管的第二极102与第二位线BL＇电连接，环栅晶体管的第一极101与浮空栅电极109电连接，这样一来，与环栅晶体管的栅极103电连接的控制线CL可以设置在第二位线BL＇和浮空栅电极109之间，相对于预充晶体管PTR为垂直沟道晶体管的情况下，控制线CL设置在第二位线BL＇远离浮空栅电极109的一侧，与环栅晶体管的栅极103电连接的控制线CL设置在第二位线BL＇和浮空栅电极109之间可以减小铁电存储器10沿第一方向X的尺寸。在此基础上，控制线CL还可以和第二字线WL＇同时制作，从而可以减少一张掩膜板，这样一来，在铁电存储器10的制作过程中，可以减少工艺步骤和成本。On this basis, in the case where the pre-charge transistor PTR is a gate-around transistor, since the gate 103 of the gate-around transistor is arranged between the first pole 101 of the gate-around transistor and the second pole 102 of the gate-around transistor, the The second pole 102 of the gate transistor is electrically connected to the second bit line BL', and the first pole 101 of the gate-around transistor is electrically connected to the floating gate electrode 109. In this way, the control gate 103 electrically connected to the gate-around transistor The line CL can be arranged between the second bit line BL' and the floating gate electrode 109. In the case where the pre-charge transistor PTR is a vertical channel transistor, the control line CL is arranged on the second bit line BL' away from the floating gate electrode 109. On one side of the electrode 109, the control line CL electrically connected to the gate 103 of the surrounding gate transistor is arranged between the second bit line BL' and the floating gate electrode 109, which can reduce the size of the ferroelectric memory 10 along the first direction X . On this basis, the control line CL can be fabricated simultaneously with the second word line WL', so that a mask can be reduced. In this way, process steps and costs can be reduced during the fabrication of the ferroelectric memory 10 .

实施例三Embodiment Three

实施例三和实施例一的区别之处在于，读取晶体管STR的结构不相同，在实施例一中，读取晶体管STR为垂直沟道晶体管，在实施例三中，读取晶体管STR为环栅晶体管。The difference between the third embodiment and the first embodiment is that the structure of the read transistor STR is different. In the first embodiment, the read transistor STR is a vertical channel transistor. In the third embodiment, the read transistor STR is a ring transistor. gate transistor.

本实施例三提供的铁电存储器10，如图8所示，铁电存储器10包括：阵列分布的多个存储单元100、多条平行排列的第一位线BL、多条平行排列的第二位线BL＇、多条平行排列的第一字线WL、多条平行排列的第二字线WL＇、多条平行排列的源线SL以及多条平行排列的控制线CL；存储单元100包括读取晶体管STR、预充晶体管PTR以及至少一个电容组107。本实施例三仅对与实施例一不相同的部分进行介绍，相同的部分可以参考上述实施例一，此处不再赘述。The ferroelectric memory 10 provided in the third embodiment, as shown in FIG. A bit line BL', a plurality of first word lines WL arranged in parallel, a plurality of second word lines WL' arranged in parallel, a plurality of source lines SL arranged in parallel, and a plurality of control lines CL arranged in parallel; the memory unit 100 includes Read transistor STR, precharge transistor PTR and at least one capacitor bank 107 . The third embodiment only introduces the parts that are different from the first embodiment, and the same parts can refer to the first embodiment above, and will not be repeated here.

图8为实施例三提供的铁电存储器10的剖面示意图。FIG. 8 is a schematic cross-sectional view of the ferroelectric memory 10 provided in the third embodiment.

在本实施例三中，上述读取晶体管STR为环栅晶体管，参考图7，读取晶体管STR包括第一极101、第二极102和栅极103，读取晶体管STR的第一极与第一位线BL电连接，读取晶体管STR的第二极与源线SL电连接，读取晶体管STR的栅极与预充晶体管PTR的第一极电连接；其中，读取晶体管STR的第一极101和读取晶体管STR的第二极102中一个为源极S，一个为漏极D。读取晶体管STR的第一极101设置在读取晶体管STR的第二极102沿第一方向X的一侧；在一些示例中，读取晶体管STR的第一极101和读取晶体管STR的第二极102沿第一方向X层叠设置；读取晶体管STR的栅极103设置在读取晶体管STR的第一极101和读取晶体管STR的第二极102之间。In the third embodiment, the read transistor STR is a gate-around transistor. Referring to FIG. 7, the read transistor STR includes a first pole 101, a second pole 102, and a gate 103. The bit line BL is electrically connected, the second pole of the read transistor STR is electrically connected to the source line SL, and the gate of the read transistor STR is electrically connected to the first pole of the prefill transistor PTR; wherein, the first pole of the read transistor STR One of the electrode 101 and the second electrode 102 of the reading transistor STR is the source S, and the other is the drain D. The first pole 101 of the read transistor STR is arranged on one side of the second pole 102 of the read transistor STR along the first direction X; in some examples, the first pole 101 of the read transistor STR and the second pole 102 of the read transistor STR The diodes 102 are stacked along the first direction X; the gate 103 of the reading transistor STR is arranged between the first pole 101 of the reading transistor STR and the second pole 102 of the reading transistor STR.

此处，可以是读取晶体管STR的第一极101为源极S，读取晶体管STR的第二极102为漏极D；也可以是读取晶体管STR的第一极101为漏极D，读取晶体管STR的第二极102为源极S。Here, the first pole 101 of the reading transistor STR may be the source S, and the second pole 102 of the reading transistor STR may be the drain D; or the first pole 101 of the reading transistor STR may be the drain D, The second terminal 102 of the read transistor STR is the source S.

请继续参考图7，上述环栅晶体管还包括：第一绝缘介质层106、第二绝缘介质层110、半导体层104以及栅介质层105；环栅晶体管的半导体层104包括第一部分，第一沿第一方向X延伸；环栅晶体管的第一绝缘介质层106、环栅晶体管的第二绝缘介质层110、环栅晶体管的半导体层104和环栅晶体管的栅介质层105的设置位置以及连接关系可以参考上述实施例二中有关环栅晶体管的相关描述，此处不再赘述。Please continue to refer to FIG. 7, the above-mentioned gate-all-around transistor also includes: a first insulating dielectric layer 106, a second insulating dielectric layer 110, a semiconductor layer 104, and a gate dielectric layer 105; the semiconductor layer 104 of the gate-all-around transistor includes a first part, a first edge The first direction X extends; the setting position and connection relationship of the first insulating dielectric layer 106 of the surrounding gate transistor, the second insulating dielectric layer 110 of the surrounding gate transistor, the semiconductor layer 104 of the surrounding gate transistor, and the gate dielectric layer 105 of the surrounding gate transistor Reference may be made to the related descriptions about the gate-all-around transistor in the above-mentioned second embodiment, which will not be repeated here.

以第一方向X为竖直方向X，垂直于第一方向X的方向为水平方向为例，相对于平面晶体管中的第一极101和第二极102沿水平方向同层设置，且半导体层104沿水平方向延伸而言，在本实施例三中，由于读取晶体管STR为环栅晶体管，环栅晶体管的第一极101和环栅晶体管的第二极102沿竖直方向X层叠设置，且环栅晶体管的半导体层104包括第一部分，第一部分沿竖直方向X延伸，因而读取晶体管STR在水平方向X上的尺寸较小，从而可以使得存储单元100的尺寸较小，进而可以提高铁电存储器10的存储密度和容量。Taking the first direction X as the vertical direction X, and the direction perpendicular to the first direction X as the horizontal direction as an example, the first pole 101 and the second pole 102 in the planar transistor are arranged in the same layer along the horizontal direction, and the semiconductor layer 104 extending along the horizontal direction, in the third embodiment, since the reading transistor STR is a gate-around transistor, the first pole 101 of the gate-around transistor and the second pole 102 of the gate-around transistor are stacked along the vertical direction X, And the semiconductor layer 104 of the gate-around transistor includes a first part, and the first part extends along the vertical direction X, so the size of the read transistor STR in the horizontal direction X is relatively small, so that the size of the memory cell 100 can be made small, thereby improving Storage density and capacity of ferroelectric memory 10.

在此基础上，上述预充晶体管PTR沿第一方向X可以与读取晶体管STR层叠设置，也可以不与读取晶体管STR层叠设置。在预充晶体管PTR沿第一方向X与读取晶体管STR层叠设置的情况下，在垂直于第一方向X的平面上，可以减小预充晶体管PTR和读取晶体管STR所占的面积，进而可以减小存储单元100所占的面积。On this basis, the above-mentioned pre-charge transistor PTR may be stacked with the read transistor STR along the first direction X, or may not be stacked with the read transistor STR. In the case where the precharge transistor PTR is stacked with the read transistor STR along the first direction X, on a plane perpendicular to the first direction X, the area occupied by the precharge transistor PTR and the read transistor STR can be reduced, thereby The area occupied by the memory cell 100 can be reduced.

实施例四Embodiment Four

实施例四和实施例一的区别之处在于，预充晶体管PTR的结构以及读取晶体管STR的结构均不相同，在实施例一中，预充晶体管PTR为垂直沟道晶体管，读取晶体管STR为垂直沟道晶体管，在实施例四中，预充晶体管PTR为环栅晶体管，读取晶体管STR为环栅晶体管。The difference between the fourth embodiment and the first embodiment is that the structure of the pre-charge transistor PTR and the structure of the read transistor STR are different. In the first embodiment, the pre-charge transistor PTR is a vertical channel transistor, and the read transistor STR is a vertical channel transistor. In Embodiment 4, the precharge transistor PTR is a gate-around transistor, and the read transistor STR is a gate-around transistor.

本实施例四提供的铁电存储器10，如图9所示，铁电存储器10包括：阵列分布的多个存储单元100、多条平行排列的第一位线BL、多条平行排列的第二位线BL＇、多条平行排列的第一字线WL、多条平行排列的第二字线WL＇、多条平行排列的源线SL以及多条平行排列的控制线CL；存储单元100包括读取晶体管STR、预充晶体管PTR以及至少一个电容组107。本实施例四仅对与实施例一不相同的部分进行介绍，相同的部分可以参考上述实施例一，此处不再赘述。The ferroelectric memory 10 provided in Embodiment 4, as shown in FIG. 9 , the ferroelectric memory 10 includes: a plurality of memory cells 100 distributed in an array, a plurality of first bit lines BL arranged in parallel, and a plurality of second bit lines BL arranged in parallel. A bit line BL', a plurality of first word lines WL arranged in parallel, a plurality of second word lines WL' arranged in parallel, a plurality of source lines SL arranged in parallel, and a plurality of control lines CL arranged in parallel; the memory unit 100 includes Read transistor STR, precharge transistor PTR and at least one capacitor bank 107 . This fourth embodiment only introduces the parts that are different from the first embodiment, and the same parts can refer to the first embodiment above, and will not be repeated here.

图9为实施例四提供的铁电存储器10的剖面示意图。FIG. 9 is a schematic cross-sectional view of the ferroelectric memory 10 provided in the fourth embodiment.

预充晶体管PTR为环栅晶体管，预充晶体管PTR的结构、连接关系、以及预充晶体管PTR为环栅晶体管所具有的有益效果可以参考上述实施例二，本实施例四不再赘述。读取晶体管STR为环栅晶体管，读取晶体管STR的结构、连接关系、以及读取晶体管STR为环栅晶体管所具有的有益效果可以参考上述实施例三，本实施例四不再赘述。The pre-charge transistor PTR is a gate-all-around transistor. The structure and connection relationship of the pre-charge transistor PTR and the beneficial effects of the pre-charge transistor PTR being a gate-all-around transistor can be referred to the second embodiment above, and the fourth embodiment will not be repeated. The readout transistor STR is a gate-all-around transistor, and the structure and connection relationship of the readout transistor STR and the beneficial effects of the readout transistor STR being a gate-all-around transistor can be referred to the above-mentioned third embodiment, which will not be repeated in this fourth embodiment.

图10a和图10b提供的存储单元的电路结构均如图4c所示，图10a为本实施例四提供的铁电存储器10中一个存储单元100在垂直第一方向X的平面上的俯视结构示意图，其中，预充晶体管PTR和读取晶体管STR均为图7所示的环栅晶体管。图10b为相关技术提供的铁电存储器10中一个存储单元100在垂直于第一方向X的平面上的俯视结构示意图，其中，预充晶体管PTR和读取晶体管STR均为平面晶体管。通过对比图10a和图10b可知，本实施例四提供的铁电存储器10中的预充晶体管PTR和读取晶体管STR在垂直于第一方向X的平面所占的面积大大减小。当存储单元100中电容的个数n为16时，一个存储单元100在垂直于第一方向X的平面上的投影的面积可以减小31％左右。The circuit structures of the memory cells provided in FIG. 10a and FIG. 10b are both shown in FIG. 4c, and FIG. 10a is a schematic top view of a memory cell 100 in the ferroelectric memory 10 provided in Embodiment 4 on a plane perpendicular to the first direction X , wherein both the precharge transistor PTR and the read transistor STR are gate-around transistors as shown in FIG. 7 . 10b is a schematic top view of a memory cell 100 in a ferroelectric memory 10 provided in the related art on a plane perpendicular to the first direction X, wherein both the precharge transistor PTR and the read transistor STR are planar transistors. By comparing FIG. 10 a with FIG. 10 b , it can be seen that the area occupied by the precharge transistor PTR and the read transistor STR in the ferroelectric memory 10 provided in the fourth embodiment on a plane perpendicular to the first direction X is greatly reduced. When the number n of capacitors in the storage unit 100 is 16, the projected area of a storage unit 100 on a plane perpendicular to the first direction X can be reduced by about 31%.

实施例五Embodiment five

实施例五和实施例一的区别之处在于，源线SL与第一位线BL、第二位线BL＇的位置关系不同，在实施例一中，多条源线SL与多条第一位线BL、多条第二位线BL＇相交；在实施例五中，多条源线SL与多条第一位线BL相互平行，多条源线SL与多条第二位线BL＇相互平行。The difference between the fifth embodiment and the first embodiment is that the positional relationship between the source line SL and the first bit line BL and the second bit line BL' is different. In the first embodiment, multiple source lines SL and multiple first bit lines The bit line BL intersects with the multiple second bit lines BL'; in the fifth embodiment, the multiple source lines SL and the multiple first bit lines BL are parallel to each other, and the multiple source lines SL and the multiple second bit lines BL' parallel to each other.

本实施例五仅对与实施例一不相同的部分进行介绍，相同的部分可以参考上述实施例一，此处不再赘述。This fifth embodiment only introduces the parts that are different from the first embodiment, and the same parts can refer to the first embodiment above, and will not be repeated here.

如图11a和图11b所示，多条源线SL与多条第一位线BL相互平行，多条源线SL与多条第二位线BL＇相互平行。As shown in FIG. 11 a and FIG. 11 b , multiple source lines SL and multiple first bit lines BL are parallel to each other, and multiple source lines SL and multiple second bit lines BL' are parallel to each other.

其中，图11a为实施例五提供的铁电存储器的立体结构示意图，图11b为图11a中沿CC向的剖面示意图。Wherein, FIG. 11a is a schematic perspective view of the three-dimensional structure of the ferroelectric memory provided in Embodiment 5, and FIG. 11b is a schematic cross-sectional view along CC direction in FIG. 11a.

在本实施例五中，将多条源线SL与多条第一位线BL相互平行设置，多条源线 SL与多条第二位线BL＇相互平行设置，提高了铁电存储器10设计的灵活性，进而可以降低***电路的设计难度。In the fifth embodiment, a plurality of source lines SL and a plurality of first bit lines BL are arranged in parallel with each other, and a plurality of source lines SL and a plurality of second bit lines BL' are arranged in parallel with each other, which improves the design of the ferroelectric memory 10. The flexibility can reduce the design difficulty of peripheral circuits.

在与同一个存储单元100电连接的第一位线BL和第二位线BL＇电连接的情况下，考虑到若读取晶体管STR的第一极101相对于第二极102远离预充晶体管PTR，则与读取晶体管STR的第一极101电连接的第一位线BL相对于与读取晶体管STR的第二极102电连接的源线SL远离预充晶体管PTR，即沿第一方向X，源线SL设置在第一位线BL和第二位线BL＇之间，这样一来，第一位线BL和第二位线BL＇通过位线接触通孔108电连接时，为了防止第一位线BL、第二位线BL＇与源线SL短路，因此位线接触通孔108需避让源线SL，从而增加了铁电存储器10的设计难度。基于此，在一些示例中，读取晶体管STR的第一极101相对于读取晶体管STR的第二极102靠近预充晶体管PTR，且沿第一方向X，第一位线BL设置在源线SL和第二位线BL＇之间。In the case that the first bit line BL and the second bit line BL' electrically connected to the same memory cell 100 are electrically connected, it is considered that if the first pole 101 of the read transistor STR is far away from the precharge transistor relative to the second pole 102 PTR, the first bit line BL electrically connected to the first pole 101 of the read transistor STR is far away from the precharge transistor PTR relative to the source line SL electrically connected to the second pole 102 of the read transistor STR, that is, in the first direction X, the source line SL is arranged between the first bit line BL and the second bit line BL', so that when the first bit line BL and the second bit line BL' are electrically connected through the bit line contact hole 108, in order To prevent the first bit line BL, the second bit line BL′ from being short-circuited with the source line SL, the bit line contact via hole 108 needs to avoid the source line SL, thereby increasing the design difficulty of the ferroelectric memory 10 . Based on this, in some examples, the first pole 101 of the read transistor STR is closer to the precharge transistor PTR than the second pole 102 of the read transistor STR, and along the first direction X, the first bit line BL is arranged on the source line SL and the second bit line BL' between.

由于沿第一方向X，第一位线BL设置在源线SL和第二位线BL＇之间，这样在第一位线BL和第二位线BL＇通过位线接触通孔108电连接时，设置位线接触通孔108时无需避让源线SL，从而降低了铁电存储器10的设计难度。Since the first bit line BL is arranged between the source line SL and the second bit line BL' along the first direction X, the first bit line BL and the second bit line BL' are electrically connected through the bit line contact via 108 When setting the bit line contact via hole 108, there is no need to avoid the source line SL, thereby reducing the design difficulty of the ferroelectric memory 10.

可以理解的是，在本实施例五中，预充晶体管PTR和读取晶体管STR除了可以是实施例一所示的结构外，预充晶体管PTR和读取晶体管STR还可以是实施例二、实施例三或实施例四所示的结构，具体可以参考上述实施例二、实施例三和实施例四，此处不再赘述。图11a和图11b以预充晶体管PTR和读取晶体管STR为实施例二所示的结构为例进行示意。It can be understood that, in the fifth embodiment, in addition to the structure shown in the first embodiment, the precharge transistor PTR and the read transistor STR can also be the second embodiment. For the structure shown in Example 3 or Example 4, specific reference may be made to the above-mentioned Example 2, Example 3, and Example 4, which will not be repeated here. FIG. 11 a and FIG. 11 b take the precharge transistor PTR and the read transistor STR as an example to illustrate the structure shown in the second embodiment.

以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

一种铁电存储器，其特征在于，包括：阵列分布的多个存储单元、多条第一位线、多条第二位线、多条第一字线、多条第二字线、多条源线以及多条控制线；A ferroelectric memory, characterized in that it includes: a plurality of memory cells distributed in an array, a plurality of first bit lines, a plurality of second bit lines, a plurality of first word lines, a plurality of second word lines, a plurality of source line and multiple control lines;

所述多个存储单元中的每个存储单元包括：Each storage unit in the plurality of storage units includes:

读取晶体管，所述读取晶体管的第一极与所述第一位线电连接，所述读取晶体管的第二极与所述源线电连接；所述读取晶体管的第一极设置在所述读取晶体管的第二极沿第一方向的一侧；所述读取晶体管的半导体层包括第一部分，所述第一部分沿所述第一方向延伸；所述读取晶体管的第一极和第二极中一个为源极，另一个为漏极；A read transistor, the first pole of the read transistor is electrically connected to the first bit line, and the second pole of the read transistor is electrically connected to the source line; the first pole of the read transistor is set On one side of the second pole of the read transistor along the first direction; the semiconductor layer of the read transistor includes a first portion extending along the first direction; the first portion of the read transistor One of the pole and the second pole is a source, and the other is a drain;

预充晶体管，所述预充晶体管的第一极与所述读取晶体管的栅极电连接，所述预充晶体管的第二极与所述第二位线电连接，所述预充晶体管的栅极与所述控制线电连接；所述预充晶体管的第一极设置在所述预充晶体管的第二极沿所述第一方向的一侧；所述预充晶体管的半导体层包括第二部分，所述第二部分沿所述第一方向延伸；所述预充晶体管的第一极和第二极中一个为源极，另一个为漏极；A pre-charge transistor, the first electrode of the pre-charge transistor is electrically connected to the gate of the read transistor, the second electrode of the pre-charge transistor is electrically connected to the second bit line, and the pre-charge transistor The gate is electrically connected to the control line; the first pole of the precharge transistor is arranged on one side of the second pole of the precharge transistor along the first direction; the semiconductor layer of the precharge transistor includes a first Two parts, the second part extends along the first direction; one of the first pole and the second pole of the pre-charge transistor is a source, and the other is a drain;

至少一个电容组，所述至少一个电容组中的每个电容组包括沿所述第一方向层叠设置且电连接的第一电容和第二电容；所述第一电容的第一电极板和所述第二电容的第一电极板均与所述读取晶体管的栅极以及所述预充晶体管的第一极电连接，所述第一电容的第二电极板与所述第一字线电连接，所述第二电容的第二电极板与所述第二字线电连接。At least one capacitor group, each capacitor group in the at least one capacitor group includes a first capacitor and a second capacitor that are stacked and electrically connected along the first direction; the first electrode plate of the first capacitor and the first capacitor The first electrode plate of the second capacitor is electrically connected to the gate of the read transistor and the first electrode of the pre-charge transistor, and the second electrode plate of the first capacitor is electrically connected to the first word line connected, the second electrode plate of the second capacitor is electrically connected to the second word line.
根据权利要求1所述的铁电存储器，其特征在于，所述读取晶体管和所述预充晶体管沿所述第一方向层叠设置。The ferroelectric memory according to claim 1, wherein the read transistor and the precharge transistor are stacked along the first direction.
根据权利要求1或2所述的铁电存储器，其特征在于，所述存储单元还包括浮空栅电极；所述浮空栅电极的部分用于作为所述电容组中所述第一电容的第一电极板和所述第二电容的第一电极板；所述读取晶体管的栅极以及所述预充晶体管的第一极均与所述浮空栅电极电连接。The ferroelectric memory according to claim 1 or 2, wherein the memory cell further comprises a floating gate electrode; a part of the floating gate electrode is used as the first capacitor in the capacitor bank The first electrode plate and the first electrode plate of the second capacitor; the gate of the read transistor and the first pole of the pre-charge transistor are all electrically connected to the floating gate electrode.
根据权利要求3所述的铁电存储器，其特征在于，所述第一字线与所述浮空栅电极相交，所述第一字线与所述浮空栅电极相交的部分用于作为所述第一电容的第二电极板；The ferroelectric memory according to claim 3, wherein the first word line intersects the floating gate electrode, and the intersecting part of the first word line and the floating gate electrode is used as the The second electrode plate of the first capacitor;

和/或，所述第二字线与所述浮空栅电极相交，所述第二字线与所述浮空栅电极相交的部分用于作为所述第二电容的第二电极板。And/or, the second word line intersects the floating gate electrode, and the intersecting part of the second word line and the floating gate electrode is used as a second electrode plate of the second capacitor.
根据权利要求1-4任一项所述的铁电存储器，其特征在于，所述读取晶体管为垂直沟道晶体管，和/或，所述预充晶体管为所述垂直沟道晶体管；The ferroelectric memory according to any one of claims 1-4, wherein the read transistor is a vertical channel transistor, and/or, the pre-charge transistor is the vertical channel transistor;

所述垂直沟道晶体管的栅极包括栅基底、以及与所述栅基底接触且沿所述第一方向延伸的栅极柱，所述垂直沟道晶体管的第一极和第二极设置在所述栅基底沿所述第一方向的同一侧；The gate of the vertical channel transistor includes a gate base, and a gate column that is in contact with the gate base and extends along the first direction, and the first pole and the second pole of the vertical channel transistor are arranged on the gate base. the same side of the gate substrate along the first direction;

所述垂直沟道晶体管的半导体层至少设置在所述栅极柱的侧面，所述垂直沟道晶体管的第一极和所述第二极分别与所述垂直沟道晶体管的半导体层接触；The semiconductor layer of the vertical channel transistor is disposed at least on the side of the gate pillar, and the first pole and the second pole of the vertical channel transistor are respectively in contact with the semiconductor layer of the vertical channel transistor;

所述垂直沟道晶体管还包括：The vertical channel transistor also includes:

栅介质层，设置在所述垂直沟道晶体管的半导体层和所述垂直沟道晶体管的栅极之间；a gate dielectric layer disposed between the semiconductor layer of the vertical channel transistor and the gate of the vertical channel transistor;

第一绝缘介质层，设置在所述垂直沟道晶体管的第一极和第二极之间。The first insulating medium layer is arranged between the first pole and the second pole of the vertical channel transistor.
根据权利要求1-4任一项所述的铁电存储器，其特征在于，所述读取晶体管为环栅晶体管，和/或，所述预充晶体管为所述环栅晶体管；The ferroelectric memory according to any one of claims 1-4, wherein the read transistor is a gate-around transistor, and/or, the pre-charge transistor is the gate-around transistor;

所述环栅晶体管的栅极设置在所述环栅晶体管的第一极和第二极之间；The gate of the gate-around transistor is arranged between the first pole and the second pole of the gate-around transistor;

所述环栅晶体管还包括：第一绝缘介质层、第二绝缘介质层以及栅介质层；The gate-all-around transistor further includes: a first insulating dielectric layer, a second insulating dielectric layer, and a gate dielectric layer;

所述第一绝缘介质层设置在所述环栅晶体管的第一极和所述环栅晶体管的栅极之间；所述第二绝缘介质层设置在所述环栅晶体管的第二极与所述环栅晶体管的栅极之间；所述环栅晶体管的半导体层依次贯穿所述环栅晶体管的第一极、所述第一绝缘介质层、所述栅极、所述第二绝缘介质层以及所述第二极；所述环栅晶体管的第一极和第二极分别与所述环栅晶体管的半导体层接触，所述环栅晶体管的栅介质层设置在所述环栅晶体管的半导体层和所述环栅晶体管的栅极之间。The first insulating medium layer is arranged between the first pole of the gate-around transistor and the gate of the gate-around transistor; the second insulating medium layer is arranged between the second pole of the gate-around transistor and the gate of the gate-around transistor. between the gates of the gate-all-round transistor; the semiconductor layer of the gate-all-around transistor passes through the first pole of the gate-all-round transistor, the first insulating dielectric layer, the gate, and the second insulating dielectric layer in sequence and the second pole; the first pole and the second pole of the gate-around transistor are respectively in contact with the semiconductor layer of the gate-around transistor, and the gate dielectric layer of the gate-around transistor is arranged on the semiconductor layer of the gate-around transistor layer and the gate of the gate-all-around transistor.
根据权利要求1-6任一项所述的铁电存储器，其特征在于，所述多条源线和所述多条第一位线相交。The ferroelectric memory according to any one of claims 1-6, wherein the multiple source lines intersect with the multiple first bit lines.
根据权利要求1-6任一项所述的铁电存储器，其特征在于，所述多条源线和所述多条第一位线相互平行。The ferroelectric memory according to any one of claims 1-6, wherein the plurality of source lines and the plurality of first bit lines are parallel to each other.
根据权利要求1-8任一项所述的铁电存储器，其特征在于，与同一个所述存储单元电连接的所述第一位线和所述第二位线电连接。The ferroelectric memory according to any one of claims 1-8, characterized in that the first bit line and the second bit line electrically connected to the same memory cell are electrically connected.
根据权利要求9所述的铁电存储器，其特征在于，所述多条源线和所述多条第一位线相互平行，所述读取晶体管的第一极相对于所述读取晶体管的第二极靠近所述预充晶体管，且沿所述第一方向，所述第一位线设置在所述源线和所述第二位线之间。The ferroelectric memory according to claim 9, wherein the plurality of source lines and the plurality of first bit lines are parallel to each other, and the first pole of the read transistor is opposite to that of the read transistor. The second pole is close to the pre-charge transistor, and along the first direction, the first bit line is disposed between the source line and the second bit line.
根据权利要求1-10任一项所述的铁电存储器，其特征在于，所述第一电容和所述第二电容还包括设置在所述第一电极板和所述第二电极板之间的铁电材料。The ferroelectric memory according to any one of claims 1-10, wherein the first capacitor and the second capacitor further comprise ferroelectric materials.
根据权利要求1-11任一项所述的铁电存储器，其特征在于，所述多条第一位线和所述多条第二位线相互平行，所述多条第一字线、所述多条第二字线以及所述多条控制线相互平行，所述多条第一位线和所述多条第一字线相交。The ferroelectric memory according to any one of claims 1-11, wherein the plurality of first bit lines and the plurality of second bit lines are parallel to each other, and the plurality of first word lines, the plurality of The plurality of second word lines and the plurality of control lines are parallel to each other, and the plurality of first bit lines intersect with the plurality of first word lines.
一种电子设备，其特征在于，包括印刷电路板以及如权利要求1-12任一项所述的铁电存储器；An electronic device, characterized by comprising a printed circuit board and the ferroelectric memory according to any one of claims 1-12;

其中，所述铁电存储器和所述印刷电路板电连接。Wherein, the ferroelectric memory is electrically connected to the printed circuit board.