CN112447650A - Chip packaging part - Google Patents
Chip packaging part Download PDFInfo
- Publication number
- CN112447650A CN112447650A CN201910806941.7A CN201910806941A CN112447650A CN 112447650 A CN112447650 A CN 112447650A CN 201910806941 A CN201910806941 A CN 201910806941A CN 112447650 A CN112447650 A CN 112447650A
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- China
- Prior art keywords
- lead frame
- chip
- heat dissipation
- insulating block
- adhesive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a chip package which comprises a lead frame, a chip assembly arranged on the lead frame and a packaging layer for packaging the chip assembly. The lead frame has relative first face and second face, and the chip subassembly sets up the first face at the lead frame. And the packaging layer is provided with a top pinhole. The heat dissipation assembly is arranged on the second surface of the lead frame. The heat dissipation assembly comprises a heat dissipation sheet, an adhesive layer and an insulating block, wherein the adhesive layer is used for adhering the heat dissipation sheet and the second surface of the lead frame, and the insulating block is arranged between the heat dissipation sheet and the second surface and used for isolating the heat dissipation sheet and the second surface. The insulating block is opposite to the thimble. In the packaging process of the chip packaging part, even if the thimble applies larger pressure to the lead frame through the thimble hole, the lead frame can not press through the adhesive layer, so that the lead frame is prevented from contacting with the radiating fin, and the chip short circuit is prevented from being caused. And under the condition that the thimble applies larger pressure to the lead frame, the lead frame can be fully contacted with the bonding layer, and the heat dissipation performance of the chip is ensured.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip packaging piece.
Background
An IGBT (Insulated Gate Bipolar Transistor) module is a modular semiconductor product manufactured by bridging and packaging a plurality of IGBT chips and FRD chips (free wheeling diode chips) using a specific circuit. The integrated high-power module has the advantages of compact structure, high reliability, convenience in installation and the like, and is favorable for realizing high-reliability integrated layout in the application of the high-power module.
Because the module integrates the IGBT chip, the FRD chip and the driver in one package, the whole machine product has higher reliability and the volume of the equipment is greatly reduced. However, when the number of chips connected in parallel is increased to obtain higher current handling capability, heat loss generated during device operation is too concentrated, which increases difficulty in heat dissipation. Therefore, appropriate measures must be taken to suppress heat accumulation during operation of the module, and this requirement has led to a new technology in the field of power semiconductors, namely heat dissipation technology.
Referring to fig. 1, in order to sufficiently dissipate heat of a chip 1 inside a module, a copper insulating sheet 3 is adhered under a lead frame 2 to which the chip 1 is soldered during a packaging process. The copper insulating sheet 3 is composed of a layer of epoxy resin 4 and a layer of copper heat sink 5. The epoxy resin 4 is mainly used to insulate the lead frame 2 from the copper heat sink 5, so as to achieve insulation between the lead frame 2 and the copper heat sink 5. And under certain pressure, the epoxy resin 4 can be in full contact with the lead frame 2, so that the heat dissipation performance of the chip 1 is better. However, when the pressure is too high, the lead frame 2 may be pressed through the epoxy 4, causing the lead frame 2 to come into contact with the copper heat sink 5, thereby causing the chip 1 to be short-circuited. In the packaging process, the thimble 6 is pressed against the lead frame 2 at one side of the lead frame 2 to give a certain pressure to the lead frame 2, so that the epoxy resin 4 can be fully contacted with the lead frame 2. However, the pressure exerted on the lead frame 2 by the thimble 6 and the depth of the lead frame 2 embedded into the epoxy resin 4 are not well controlled during the packaging process. If the pressure exerted on the lead frame 2 by the thimble 6 is too large, contact between the lead frame 2 and the copper heat sink 5 is easily caused, and thus the chip 1 is short-circuited; if the pressure applied to the lead frame 2 by the ejector pin 6 is small, the lead frame 2 and the epoxy resin 4 cannot be in sufficient contact with each other, resulting in a decrease in the heat dissipation performance of the chip 1.
Disclosure of Invention
The invention provides a chip package to prevent conductive connection between a lead frame and a heat sink.
The invention provides a chip package which comprises a lead frame, a chip assembly arranged on the lead frame and a packaging layer for packaging the chip assembly. The lead frame is provided with a first surface and a second surface which are opposite, and the chip assembly is arranged on the first surface of the lead frame. And a top pinhole is arranged on the packaging layer. The chip package further includes a heat dissipation assembly disposed on the second side of the lead frame. The heat dissipation assembly comprises a heat dissipation sheet, an adhesive layer for adhering the heat dissipation sheet and the second surface of the lead frame, and an insulating block arranged between the heat dissipation sheet and the second surface and used for isolating the heat dissipation sheet from the second surface. Wherein, the insulating block is opposite to the position of the thimble hole.
In the scheme, the insulating block used for isolating the radiating fin from the second surface is arranged between the second surface of the lead frame and the radiating fin, and the insulating block is opposite to the thimble hole, so that in the packaging process of the chip packaging piece, even if the thimble applies large pressure to the lead frame through the thimble hole, the lead frame cannot press through the adhesive layer, the lead frame is prevented from contacting with the radiating fin, and the chip is prevented from being short-circuited. And under the condition that the thimble applies larger pressure to the lead frame, the lead frame can be fully contacted with the bonding layer, so that the heat dissipation performance of the chip is ensured.
In one embodiment, the dielectric block is embedded in the heat sink and the adhesive layer to facilitate the placement of the dielectric block.
In a specific embodiment, a first groove is formed on the side of the heat sink facing the adhesive layer, and a second groove is formed on the side of the adhesive layer facing the heat sink. The first groove is opposite to the second groove, and the insulating block is arranged in the first groove and the second groove. Through the mode, the insulating block is embedded between the radiating fin and the adhesive layer.
In a particular embodiment, the insulator block is interference fit within the first recess to facilitate assembly of the insulator block.
In one embodiment, the first groove and the second groove are rectangular grooves, so as to facilitate the grooving of the heat sink.
In a specific embodiment, the first groove has a length L1The length of the radiating fin is L2Wherein L is1≤1/5L2So as to improve the bonding stability between the heat sink and the bonding layer.
In a specific embodiment, the first groove has a depth D1The thickness of the heat sink is H1Wherein D is1≤1/2H1To prevent the heat sink from being broken due to local thinness.
In a specific embodiment, the second groove has a depth D2The depth of the bonding layer is H2Wherein D is2≤1/2H2So as to ensure the bonding stability between the bonding layer and the lead frame.
In a specific embodiment, the material of the insulating block is a heat conducting material to improve the heat dissipation performance of the chip. When the insulating block is specifically provided, the material of the insulating block may be ceramic to prevent the insulating block from being crushed by the pressure exerted on the lead frame by the thimble.
In a particular embodiment, the insulating block is shaped as a cube to facilitate the positioning of the insulating block.
In one embodiment, the heat sink is a copper heat sink to improve heat dissipation performance of the chip and save cost.
In one embodiment, the material of the adhesive layer is epoxy resin, so as to improve the stability and thermal conductivity of the adhesive between the lead frame and the heat sink.
In one particular embodiment, the lead frame is a copper frame to save costs.
Drawings
Fig. 1 is a schematic structural diagram of a chip package in the prior art;
fig. 2 is a schematic structural diagram of a chip package according to an embodiment of the present invention.
Reference numerals:
10-lead frame 11-first side 12-second side
20-chip assembly 30-encapsulation layer 31-pin hole
32-thimble 41-heat sink 411-first groove
42-adhesive layer 421-second groove 50-insulating block
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
To facilitate understanding of the chip package provided by the embodiment of the invention, an application scenario thereof is first described. The chip package may be specifically a power module package such as, but not limited to, an IGBT module, and may also be other types of chip packages. The chip package provided by the embodiment of the invention is described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a chip package according to an embodiment of the present invention includes a lead frame 10 and a chip assembly 20 disposed on the lead frame 10. The lead frame 10 is a frame structure conventionally used for arranging chips in the prior art, and may be a copper frame in particular, so as to save cost. The lead frame 10 shown in fig. 2 has a first surface 11 and a second surface 12 opposite to each other. A chip module 20 is provided on the first surface 11 of the lead frame 10. The chip assembly 20 may include a chip, which may specifically be an IGBT chip, an FRD chip, or other types of chips. Two chips may be disposed on the chip assembly 20, for example, one IGBT chip and one FRD chip may be disposed on the first surface 11 of the lead frame 10. It should be understood that the number of chips included in the chip assembly 20 is not limited to the above-described embodiment, and other embodiments are possible. Specifically, when the chip module 20 is provided on the first surface 11 of the lead frame 10, soldering may be used, or another method may be used.
Referring to fig. 2, an encapsulation layer 30 is further disposed on the first surface 11 of the lead frame 10 and the chip assembly 20 to encapsulate the chip assembly 20. In a specific configuration, the material of the encapsulation layer 30 may be epoxy resin, silica gel, or other materials capable of encapsulating chips in the prior art.
With continued reference to fig. 2, to improve the heat dissipation performance of the chip, a heat dissipation assembly for dissipating heat from the chip assembly 20 is disposed on the second surface 12 of the lead frame 10. The heat dissipation assembly shown in fig. 2 includes a heat dissipation plate 41, and the heat dissipation plate 41 may be a metal plate such as a copper heat dissipation plate 41, an aluminum heat dissipation plate 41, or an alloy heat dissipation plate 41, so as to improve the heat dissipation performance of the chip and save the cost.
In addition, to prevent contact between the heat sink 41 and the lead frame 10, the heat sink 41 is adhered to the second surface 12 of the lead frame 10 by the adhesive layer 42. In a specific configuration, the material of the adhesive layer 42 may be epoxy resin, which not only realizes heat conduction between the lead frame 10 and the heat sink 41 to improve the heat dissipation performance of the chip assembly 20, but also prevents contact between the lead frame 10 and the heat sink 41 to short-circuit the chip assembly 20. It should be understood that the material of the adhesive layer 42 is not limited to the epoxy resin, and other materials that are insulating materials and can adhere the heat sink 41 and the lead frame 10 may be used.
Specifically, when the heat sink 41 is disposed on the second surface 12 of the lead frame 10, in order to ensure that the bonding between the lead frame 10 and the adhesive layer 42 and between the adhesive layer 42 and the heat sink 41 is reliable, referring to fig. 2, the thimble 32 is pressed against the first surface 11 of the lead frame 10, so that the lead frame 10 is pressed downward (referring to the chip package shown in fig. 2), and thus the pressure for pressing the second surface 12 of the lead frame 10, the adhesive layer 42, and the heat sink 41 together is provided, thereby improving the stability of the bonding between the heat sink 41 and the lead frame 10. In a specific arrangement, referring to fig. 2, the encapsulation layer 30 has an ejector pin hole 31 for allowing an ejector pin 32 to pass through, and the ejector pin 32 is pressed against the first surface 11 of the lead frame 10 by passing through the ejector pin hole 31.
In order to prevent the thimble 32 from pressing against the lead frame 10 too deeply, which may cause the lead frame 10 to be embedded into the adhesive layer 42 too deeply, and thus the heat sink 41 to contact the lead frame 10, referring to fig. 2, an insulating block 50 for isolating the heat sink 41 from the second surface 12 is disposed between the heat sink 41 and the second surface 12, wherein the insulating block 50 is opposite to the thimble hole 31. By arranging the insulating block 50 for isolating the heat sink 41 from the second surface 12 between the second surface 12 of the lead frame 10 and the heat sink 41, and the insulating block 50 is opposite to the thimble hole 31, in the packaging process of the chip package, even if the thimble applies a large pressure to the frame of the lead frame 10 through the thimble hole 31, the lead frame 10 does not press through the adhesive layer 42, so that the lead frame 10 is prevented from contacting the heat sink 41, and the short circuit of the chip is prevented. And under the larger pressure applied to the lead frame 10 by the thimble 32, the lead frame 10 can be fully contacted with the adhesive layer 42, so that the heat dissipation performance of the chip is ensured.
When the heat sink is disposed, the insulating block 50 may be embedded in the heat sink 41 and the adhesive layer 42 to facilitate the disposition of the insulating block 50. Specifically, referring to fig. 2, a first groove 411 may be formed on the heat sink 41 toward the surface of the adhesive layer 42, and a second groove 421 may be formed on the adhesive layer 42 toward the surface of the heat sink 41. The first recess 411 is opposite to the second recess 421, so that the insulation block 50 is disposed in the first recess 411 and the second recess 421. In the above manner, the insulating block 50 is embedded between the heat sink 41 and the adhesive layer 42. When the insulating block 50 is fixed in the first groove 411 and the second groove 421, the insulating block 50 can be assembled in the first groove 411 in an interference manner, so that the assembling of the insulating block 50 is facilitated; the insulation block 50 can be adhered in the first groove 411 and the second groove 421 by gluing, so as to fix the insulation block 50 in the first groove 411 and the second groove 421.
In addition, the first recess 411 and the second recess 421 may be rectangular grooves, and the first recess 411 is opposite to the thimble hole 31, so as to form a groove on the heat sink 41. In specifically providing the first recess 411, referring to fig. 2, the length of the first recess 411 (the left-right direction in the chip package shown in fig. 2 is the length direction of the first recess 411) is L1The length of the heat sink 41 (the left-right direction in the chip package shown in fig. 2 is the longitudinal direction of the heat sink 41) is L2. Wherein L is1≤1/5L2To prevent the first recess 411 from being too long, thereby affecting the heat sink 41 and the adhesive layerThe bonding area of the heat sink 41 and the adhesive layer 42 affects the stability of the bonding between the heat sink 41 and the adhesive layer 42, thereby improving the stability of the bonding between the heat sink 41 and the adhesive layer 42. In particular, the length L of the first groove 411 may be set1＝1/5L2、L1＝1/6L2、L1＝1/7L2、L1＝1/8L2Equal to or less than 1/5L2Any value of (c).
With continued reference to fig. 2, the depth of the first recess 411 (the height of the first recess 411 in the up-down direction in the chip package shown in fig. 2 is the thickness of the first recess 411) is D1The thickness of the heat sink 41 (the height of the heat sink 41 in the vertical direction in the chip package shown in fig. 2 is the thickness of the heat sink 41) is H1. Wherein D is1≤1/2H1To prevent the heat sink 41 from being broken due to local thinness. Specifically, the thickness D of the first recess 411 may be set1＝1/2H1、D1＝1/3H1、D1＝1/4H1、D1＝1/5H1、D1＝1/6H1Equal to or less than 1/2H1Any value of (c).
When the second groove 421 is provided, the second groove 421 is opposite to the pinhole 31 on the encapsulation layer 30. In addition, referring to fig. 2, the depth of the second groove 421 ((the height of the second groove 421 in the up-down direction in the chip package shown in fig. 2 is the thickness of the second groove 421)) is D2The depth of the adhesive layer 42 (the height of the adhesive layer 42 in the vertical direction in the chip package shown in fig. 2 is the thickness of the adhesive layer 42) is H2. Wherein D is2≤1/2H2To ensure the stability of the adhesion between the adhesive layer 42 and the lead frame 10. Specifically, the thickness D of the second groove 421 may be set2＝1/2H2、D2＝1/3H2、D2＝1/4H2、D2＝1/5H2、D2＝1/6H2Equal to or less than 1/2H2Any value of (c).
In particular, when the insulation block 50 is disposed, the insulation block 50 has a cubic shape so that the insulation block 50 is disposed in the first and second grooves 411 and 421. It should be understood that the shape of the insulation block 50 is not limited to the cube shown above, and correspondingly, the first and second grooves 411 and 421 are not limited to the rectangular grooves shown above, and other ways can be adopted. That is, it is within the scope of the present invention that the insulating block 50 is disposed opposite to the top pin hole 31 and between the second surface 12 of the lead frame 10 and the heat sink 41. For example, the shape of the insulation block 50 may be circular, and in this case, the shape of the first recess 411 and the second recess 421 is also circular, so that the first recess 411 and the second recess 421 can accommodate the insulation block 50.
In addition, the material of the insulating block 50 may be a heat conductive material to improve the heat dissipation performance of the chip. Specifically, the material of the dielectric block 50 may be ceramic to prevent the dielectric block 50 from being crushed by the pressure exerted by the thimble 32 on the lead frame 10. It should be understood that the material of the insulating block 50 is not limited to ceramic, but may be other insulating materials capable of conducting heat and withstanding a certain pressure in the prior art.
By arranging the insulating block 50 for isolating the heat sink 41 from the second surface 12 between the second surface 12 of the lead frame 10 and the heat sink 41, and the insulating block 50 is opposite to the thimble hole 31, in the packaging process of the chip package, even if the thimble 32 applies a large pressure to the frame of the lead frame 10 through the thimble hole 31, the lead frame 10 does not press through the adhesive layer 42, so that the lead frame 10 is prevented from contacting the heat sink 41, and the short circuit of the chip is prevented. And under the larger pressure applied to the lead frame 10 by the thimble 32, the lead frame 10 can be fully contacted with the adhesive layer 42, so that the heat dissipation performance of the chip is ensured.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A chip package, comprising:
a lead frame having opposing first and second faces;
a chip assembly disposed on the first side;
an encapsulation layer encapsulating the chip assembly, the encapsulation layer having a pin hole;
the heat dissipation assembly is arranged on the second surface and comprises a heat dissipation fin, an adhesive layer and an insulating block, wherein the adhesive layer is used for adhering the heat dissipation fin and the second surface, and the insulating block is arranged between the heat dissipation fin and the second surface and used for isolating the heat dissipation fin and the second surface; the insulating block is opposite to the thimble hole.
2. The chip package of claim 1, wherein the insulating block is embedded within the heat sink and the adhesive layer.
3. The chip package of claim 2, wherein a first groove is formed on a surface of the heat sink facing the adhesive layer, and a second groove is formed on a surface of the adhesive layer facing the heat sink; the first groove is opposite to the second groove, and the insulating block is arranged in the first groove and the second groove.
4. The chip package of claim 3, wherein the first recess and the second recess are both rectangular slots.
5. The chip package of claim 4, wherein the first groove has a length L1The length of the radiating fin is L2(ii) a Wherein L is1≤1/5L2。
6. The chip package of claim 3, wherein the first recess has a depth D1The thickness of the radiating fin is H1(ii) a Wherein D is1≤1/2H1。
7. The chip package of claim 3, wherein the second recess has a depth D2The thickness of the bonding layer is H2(ii) a Wherein D is2≤1/2H2。
8. The chip package of any one of claims 1-7, wherein the insulating block is a thermally conductive material.
9. The chip package of claim 8, wherein the insulating block is made of ceramic.
10. The chip package of any one of claims 1-7, wherein the insulating block is cubic in shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910806941.7A CN112447650A (en) | 2019-08-29 | 2019-08-29 | Chip packaging part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910806941.7A CN112447650A (en) | 2019-08-29 | 2019-08-29 | Chip packaging part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112447650A true CN112447650A (en) | 2021-03-05 |
Family
ID=74741970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910806941.7A Pending CN112447650A (en) | 2019-08-29 | 2019-08-29 | Chip packaging part |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112447650A (en) |
-
2019
- 2019-08-29 CN CN201910806941.7A patent/CN112447650A/en active Pending
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