CN112399107B

CN112399107B - 7T global shutter pixel structure based on semi-floating gate

Info

Publication number: CN112399107B
Application number: CN201910742833.8A
Authority: CN
Inventors: 徐江涛; 李凤; 史兴萍; 王瑞硕; 夏梦真
Original assignee: Tianjin University Marine Technology Research Institute
Current assignee: Tianjin University Marine Technology Research Institute
Priority date: 2019-08-13
Filing date: 2019-08-13
Publication date: 2023-05-26
Anticipated expiration: 2039-08-13
Also published as: CN112399107A

Abstract

A7T global shutter pixel structure based on a semi-floating gate comprises a semi-floating gate device M _SFG Six switching tubes and two capacitors; first half floating gate M _SFG Resetting, exposing, completing resetting of the capacitor C during the exposure period, sampling and storing reset signals to the capacitors C1 and C2, sampling and storing optical signals to the capacitor C1 after the exposure is completed, and finally sequentially reading out the reset signals and the optical signals to complete one working period of the pixel structure provided by the invention; the structure solves the voltage distribution problem of the traditional 8T pixel photoelectric detection region and the photoelectric conversion region, and compared with the 8T pixel, the structure reduces one MOS tube and increases the filling factor.

Description

7T global shutter pixel structure based on semi-floating gate

Technical Field

The invention relates to the field of CMOS image sensors, in particular to a 7T global shutter pixel structure based on a semi-floating gate.

Background

Since the invention of passive pixel image sensors in the 60 s of the last century, CMOS image sensors have been largely classified into rolling shutter CMOS image sensors and global shutter CMOS image sensors according to the difference of exposure modes. The rolling shutter CMOS image sensor is different from the global shutter CMOS image sensor in that the pixel array of the rolling shutter CMOS image sensor is exposed row by row, whereas the global shutter CMOS image sensor is exposed simultaneously for the entire pixel array. When capturing fast moving objects, rolling shutter CMOS image sensors can cause jelly effects due to the time difference in exposure of each row of pixels, while global shutter CMOS image sensors solve this drawback. Global shutter CMOS image sensors have become the best choice in the field of high-speed photography.

The core of the global shutter CMOS image sensor design is the "global shutter pixel". The global shutter pixel design requires the introduction of an additional storage node for storing the photo-generated signal after exposure. Currently, the types of storage nodes are classified into charge domain global shutter pixels and voltage domain global shutter pixels. The charge domain global shutter pixel mainly includes the following types: the first type is a 5T pixel structure which adopts a floating diffusion node as a photo-generated signal charge storage node, the second type is a 6T pixel and a 7T pixel which adopt a MOS capacitor under a polysilicon gate similar to a CCD to store photo-generated signal charges, and the third type is a 6T pixel which adopts a photodiode of a surface clamping process to store the photo-generated signal charges. The first type of charge domain global shutter pixel has large filling factor, but the global shutter has low efficiency, low readout noise and is not commonly used. The second and third types of charge domain global shutter pixels, while completely eliminating KTC noise relative to the first type, have significantly improved global shutter efficiency, but have relatively small fill factors and high process requirements. The voltage domain global shutter pixels mainly include 7T global shutter pixels and 8T global shutter pixels. The 7T global shutter pixel fill factor is small and the readout noise is large. The 8T global shutter pixel fill factor is the smallest but the global shutter efficiency is the highest among the global shutter pixels.

At present, although the 8T pixel structure is most commonly used, since the front part circuit structure is the same as that of the conventional 4T pixel structure, there is a problem in that voltage distribution in the photoelectric detection region and the photoelectric conversion region in the conventional 4T pixel is difficult. And the front-lit 8T pixel fill factor is small.

Disclosure of Invention

Aiming at the technical problems in the prior art, the invention provides a 7T global shutter pixel structure based on a semi-floating gate. Based on a semi-floating gate device, the design introduces two capacitors and six MOS tubes, solves the voltage distribution problem of the traditional 8T pixel photoelectric detection region and photoelectric conversion region, reduces one MOS tube relative to 8T pixels, and increases the filling factor.

A 7T global shutter pixel structure based on a semi-floating gate,as shown in fig. 1, comprises a semi-floating gate device M _SFG Six switching tubes and two capacitors; wherein the semi-floating gate device is used for collecting signal charges, and the capacitors C1 and C2 are used for storing a signal level and a reset level from the semi-floating gate, respectively. C1 and C2 can be any type of capacitance, depending on the particular design; the capacitor C is an equivalent capacitor of the half floating gate drain terminal; the six switching tubes can be any type of switching tube, and are respectively used as the source follower M according to specific design _SF Reset tube M _RST Select pipe M _SEL And sampling switch M _S1 、M _S2 . Wherein the switching tube M _S1 And M _S2 The sampling device is used for sampling the control signal level and the reset level respectively; the reset tube is used for resetting the signal in the capacitor; the selection tube is used for controlling the output of the pixel array row signals through time sequence. Semi-floating gate M in the invention _SFG The grid electrode is connected with the control signal line CG, the source electrode is connected with fixed voltage, and the drain electrode is simultaneously connected with the source electrode/drain electrode of the reset tube and the switch tube M _PC And M _S1 Is a member of the group; reset tube M _RST The drain/source is connected with the power supply, the grid is connected with the control signal RST, and the source/drain is simultaneously connected with the switch tube M _PC And M _S1 Is provided. M is M _S1 Source/drain and M of (2) _S2 Is connected with the drain/source of the capacitor C1 and the other end is connected with M _PC ；M _S2 Drain/source and M of (2) _S1 Source/drain connected to one end of capacitor C2 and M _SF Is connected to the gate of (c). One end of C1 and C2 is respectively connected with M _S1 And M _S2 And the other ends are grounded. M is M _SF Gate and M of (2) _S2 And one end of the capacitor C2. M is M _SEL Gate connected to control signal SEL, source/drain connected to M _SF The other end of the output signal is output. And the substrates of all the switch tubes are grounded if the switch tubes are NMOS tubes, and are connected with a power supply if the switch tubes are PMOS tubes.

A7T global shutter pixel structure based on a semi-floating gate, the working sequence is shown in fig. 2, and comprises 8 sequence signals: CG is M _SFG Controlling a time sequence; s is M _SFG The source electrode always maintains a voltage of about 1.6V; d is M _SFG A drain electrode; RST is reset tube M _RST Is controlled by the control timing of (a); PC is a switch tube M _PC Is controlled by the control timing of (a); s1 is a switch tube M _S1 Is controlled by the control timing of (a); s2 is a switch tube M _S2 Is controlled by the control timing of (a); SEL is a selection tube M _SEL Is controlled by the control timing of (a). And

reference numerals

1, 2, 3, 4, 5, 6, 7 in fig. 2 denote 7 working phases of the pixel, respectively: stage 1 is a semi-floating gate device M _SFG Is aimed at M _SFG Resetting; stage 2 is the pixel exposure stage, which is intended to expose the pixel, M _SFG Collecting signal charges; the stage 3 is a capacitor C reset stage, which is positioned at the later stage of pixel exposure and aims to reset the capacitor C; stage 4 is a pixel reset signal sampling stage, which is aimed at sampling the reset signal in capacitor C into capacitors C1 and C2; stage 5 is a pixel optical signal sampling stage, which is aimed at sampling an optical signal onto the capacitor C1; stage 6 is a reset signal readout stage, intended to read out the reset signal to the readout circuit; stage 7 is an optical signal readout stage, intended to read out an optical signal to a readout circuit. Therefore, the working principle of the pixel structure is as follows: first half floating gate M _SFG Resetting, exposing, completing resetting of the capacitor C during the exposure period, sampling and storing reset signals to the capacitors C1 and C2, sampling and storing optical signals to the capacitor C1 after the exposure is completed, and finally sequentially reading out the reset signals and the optical signals, thereby completing one working period of the pixel structure. The working sequence of the pixel structure proposed by the present invention is not limited to the sequence design shown in fig. 2, and can be modified according to the specific design.

Compared with the traditional 8T pixel, the 7T global shutter pixel structure based on the semi-floating gate solves the problem of voltage distribution between a photodiode and a photoelectric conversion zone in the traditional 8T pixel due to the introduction of the semi-floating gate, so that the novel 7T global shutter pixel structure can realize high-full-well capacity and high global shutter efficiency design; the novel 7T global shutter pixel structure has higher pixel filling factor due to the fact that one switching tube is reduced; the correlated double sampling technology can be realized, the thermal noise is completely eliminated, and the correlated double sampling technology can be used for designing a low-readout noise global shutter CMOS image sensor.

Drawings

FIG. 1 is a schematic diagram of a semi-floating gate based 7T global shutter pixel;

fig. 2 is a timing diagram of pixel operation.

Detailed Description

For further clarity of objects, technical solutions and advantages of the present invention, the following specific embodiments of the present invention are given in connection with examples. In this example:

semi-floating gate device M _SFG An NMOS tube is adopted, and the width-to-length ratio is (1.2 mu m)/(6 mu m); switch tube M _PC An NMOS tube is adopted, and the width-to-length ratio is (4 mu m)/(5 mu m); reset tube M _RST An NMOS tube is adopted, and the width-to-length ratio is (4 mu m)/(0.35 mu m); source follower M _SF An NMOS tube is adopted, and the width-to-length ratio is (4 mu m)/(6 mu m); select pipe M _SEL An NMOS tube is adopted, and the width-to-length ratio is (4 mu m)/(5 mu m); switch tube M _S1 And M _S2 NMOS tubes are adopted, and the width-to-length ratio is (4 mu m)/(5 mu m); the capacitors C1 and C2 are both in MOS type capacitor structures, and the capacitance values are both 4fF.

In the timing design, the high level is 3.3V and the low level is 0V. And the parameters of one exposure period in the timing design part are designed as follows: the phase 1 is 2 mu s, the phase 2 is 24 mu s-1 ms, the phase 3 is 4 mu s, the phase 4 is 3 mu s, the phase 5 is 3 mu s, the phase 6 is 3 mu s, and the phase 7 is 3 mu s.

The above design examples are only for further illustrating the technical solution of the present invention, and are not limiting the invention.

Claims

1. A7T global shutter pixel structure based on a semi-floating gate is characterized in that: comprising a semi-floating gate device M _SFG Six switching tubes and two capacitors; semi-floating gate M _SFG The grid electrode is connected with the control signal line CG, the source electrode is connected with fixed voltage, and the drain electrode is simultaneously connected with the reset tube M _RST A terminal of (a) and a switching tube M _PC And M _S1 Is a member of the group; capacitor C is a semi-floating gate M _SFG Equivalent capacitance of drain terminal, reset tube M _RST B is connected with a power supply, the grid electrode is connected with a control signal RST and a reset tube M _RST A end is connected with a switch tube M at the same time _PC And M _S1 Is a member of the group; m is M _S1 A and M of (c) _S2 Is connected to the terminal B of the capacitor C1And M is connected with _S1 B-termination M of (C) _PC ；M _S2 B-terminal and M-terminal of (C) _S1 Is connected with one end of a capacitor C2 and the grid electrode of the MSF; one end of C1 and C2 is respectively connected with M _S1 And M _S2 The other ends of the two connecting rods are grounded; m is M _SF Gate and M of (2) _S2 And one end of the capacitor C2 is connected; m is M _SEL Gate electrode of (a) is connected with control signal SEL, M _SEL The A end of the (B) is connected with one end of the MSF, and the other end of the (B) is output; wherein, when the A end is a source electrode, the B end is a drain electrode; when the end A is a drain electrode, the end B is a source electrode; and the substrates of all the switch tubes are grounded if the switch tubes are NMOS tubes, and are connected with a power supply if the switch tubes are PMOS tubes.

2. The 7T global shutter pixel structure based on a semi-floating gate of claim 1, wherein: comprising 8 timing signals: CG is M _SFG Controlling a time sequence; s is the voltage of MSFG source electrode which is always kept about 1.6V; d is M _SFG A drain electrode; RST is reset tube M _RST Is controlled by the control timing of (a); PC is a switch tube M _PC Is controlled by the control timing of (a); s1 is a switch tube M _S1 Is controlled by the control timing of (a); s2 is a switch tube M _S2 Is controlled by the control timing of (a); SEL is a selection tube M _SEL Is controlled by the control timing of (a);

stage 1 is the reset stage of the semi-floating gate device MSFG, for M _SFG Resetting; stage 2 is a pixel exposure stage, exposing the pixels, M _SFG Collecting signal charges; the phase 3 is a reset phase of the capacitor C, and the phase is positioned at the later stage of pixel exposure and resets the capacitor C; the phase 4 is a pixel reset signal sampling phase, and samples the reset signal in the capacitor C to the capacitors C1 and C2; stage 5 is a pixel optical signal sampling stage, which samples an optical signal onto the capacitor C1; stage 6 is a reset signal reading stage, which reads out the reset signal to a reading circuit; stage 7 is an optical signal reading stage, which reads out an optical signal to a readout circuit.