CN112397443A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112397443A
CN112397443A CN201910750640.7A CN201910750640A CN112397443A CN 112397443 A CN112397443 A CN 112397443A CN 201910750640 A CN201910750640 A CN 201910750640A CN 112397443 A CN112397443 A CN 112397443A
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layer
forming
contact hole
semiconductor structure
conductive
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CN112397443B (en
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张田田
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Shenzhen Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Shenzhen Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, forming an active drain doping region in the substrate, forming an interlayer dielectric layer on the substrate, and forming a contact hole exposing the source drain doping region in the interlayer dielectric layer; forming a metal layer on the source drain doped region exposed out of the contact hole; forming a conductive layer filling the contact hole on the metal layer; and carrying out first annealing treatment to convert the metal layer, the source drain doped region and the conducting layer with partial thickness into a silicide layer, and taking the residual conducting layer in the contact hole as a contact hole plug. In the embodiment of the invention, the contact hole plug can be directly contacted with the silicide layer, so that the contact performance between the contact hole plug and the source drain doped region is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In the current MOS transistor process, in order to improve the ohmic contact between the gate, the source, and the drain of the transistor and the contact plug (plug), a metal silicide is usually formed on the surface of the gate, the source, and the drain. Currently, a Self-Aligned metal Silicide (Self-Aligned Silicide) process is mostly used to form a metal Silicide. Specifically, after forming the source and drain electrodes, a metal layer composed of cobalt, titanium, nickel, or the like is formed over the source, drain, and gate electrodes, and then the metal layer is reacted with silicon in the gate electrodes, source, and drain electrodes through one or more rapid annealing processes (RTA) to form a low-resistivity metal silicide, thereby reducing the sheet resistance (Rs) of the source and drain electrodes.
With the decreasing feature size of transistors, nickel silicide and platinum silicide are widely used as contact salicide due to their characteristics of smaller sheet resistance, less silicon consumption, and lower annealing temperature.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which can improve the contact performance between a contact hole plug and a source drain doped region.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, forming an active drain doping region in the substrate, forming an interlayer dielectric layer on the substrate, and forming a contact hole exposing the source drain doping region in the interlayer dielectric layer; forming a metal layer on the source drain doped region exposed out of the contact hole; forming a conductive layer filling the contact hole on the metal layer; and carrying out first annealing treatment to convert the metal layer, the source drain doped region and the conducting layer with partial thickness into a silicide layer, and taking the residual conducting layer in the contact hole as a contact hole plug.
Optionally, before the first annealing treatment, the forming method further includes: and forming a diffusion barrier layer on the side wall of the contact hole.
Optionally, before forming the metal layer, the forming method further includes: forming a pad layer on a sidewall of the contact hole; the step of forming the diffusion barrier layer comprises: and performing second annealing treatment after the step of forming the conducting layer to convert the liner layer and the conducting layer with partial thickness into the diffusion barrier layer.
Optionally, the metal layer is formed by a selective chemical vapor deposition process.
Optionally, in the step of forming the metal layer, the thickness of the metal layer is
Figure BDA0002167064930000021
To
Figure BDA0002167064930000022
Optionally, the temperature of the second annealing treatment is 400 ℃ to 450 ℃.
Optionally, the material of the diffusion barrier layer includes CoSiN.
Optionally, in the step of forming the pad layer, the pad layer has a thickness of
Figure BDA0002167064930000023
To
Figure BDA0002167064930000024
Optionally, the step of forming the conductive layer includes: and forming an adhesive layer which conformally covers the side wall of the contact hole and the metal layer.
Optionally, the step of forming the conductive layer further includes: after the adhesive layer is formed, a conductive material layer filling the contact hole is formed on the adhesive layer, and the conductive material layer and the adhesive layer are used for forming the conductive layer.
Optionally, the step of forming the conductive layer further includes: after forming the bonding layer, forming a seed layer conformally covering the bonding layer; and forming a conductive material layer for filling the contact hole on the seed layer, wherein the conductive material layer, the seed layer and the bonding layer are used for forming the conductive layer.
Optionally, the first annealing treatment is performed by using a dynamic surface annealing process.
Optionally, in the step of forming the silicide layer, a material of the silicide layer includes CoSix、TiSixAnd CoTiSixOne or more of (a).
Optionally, in the step of forming the conductive layer, the conductive layer further covers the top of the interlayer dielectric layer; after the second annealing treatment is performed, the forming method further includes: and removing the conducting layer higher than the interlayer dielectric layer by adopting a planarization process.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the source-drain doped region is positioned in the substrate; the interlayer dielectric layer is positioned on the substrate, and a contact hole exposing the source-drain doped region is formed in the interlayer dielectric layer; the silicide layer is positioned on the source drain doped region at the bottom of the contact hole; a contact hole plug in the contact hole and in direct contact with the silicide layer.
Optionally, the semiconductor structure further includes: and the diffusion barrier layer is positioned between the interlayer dielectric layer and the contact hole plug.
Optionally, the semiconductor structure further includes: the liner layer is positioned between the interlayer dielectric layer and the diffusion barrier layer; the diffusion barrier layer is formed by converting a partial thickness of the liner layer and the contact hole plug.
Optionally, the thickness of the diffusion barrier layer is
Figure BDA0002167064930000031
To
Figure BDA0002167064930000032
Optionally, the material of the diffusion barrier layer includes CoSiN.
Optionally, the material of the silicide layer includes one or more of CoSix, TiSix, and CoTiSix.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, before the first annealing treatment is carried out, the metal layer is formed, and the conducting layer for filling the contact hole is formed on the metal layer, wherein the conducting layer is formed, a binding layer which is in conformal coverage with the side wall of the contact hole and the metal layer is usually required to be formed, and the forming of the metal layer and the forming of the binding layer are both film-forming processes.
In addition, the steps of forming the metal layer and forming the bonding layer are performed on the same machine, and the bonding layer can protect the metal layer, so that the problem that the metal layer is oxidized in the process of machine conversion is solved, and the formation quality of a subsequent silicide layer is improved.
Drawings
Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 5 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 4, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate 1 is provided, a source-drain doped region 2 is formed in the substrate 1, an interlayer dielectric layer 3 is formed on the substrate 1, and a contact hole 4 exposing the source-drain doped region 2 is formed in the interlayer dielectric layer 3.
Referring to fig. 2, a metal layer 5 conformally covering the bottom and sidewalls of the contact hole 4 is formed; a protective layer 6 is formed conformally covering the metal layer 5.
Referring to fig. 3, an annealing process 10 is performed to convert the metal layer 5 and a portion of the thickness of the source/drain doped region 2 into a silicide layer 7.
Referring to fig. 4, after the silicide layer 7 is formed, a contact hole plug 8 filling the contact hole 4 is formed.
In the semiconductor field, the steps of forming the metal layer 5 and performing the annealing treatment 10 are usually performed on different machines, and during the machine conversion, there is usually a vacuum break (Air break), that is, the metal layer 5 is exposed to Air. Therefore, after the metal layer 5 is formed, the protective layer 6 for protecting the metal layer 5 is usually formed, so that the problem of oxidation of the metal layer 5 due to contact with air can be prevented, or the protective layer 6 can prevent the problem of oxidation of the remaining metal layer 5 that has not completely reacted after the silicide layer 7 is formed.
However, after the contact hole plug 8 is formed, the protective layer 6 is further formed between the contact hole plug 8 and the silicide layer 7, and the contact hole plug 8 is not in direct contact with the silicide layer 7, which easily results in poor contact performance between the contact hole plug 8 and the source/drain doped region 2, and in the field of semiconductors, contact resistance between the contact hole plug 8 and the source/drain doped region 2 is one of main factors affecting interconnection performance of devices, and the contact performance between the contact hole plug 8 and the source/drain doped region 2 has a significant effect on interconnection performance of devices.
In addition, the protective layer 6 is usually a material with higher resistivity and poorer conductivity, and the protective layer 6 is located between the silicide layer 7 and the contact hole plug 8, so that the contact resistance between the contact hole plug 8 and the source/drain doped region 2 is further easily increased, and the performance of the formed semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, forming an active drain doping region in the substrate, forming an interlayer dielectric layer on the substrate, and forming a contact hole exposing the source drain doping region in the interlayer dielectric layer; forming a metal layer on the source drain doped region exposed out of the contact hole; forming a conductive layer filling the contact hole on the metal layer; and carrying out first annealing treatment to convert the metal layer, the source drain doped region and the conducting layer with partial thickness into a silicide layer, and taking the residual conducting layer in the contact hole as a contact hole plug.
In the embodiment of the invention, before the first annealing treatment is carried out, the metal layer is formed, and the conducting layer for filling the contact hole is formed on the metal layer, wherein forming the conductive layer typically requires forming an adhesion layer conformally covering the sidewalls of the contact hole and the metal layer, wherein forming the metal layer and forming the adhesion layer are both film forming processes, therefore, the embodiments of the invention can perform the steps of forming the metal layer and forming the adhesive layer on the same machine, without forming a protective film for protecting the metal layer, so that after the silicide layer and the contact hole plug are formed subsequently, the contact hole plug can be in direct contact with the silicide layer, which is beneficial to reducing the contact resistance between the contact hole plug and the source drain doped region, and the contact performance between the contact hole plug and the source drain doped region is improved.
In addition, the steps of forming the metal layer and forming the bonding layer are performed on the same machine, and the bonding layer can protect the metal layer, so that the problem that the metal layer is oxidized in the process of machine conversion is solved, and the formation quality of a subsequent silicide layer is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 5 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5, a substrate 100 is provided, a source-drain doped region 110 is formed in the substrate 100, an interlayer dielectric layer 120 is formed on the substrate 100, and a contact hole 200 exposing the source-drain doped region 110 is formed in the interlayer dielectric layer 120.
The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is used to form a planar field effect transistor, and the substrate 100 only includes a substrate. In other embodiments, when the base is used for forming a finfet, the base comprises a substrate and a fin protruding from the substrate.
In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
It should be noted that a gate structure (not shown) is usually formed on the substrate 100. The gate structure is used for controlling the on and off of the conductive channel when the field effect transistor works.
In this embodiment, the gate structure is a metal gate structure. The gate structure includes a high-k gate dielectric layer (not shown) and a gate electrode layer (not shown) over the high-k gate dielectric layer.
The high-k gate dielectric layer is made of a high-k dielectric material; wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO2. In other embodiments, the material of the high-k gate dielectric layer can be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
The gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the gate electrode layer is W.
In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure comprises a gate oxide layer and a gate layer positioned on the gate oxide layer.
The description of the gate structure is not repeated herein.
In this embodiment, the source-drain doped region 110 is located in the substrate 100 at two sides of the gate structure.
When an NMOS transistor is formed, the source-drain doped region 110 comprises a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, and therefore carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the source-drain doped region 110 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved, wherein the P-type ions are B ions, Ga ions or In ions.
The interlayer dielectric layer 120 is used for isolating adjacent devices, and the interlayer dielectric layer 120 is also used for isolating subsequent contact hole plugs.
Therefore, the material of the interlayer dielectric layer 120 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 120 has a single-layer structure, and the material of the interlayer dielectric layer 120 is silicon oxide.
The contact hole 200 is used to provide a spatial location for the subsequent formation of a contact hole plug.
Still to be noted, with continuing reference to fig. 5, in this embodiment, the forming method further includes: a liner layer 130 is formed on sidewalls of the contact hole 200.
The pad layer 130 is used to reduce the opening size of the contact hole 200, so as to meet the requirements of miniaturization and high integration of devices, and the pad layer 130 is also beneficial to reducing the difficulty of the process for forming the contact hole 200 and increasing the process window for forming the contact hole 200.
In addition, after a conductive layer filling the contact hole 200 is formed, the method further includes: and performing second annealing treatment to convert the liner layer 130 and the conductive layer with partial thickness into a diffusion barrier layer, wherein the liner layer 130 is also used for preparing the subsequent formation of the diffusion barrier layer.
In this embodiment, the material of the liner layer 130 includes silicon nitride. The silicon nitride material has higher density, thereby being beneficial to improving the effect of a subsequent diffusion barrier layer for blocking diffusion, and the silicon nitride material has lower dielectric constant and being beneficial to ensuring the isolation effect between adjacent contact hole plugs.
The liner layer 130 should not be too thin nor too thick. If the thickness of the pad layer 130 is too small, the pad layer 130 may not function as a reduction in the size of the opening of the contact hole 200, or the pad layer 130 may have too small a thickness for subsequent conversion into a diffusion barrier layer; if the thickness of the liner layer 130 is too large, the opening size of the contact hole 200 is easily too small, and further the size of the subsequent contact hole plug is easily too small, which easily causes the resistance of the contact hole plug and the contact resistance of the contact hole plug and the source/drain doped region 110 to be too large. For this reason, in this embodiment, the thickness of the liner layer 130 is
Figure BDA0002167064930000071
To
Figure BDA0002167064930000072
In this embodiment, the step of forming the liner layer 130 includes: forming a layer of liner material (not shown) conformally covering the bottom and sidewalls of the contact hole 200 and the top of the interlevel dielectric layer 120; and removing the gasket material layer at the bottom of the contact hole 200 and at the top of the interlayer dielectric layer 120, and using the residual gasket material layer as the gasket layer 130.
In this embodiment, the liner material layer is formed by an atomic layer deposition process.
In this embodiment, a dry etching process is used to remove the pad material layer at the bottom of the contact hole 200 and at the top of the interlayer dielectric layer 120.
Referring to fig. 6, a metal layer 140 is formed on the source/drain doped region 110 exposed by the contact hole 200.
The metal layer 140 is used for the subsequent formation of a silicide layer.
In this embodiment, the metal layer 140 is made of Ti. Ti is a metal material commonly used in forming a silicide layer in a semiconductor process, which is advantageous for improving process compatibility.
Specifically, in this embodiment, after a conductive layer is formed on the metal layer 140 to fill the contact hole 200, the method further includes: and performing first annealing treatment to convert the metal layer 140, the source drain doped region 110 and the conductive layer with partial thickness into silicide layers.
Therefore, the thickness of the metal layer 140 should not be too small, nor too large. If the thickness of the metal layer 140 is too small, the thickness of the metal layer 140 for forming the silicide layer later is too small, which easily causes the thickness of the silicide layer formed later to be too small, so that the effect of the silicide layer for reducing the contact resistance between the contact hole plug and the source-drain doped region 110 is not obvious; if the thickness of the metal layer 140 is too large, the distance between the subsequent conductive layer and the source/drain doped region 110 is too large, and the conductive layer is difficult to react with the source/drain doped region 110 with a part of the thickness, so that a silicide layer with low resistance is difficult to form. For this purpose, in this embodiment, the thickness of the metal layer 140 is
Figure BDA0002167064930000081
To
Figure BDA0002167064930000082
In this embodiment, the metal layer 140 is formed by a Selective chemical vapor deposition (Selective chemical vapor deposition) process.
The metal layer 140 is formed by using a selective deposition process, so that the metal layer 140 is directly formed on the source/drain doped region 110 exposed from the contact hole 200.
Compared with the scheme that the metal layer is also formed on the side wall of the contact hole and the interlayer dielectric layer, in the embodiment, the metal layer 140 is only formed on the source-drain doped region 110 exposed out of the contact hole 200, so that on one hand, the metal layer 140 on the side wall of the contact hole 200 is prevented from reducing the opening size of the contact hole 200, the size of a contact hole plug formed in the contact hole 200 subsequently is increased, and the resistance of the contact hole plug is reduced; on the other hand, the formation of a thicker film layer at the top corner of the contact hole is also favorably prevented, so that the process difficulty of subsequently forming a conductive layer for filling the contact hole 200 is reduced, the filling capability of the subsequent conductive layer in the contact hole 200 is improved, the probability of generating defects such as voids (void) in the conductive layer is reduced, and the formation quality of the conductive layer is correspondingly improved.
Specifically, in the present embodiment, the metal layer 140 is formed by a selective chemical vapor deposition process. Compared with the physical vapor deposition process, the selective chemical vapor deposition process has better covering capability, is beneficial to improving the covering capability of the metal layer 140 on the source/drain doped region 110 exposed out of the contact hole 200, and has high process compatibility and low process cost.
Referring to fig. 7 to 8, a conductive layer 150 filling the contact hole 200 is formed on the metal layer 140.
The conductive layer 150 is used for forming a contact hole plug in a subsequent step, and the conductive layer 150 with a partial thickness is further used for being converted into a silicide layer together with the metal layer 140 and the source/drain doped region 110 with a partial thickness after a subsequent first annealing treatment.
In addition, the partial thickness of the conductive layer 150 is used to be converted into a diffusion barrier layer with the partial thickness of the liner layer 130 after the second annealing treatment.
This embodiment forms the metal layer 140 and the conductive layer 150 filling the contact hole 200 on the metal layer 140 before the first annealing process is performed to form the silicide layer, wherein forming the conductive layer 150 typically requires forming an adhesion layer conformally covering the sidewalls of the contact hole 200 and the metal layer 140, wherein forming the metal layer 140 and forming the adhesion layer are both film forming processes, therefore, the steps of forming the metal layer 140 and forming the adhesive layer can be performed on the same machine, without forming a protective film for protecting the metal layer 140, so that after a silicide layer and a contact hole plug are formed subsequently, the contact hole plug can be in direct contact with the silicide layer, which is beneficial to reducing the contact resistance between the contact hole plug and the source drain doped region 110, thereby being beneficial to improving the contact performance between the contact hole plug and the source drain doped region 110.
In addition, in this embodiment, the steps of forming the metal layer 140 and forming the bonding layer are performed on the same machine, and the bonding layer can protect the metal layer 140, so as to prevent the metal layer 140 from being oxidized during the machine conversion process, thereby improving the formation quality of the subsequent silicide layer.
In this embodiment, the conductive layer 150 is made of cobalt. The resistivity of cobalt is lower, which is beneficial to reducing the resistance of the subsequent contact hole plug, and the diffusion coefficient of cobalt is lower, which is beneficial to reducing the probability of the occurrence of electromigration (Electro migration) problem of the contact hole plug.
In this embodiment, the step of forming the conductive layer 150 includes:
as shown in fig. 7, an adhesion layer 151 conformally covering the sidewalls of the contact hole 200 and the metal layer 140 is formed. Specifically, the adhesive layer 151 also covers the top of the interlayer dielectric layer 120.
The adhesive layer 151 serves to improve adhesion between the conductive layer and the contact hole 200.
In this embodiment, the adhesion layer 151 is formed by a Physical Vapor Deposition (PVD) process. The physical vapor deposition process has low cost. In particular, the physical vapor deposition process may be a sputtering (Sputter) process.
With continued reference to fig. 7, a Seed layer (Seed layer)152 is formed that conformally covers the adhesion layer 151.
The seed layer 152 is used to prepare the conductive material layer for subsequent formation. Specifically, the seed layer 152 is used to provide a good step coverage and continuity for an electroplating process for forming a subsequent conductive material layer, and a thin film with fewer pinholes and voids, thereby improving the formation quality of the subsequent conductive material layer.
In this embodiment, the seed layer 152 is formed by a chemical vapor deposition process. The covering capability of the chemical vapor deposition process is better, which is beneficial to improving the step covering capability of the seed layer 152 at the bottom and the side wall of the contact hole 200 and reducing the probability of generating defects such as holes in the seed layer 152.
As shown in fig. 8, a conductive material layer 153 filling the contact hole 200 is formed on the seed layer 152, and the conductive material layer 153, the seed layer 152, and the adhesive layer 151 constitute the conductive layer 150.
In this embodiment, the conductive material layer 153 is formed by an Electroplating (ECP) process. The electroplating process forms the conductive material layer 153 on the seed layer 152 in a Bottom-up (Bottom-up) growth manner, which is beneficial to reducing the probability of generating defects such as voids in the conductive material layer 153; moreover, the cost of the electroplating process is low, and in addition, by adopting the electroplating process, the efficiency of forming the conductive material layer 153 is improved, and accordingly, the process time is saved, and the production and manufacturing efficiency is improved.
In this embodiment, in the step of forming the conductive layer 150, the conductive layer 150 further covers the top of the interlayer dielectric layer 120.
It should be noted that, in this embodiment, taking the step of forming the conductive layer 150 including forming the seed layer 152 and the conductive material layer 153 after forming the adhesive layer 151 as an example, the forming of the adhesive layer 151 and the seed layer 152 and the forming of the metal layer 140 are performed on the same machine, the forming of the conductive material layer 153 is performed through an electroplating process, and the forming of the conductive material layer 153 is performed on another machine accordingly. Accordingly, the adhesive layer 151 can protect the metal layer 140 during the converting process of the machine.
In other embodiments, the step of forming the conductive layer may further include: after the adhesive layer is formed, a conductive material layer filling the contact hole is formed on the adhesive layer. In this embodiment, the conductive material layer is formed by a chemical vapor deposition process, and the steps of forming the conductive material layer and the bonding layer can be performed on the same machine, which is beneficial to simplifying the process complexity.
It should be further noted that, in the present embodiment, for convenience of illustration and description, only the adhesive layer 151, the seed layer 152, and the conductive material layer 153 are illustrated in fig. 7 and 8, and only the conductive layer 150 is illustrated in subsequent figures.
With reference to fig. 9 in combination, in this embodiment, the forming method further includes: a diffusion barrier layer 160 is formed on sidewalls of the contact hole 200.
The diffusion barrier layer 160 is used for blocking the diffusion of the material of the subsequent contact hole plug into the interlayer dielectric layer 120, and the diffusion barrier layer 160 is also used for improving the adhesion between the contact hole plug and the interlayer dielectric layer 120.
In this embodiment, the step of forming the diffusion barrier layer 160 includes: a second annealing process 250 is performed after the step of forming the conductive layer 150 to transform a portion of the thickness of the liner layer 130 and the conductive layer 150 into the diffusion barrier layer 160.
The pad layer 130 and the conductive layer 150 with partial thickness are converted into the diffusion barrier layer 160, so that a step of forming the diffusion barrier layer 160 on the sidewall of the contact hole 200 by using a deposition process is omitted, and the diffusion barrier layer 160 is formed by converting the pad layer 130 and the conductive layer 150 with partial thickness, which is beneficial to significantly improving the adhesion between the contact hole plug and the interlayer dielectric layer 120 by the diffusion barrier layer 160.
Specifically, in the step of performing the second annealing process 250, the material of the conductive layer 150 diffuses into the liner layer 130, thereby forming the diffusion barrier layer 160.
In this embodiment, the conductive layer 150 is made of cobalt, which has a high activity, and during the annealing process, the cobalt diffuses into the liner layer 130 to form the diffusion barrier layer 160.
Therefore, in this embodiment, the material of the diffusion barrier layer 160 includes CoSiN. Specifically, the CoSiN material is an amorphous material in which the crystal orientation is disordered and disordered, so that the probability of diffusion of the material of the subsequent contact hole plug along the crystal boundary is reduced, and the diffusion barrier layer 160 can be ensured to play a role in blocking the diffusion of the contact hole plug into the interlayer dielectric layer 120.
In this embodiment, after the conductive layer 150 is formed, the second annealing 250 is performed on the same machine, and a step of machine conversion is not required, so that the process integration degree is high.
The temperature of the second annealing treatment 250 is not preferably too low or too high. If the temperature of the second annealing treatment 250 is too low, it is easy to cause insufficient energy to be obtained by the material in the conductive layer 150 and thus diffusion into the pad layer 130 is difficult, or it is easy to cause insufficient bonding strength between the material of the conductive layer 150 and the pad layer 130 and thus formation of the diffusion barrier layer 160 is difficult; if the temperature of the second annealing treatment 250 is too high, the performance of the semiconductor structure is easily affected, and if the temperature is too high, it is difficult to perform the second annealing treatment 250 on the machine for forming the conductive layer 150, and a machine conversion step is required, which easily increases the process complexity. For this reason, in this embodiment, the process temperature of the second annealing treatment 250 is 400 ℃ to 450 ℃.
With reference to fig. 10, in this embodiment, after the performing the second annealing 250, the method further includes: and removing the conductive layer 150 higher than the interlayer dielectric layer 120 by using a planarization process.
By removing the conductive layer 150 above the ild layer 120, preparation is made for forming other dielectric layers (e.g., etch stop layers or ild layers) on the ild layer 120.
In this embodiment, a chemical mechanical polishing process is used to remove the conductive layer 150 above the interlayer dielectric layer 120.
Referring to fig. 11 in combination, after removing the conductive layer 150 above the interlayer dielectric layer 120, the forming method further includes: and forming an etching stop layer 170 covering the interlayer dielectric layer 120 and the conductive layer 150.
The subsequent process further comprises: forming a dielectric layer on the etch stop layer 170; forming a conductive via exposing the contact hole plug in the dielectric layer and the etch stop layer 170; a conductive plug is formed in the conductive via, and the etch stop layer 170 is used to define a stop position of an etching process in an etching process for forming the conductive via.
In this embodiment, the material of the etch stop layer 170 is silicon nitride. In other embodiments, the material of the etch stop layer may also be aluminum nitride or titanium nitride.
In this embodiment, the etching stop layer 170 is formed before the silicide layer is formed. In other embodiments, the etch stop layer may also be formed after the silicide layer is formed.
Referring to fig. 12, a first annealing process 300 is performed to convert the metal layer 140, the source/drain doped region 110 and the conductive layer 150 with a partial thickness into a silicide layer 180, and the remaining conductive layer 150 in the contact hole 200 is used as a contact hole plug 190.
The silicide layer 180 is used for reducing contact resistance between the contact hole plug 190 and the source-drain doped region 110, and the silicide layer 180 is also used for increasing adhesion between the contact hole plug 190 and the source-drain doped region 110, so that contact performance between the contact hole plug 190 and the source-drain doped region 110 is improved.
Compared with the silicide layer formed by only converting the metal layer and the source/drain doped region with a partial thickness, in this embodiment, the silicide layer 180 is further formed by converting a partial contact hole plug 190 material, and the resistivity of the contact hole plug 190 material is usually smaller than that of the metal layer 140 material, which is beneficial to further reducing the resistance of the silicide layer 180, and further improving the contact performance between the contact hole plug 190 and the source/drain doped region 110.
In this embodiment, the silicide layer 180 is formed by converting the metal layer 140, and the source-drain doped region 110 and the conductive layer 150 with a partial thickness, and therefore, the material of the silicide layer 180 includes one or more of CoSix, TiSix, and CoTiSix.
In this embodiment, the first annealing process 300 is performed by using a Dynamic Surface Annealing (DSA) process. The dynamic surface annealing process can anneal a specific region on the surface of the wafer, has small heated volume, needs shorter cooling time after the annealing is finished, is favorable for reducing the damage to other regions, and is favorable for saving the process time.
In this embodiment, after the conductive layer 150 filling the contact hole 200 is formed, the first annealing treatment 300 is performed, which is also beneficial to improving the uniformity of the first annealing treatment 300 and reducing the damage of the first annealing treatment 300 to the wafer surface.
The contact hole plug 190 is used to electrically connect the source/drain doped region 110 to other interconnect structures or external circuits.
In this embodiment, the material of the contact hole plug 190 is the same as the material of the conductive layer 150, and the material of the contact hole plug 190 is cobalt.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 12, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a source-drain doped region 110 located in the substrate 100; an interlayer dielectric layer 120 located on the substrate 100, wherein a contact hole 200 (shown in fig. 6) exposing the source/drain doped region 110 is formed in the interlayer dielectric layer 120; the silicide layer 180 is positioned on the source drain doped region 110 at the bottom of the contact hole 200; a contact hole plug 190 in the contact hole 200 and in direct contact with the silicide layer 180.
The contact hole plug 190 is in direct contact with the silicide layer 180, which is beneficial to reducing the contact resistance between the contact hole plug 190 and the source/drain doped region 110, further beneficial to improving the contact performance between the contact hole plug 190 and the source/drain doped region 110, and reducing the problems of rear-section RC delay and the like.
The substrate 100 provides a process platform for the formation of semiconductor structures.
In this embodiment, the substrate 100 is used to form a planar field effect transistor, and the substrate 100 only includes a substrate. In other embodiments, when the base is used for forming a finfet, the base comprises a substrate and a fin protruding from the substrate.
In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
In this embodiment, the semiconductor structure includes: a gate structure (not shown) on the substrate 100. The gate structure is used for controlling the on and off of the conductive channel when the field effect transistor works.
In this embodiment, the gate structure is a metal gate structure. The gate structure includes a high-k gate dielectric layer (not shown) and a gate electrode layer (not shown) over the high-k gate dielectric layer.
The high-k gate dielectric layer is made of a high-k dielectric material; wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO2. In other embodiments, the material of the high-k gate dielectric layer can be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
The gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the gate electrode layer is W.
In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure comprises a gate oxide layer and a gate layer positioned on the gate oxide layer.
The description of the gate structure is not repeated herein.
In this embodiment, the source-drain doped region 110 is located in the substrate 100 at two sides of the gate structure.
When an NMOS transistor is formed, the source-drain doped region 110 comprises a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, and therefore carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the source-drain doped region 110 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved, wherein the P-type ions are B ions, Ga ions or In ions.
The interlayer dielectric layer 120 is used for isolating adjacent devices, and the interlayer dielectric layer 120 is also used for isolating the contact hole plugs 190.
Therefore, the material of the interlayer dielectric layer 120 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 120 has a single-layer structure, and the material of the interlayer dielectric layer 120 is silicon oxide.
The contact hole 200 is used to provide a spatial location for the formation of the contact hole plug 190.
The silicide layer 180 is used for reducing contact resistance between the contact hole plug 190 and the source-drain doped region 110, and the silicide layer 180 is also used for increasing adhesion between the contact hole plug 190 and the source-drain doped region 110, so that contact performance between the contact hole plug 190 and the source-drain doped region 110 is improved.
In this embodiment, the material of the silicide layer 180 includes one or more of CoSix, TiSix, and CoTiSix. Compared with the scheme that the material of the silicide layer only includes TiSix, the material of the silicide layer 180 in this embodiment further includes Co, wherein the metal of Co is stronger than Ti, and the resistance of the silicide layer 180 including Co is lower, so that the resistance of the silicide layer 180 is further reduced, and the contact performance between the contact hole plug 190 and the source/drain doped region 110 is further improved.
The contact hole plug 190 is used to electrically connect the source/drain doped region 110 to other interconnect structures or external circuits.
In this embodiment, the contact plug 190 is made of cobalt.
In this embodiment, the semiconductor structure further includes: and a diffusion barrier layer 160 located between the interlayer dielectric layer 120 and the contact hole plug 190.
The diffusion barrier layer 160 is used for blocking the material of the contact hole plug 190 from diffusing into the interlayer dielectric layer 120, and the diffusion barrier layer 160 is also used for improving the adhesion between the contact hole plug 190 and the interlayer dielectric layer 120.
In this embodiment, the material of the diffusion barrier layer 160 includes CoSiN. Specifically, the CoSiN material is an amorphous material, and in the amorphous material, the crystal orientation is disordered and disordered, so that the probability of diffusion of the material of the contact hole plug 190 along the crystal boundary is reduced, and the diffusion barrier layer 160 can be ensured to play a role in blocking diffusion of the material of the contact hole plug 190 into the interlayer dielectric layer 120.
In this embodiment, the thickness of the diffusion barrier layer 160 is
Figure BDA0002167064930000151
To
Figure BDA0002167064930000152
The thickness of the diffusion barrier layer 160 is small, and the volume of the diffusion barrier layer 160 is correspondingly too small, so that the volume of the contact hole plug 190 formed in the contact hole 200 is large, and further, the reduction of the resistance of the contact hole plug 190 is facilitated, and the interconnection performance of the semiconductor structure is improved.
In this embodiment, the semiconductor structure further includes: and a liner layer 130 located between the interlayer dielectric layer 120 and the diffusion barrier layer 160.
The pad layer 130 is used to reduce the opening size of the contact hole 200, so as to meet the requirements of miniaturization and high integration of the device, and the pad layer 130 is also beneficial to reducing the difficulty of the process for forming the contact hole 200. In addition, the liner layer 130 provides for the subsequent formation of a diffusion barrier 160.
It should be noted that, in the present embodiment, the diffusion barrier layer 160 is formed by converting a partial thickness of the liner layer 130 and the contact hole plug 190.
The diffusion barrier layer 160 is formed by converting the liner layer 130 and the contact hole plug 190 with partial thicknesses, so that a diffusion barrier layer does not need to be additionally formed on the side wall of the contact hole 200, and the diffusion barrier layer 160 is formed by converting the liner layer 130 and the contact hole plug 190 with partial thicknesses, which is beneficial to making the improvement effect of the adhesion between the contact hole plug 190 and the interlayer dielectric layer 120 of the diffusion barrier layer 160 more remarkable.
In this embodiment, the liner layer 130 is made of silicon nitride. The silicon nitride material has a relatively high density, which is advantageous for improving the diffusion barrier layer 160 for blocking diffusion, and the silicon nitride material has a relatively low dielectric constant, which is advantageous for ensuring the isolation between the adjacent contact hole plugs 190.
In this embodiment, the semiconductor structure further includes: and an etch stop layer 170 covering the contact hole plug 190 and the top of the interlayer dielectric layer 120.
The subsequent process further comprises: forming a dielectric layer on the etch stop layer 170; forming a conductive via hole exposing the contact hole plug 190 in the dielectric layer and the etch stop layer 170; a conductive plug is formed in the conductive via, and the etch stop layer 170 is used to define a stop position of an etching process in an etching process for forming the conductive via.
In this embodiment, the material of the etch stop layer 170 is silicon nitride. In other embodiments, the material of the etch stop layer may also be aluminum nitride or titanium nitride.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, forming an active drain doping region in the substrate, forming an interlayer dielectric layer on the substrate, and forming a contact hole exposing the source drain doping region in the interlayer dielectric layer;
forming a metal layer on the source drain doped region exposed out of the contact hole;
forming a conductive layer filling the contact hole on the metal layer;
and carrying out first annealing treatment to convert the metal layer, the source drain doped region and the conducting layer with partial thickness into a silicide layer, and taking the residual conducting layer in the contact hole as a contact hole plug.
2. The method of forming a semiconductor structure of claim 1, wherein prior to the first annealing process, the method of forming further comprises: and forming a diffusion barrier layer on the side wall of the contact hole.
3. The method of forming a semiconductor structure of claim 2, wherein prior to forming the metal layer, the method of forming further comprises: forming a pad layer on a sidewall of the contact hole;
the step of forming the diffusion barrier layer comprises: and performing second annealing treatment after the step of forming the conducting layer to convert the liner layer and the conducting layer with partial thickness into the diffusion barrier layer.
4. The method of forming a semiconductor structure of claim 1, wherein the metal layer is formed using a selective chemical vapor deposition process.
5. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the metal layer, the metal layer has a thickness of
Figure FDA0002167064920000011
To
Figure FDA0002167064920000012
6. The method of forming a semiconductor structure of claim 3, wherein the second annealing process is at a temperature of 400 ℃ to 450 ℃.
7. The method of forming a semiconductor structure of claim 3, wherein a material of the diffusion barrier layer comprises CoSiN.
8. The method of forming a semiconductor structure of claim 3, wherein in the step of forming the liner layer, the liner layer has a thickness of
Figure FDA0002167064920000013
To
Figure FDA0002167064920000014
9. The method of forming a semiconductor structure of claim 1, wherein forming the conductive layer comprises: and forming an adhesive layer which conformally covers the side wall of the contact hole and the metal layer.
10. The method of forming a semiconductor structure of claim 9, wherein the step of forming the conductive layer further comprises: after the adhesive layer is formed, a conductive material layer filling the contact hole is formed on the adhesive layer, and the conductive material layer and the adhesive layer are used for forming the conductive layer.
11. The method of forming a semiconductor structure of claim 9, wherein the step of forming the conductive layer further comprises: after forming the bonding layer, forming a seed layer conformally covering the bonding layer; and forming a conductive material layer for filling the contact hole on the seed layer, wherein the conductive material layer, the seed layer and the bonding layer are used for forming the conductive layer.
12. The method of forming a semiconductor structure of claim 1, wherein said first annealing is performed using a dynamic surface annealing process.
13. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the silicide layer, the material of the silicide layer comprises CoSix、TiSixAnd CoTiSixOne or more of (a).
14. The method of forming a semiconductor structure of claim 3, wherein in the step of forming the conductive layer, the conductive layer further covers a top portion of the interlevel dielectric layer;
after the second annealing treatment is performed, the forming method further includes: and removing the conducting layer higher than the interlayer dielectric layer by adopting a planarization process.
15. A semiconductor structure, comprising:
a substrate;
the source-drain doped region is positioned in the substrate;
the interlayer dielectric layer is positioned on the substrate, and a contact hole exposing the source-drain doped region is formed in the interlayer dielectric layer;
the silicide layer is positioned on the source drain doped region at the bottom of the contact hole;
a contact hole plug in the contact hole and in direct contact with the silicide layer.
16. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: and the diffusion barrier layer is positioned between the interlayer dielectric layer and the contact hole plug.
17. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises: the liner layer is positioned between the interlayer dielectric layer and the diffusion barrier layer;
the diffusion barrier layer is formed by converting a partial thickness of the liner layer and the contact hole plug.
18. The semiconductor structure of claim 16, wherein the diffusion barrier layer has a thickness of
Figure FDA0002167064920000031
To
Figure FDA0002167064920000032
19. The semiconductor structure of claim 16, wherein the material of the diffusion barrier layer comprises CoSiN.
20. The semiconductor structure of claim 15, wherein the material of the silicide layer comprises one or more of CoSix, TiSix, and CoTiSix.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090246952A1 (en) * 2008-03-28 2009-10-01 Tokyo Electron Limited Method of forming a cobalt metal nitride barrier film
CN102222641A (en) * 2010-04-16 2011-10-19 台湾积体电路制造股份有限公司 Method for forming a metal oxidation barrier layer of a copper interconnect
CN106356331A (en) * 2015-07-14 2017-01-25 台湾积体电路制造股份有限公司 Cobalt interconnect techniques
US20180025989A1 (en) * 2016-07-22 2018-01-25 International Business Machines Corporation Formation of liner and metal conductor
US20180301382A1 (en) * 2017-06-14 2018-10-18 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090246952A1 (en) * 2008-03-28 2009-10-01 Tokyo Electron Limited Method of forming a cobalt metal nitride barrier film
CN102222641A (en) * 2010-04-16 2011-10-19 台湾积体电路制造股份有限公司 Method for forming a metal oxidation barrier layer of a copper interconnect
CN106356331A (en) * 2015-07-14 2017-01-25 台湾积体电路制造股份有限公司 Cobalt interconnect techniques
US20180025989A1 (en) * 2016-07-22 2018-01-25 International Business Machines Corporation Formation of liner and metal conductor
US20180301382A1 (en) * 2017-06-14 2018-10-18 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method thereof

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