TW201334073A - Structure of electrical contact and fabrication method thereof - Google Patents
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本發明係關於一種接觸結構，特別是關於一種電連接於半導體元件之接觸結構及其製作方法。The present invention relates to a contact structure, and more particularly to a contact structure electrically connected to a semiconductor element and a method of fabricating the same.
隨著積體電路(IC)的積集度越來越高，半導體元件的線寬與幾何尺寸也越來越小。受限於材料本質，積集度的增加使得半導體層與外部接觸金屬的接面電阻相對提升，因此，用以連接各式半導體元件與導線的插塞結構及其製程在次世代的半導體製程中也愈顯重要。As the integration of integrated circuits (ICs) becomes higher and higher, the line width and geometry of semiconductor components are becoming smaller and smaller. Limited by the nature of the material, the increase in the degree of integration increases the junction resistance of the semiconductor layer and the external contact metal. Therefore, the plug structure for connecting various semiconductor elements and wires and the process thereof are in the next generation semiconductor process. It is also becoming more and more important.
在習知的插塞結構製作過程中，為了降低接面電阻，一般是利用自行對準矽金屬化製程(self-aligned silicide,salicide)於半導體與金屬接面形成金屬矽化物。舉例而言，一般是先在半導體元件上覆蓋一金屬層，接著進行一高溫製程，使金屬層與半導體元件接觸之特定區域，例如與摻雜區或多晶矽等之矽區域反應，俾使金屬層內的金屬原子擴散進入半導體元件之該些特定區域，而於其表面形成一金屬矽化物層。繼以，去除未反應完全之金屬層，並再進行一相轉換製程，以降低金屬矽化物層之電阻。之後，於半導體元件上形成一絕緣層，並於絕緣層中蝕刻出複數個接觸洞以分別曝露該些金屬矽化物層，最後再於接觸洞中形成阻障層/導電層，便完成一接觸插塞結構。然而，上述之製程至少需經過兩次高溫製程(熱擴散製程及相轉換製程)以及一道金屬層移除步驟，如此繁雜之步驟無疑增加了製程成本，且兩次的高溫製程也會耗損半導體製程之熱預算(thermal budget)。In the fabrication process of the conventional plug structure, in order to reduce the junction resistance, a metal telluride is generally formed on the semiconductor and metal junction by self-aligned silicide (salicide). For example, a semiconductor layer is generally covered with a metal layer, and then a high temperature process is performed to make a specific region where the metal layer contacts the semiconductor element, for example, react with a doped region or a germanium region of a polysilicon or the like, thereby causing a metal layer. The metal atoms therein diffuse into the specific regions of the semiconductor element and form a metal halide layer on the surface thereof. Subsequently, the unreacted metal layer is removed, and a phase conversion process is performed to reduce the resistance of the metal telluride layer. Then, an insulating layer is formed on the semiconductor component, and a plurality of contact holes are etched in the insulating layer to respectively expose the metal germanide layer, and finally a barrier layer/conductive layer is formed in the contact hole to complete a contact. Plug structure. However, the above process requires at least two high-temperature processes (thermal diffusion process and phase conversion process) and a metal layer removal step. Such complicated steps undoubtedly increase the process cost, and the two high-temperature processes also consume the semiconductor process. Thermal budget.
因此，尚需要一種改良式的接觸結構及其製作方法以克服上述缺點，其可以簡化接觸結構之製程步驟，並且避免過度地消耗熱預算。Accordingly, there is a need for an improved contact structure and method of making the same that overcomes the above disadvantages, which simplifies the process steps of the contact structure and avoids excessive consumption of thermal budget.
為達到上述目的，本發明係提供一種接觸結構及其製作方法，俾以簡化接觸結構之製程步驟，並且避免過度地消耗熱預算。To achieve the above object, the present invention provides a contact structure and a method of fabricating the same, which simplifies the process steps of the contact structure and avoids excessive consumption of thermal budget.
根據本發明之一較佳實施例，係提供一種接觸結構之製作方法，包含有提供一基底，基底包含有至少一矽區域，於基底上形成一絕緣層，其中絕緣層包含至少一曝露該矽區域之接觸洞，且接觸洞包含至少一側壁及一底面，形成一金屬層於接觸洞之側壁及底面，再進行一高溫製程，於矽區域內形成一第一金屬矽化物層，最後形成一導電層覆蓋於金屬層上，且導電層填滿接觸洞，其中在形成該導電層時，該第一金屬矽化物層會轉換成一第二金屬矽化物層。According to a preferred embodiment of the present invention, a method of fabricating a contact structure includes providing a substrate including at least one germanium region, and forming an insulating layer on the substrate, wherein the insulating layer includes at least one exposed a contact hole of the region, wherein the contact hole comprises at least one sidewall and a bottom surface, forming a metal layer on the sidewall and the bottom surface of the contact hole, and performing a high temperature process to form a first metal telluride layer in the germanium region, and finally forming a The conductive layer covers the metal layer, and the conductive layer fills the contact hole, wherein the first metal telluride layer is converted into a second metal germanide layer when the conductive layer is formed.
根據本發明之另一較佳實施例，係提供一種接觸結構，包含有一基底，且基底包含有至少一矽區域、一絕緣層設置於基底上，其中絕緣層包含至少一曝露該矽區域之接觸洞，且接觸洞包含至少一側壁及一底面、一金屬層設置於接觸洞之側壁、一導電層設置於金屬層上，且導電層填滿接觸洞、一金屬矽化物層實質上接觸於接觸洞之底面，其中該金屬矽化物層與該金屬層具有相同金屬材質。According to another preferred embodiment of the present invention, a contact structure includes a substrate, and the substrate includes at least one germanium region, and an insulating layer is disposed on the substrate, wherein the insulating layer includes at least one contact exposing the germanium region a hole, wherein the contact hole comprises at least one sidewall and a bottom surface, a metal layer is disposed on the sidewall of the contact hole, a conductive layer is disposed on the metal layer, and the conductive layer fills the contact hole, and a metal telluride layer is substantially in contact with the contact The bottom surface of the hole, wherein the metal telluride layer and the metal layer have the same metal material.
根據上述，本發明係提供一種接觸結構及其製作方法，其省略去除金屬層之製程步驟，也不用額外進行相轉換熱處理之步驟。因此可以簡化接觸結構之製程步驟，並且避免過度地消耗熱預算。In accordance with the above, the present invention provides a contact structure and a method of fabricating the same that omits the process steps of removing the metal layer without the additional step of phase inversion heat treatment. This simplifies the process steps of the contact structure and avoids excessive consumption of the thermal budget.
請參照第1圖至第10圖，第1圖至第10圖為根據本發明較佳實施例所繪之接觸結構之製作方法示意圖。如第1圖所示，首先提供一半導體元件，例如具有金屬閘極之互補式電晶體元件，且金屬閘極係以一後閘極(gate-last)製程搭配前高介電常數介電層(high-K first)製程而得。此半導體元件之結構簡述如下：一基底100，例如一矽基底或一絕緣層上覆矽(silicon-on-insulator,SOI)基底等，其上定義有一第一區域與一第二區域，例如一NMOS區域102與一PMOS區域104，且基底100內形成有複數個用來電性絕緣電晶體區的淺溝隔離(shallow trench isolation,STI) 106。一第一閘極結構120與第二閘極結構122，分別位於NMOS區域102及PMOS區域104，且各閘極結構120、122之側壁各具有至少一側壁子，例如一第一側壁子124與一第二側壁子126。第一側壁子124與第二側壁子126之下方基底100中具有一輕摻雜汲極(lightly doped drain,LDD)128。至少一輕摻雜汲極128與至少一源極/汲極130設置於淺溝隔離(shallow trench isolation,STI) 106之間，且源極/汲極130未被第一側壁子124與第二側壁子126覆蓋。Referring to FIGS. 1 through 10, FIGS. 1 through 10 are schematic views showing a method of fabricating a contact structure according to a preferred embodiment of the present invention. As shown in FIG. 1, first, a semiconductor device such as a complementary transistor device having a metal gate is provided, and the metal gate is combined with a front high-k dielectric layer by a gate-last process. (high-K first) process. The structure of the semiconductor device is as follows: a substrate 100, such as a germanium substrate or a silicon-on-insulator (SOI) substrate, etc., having a first region and a second region defined thereon, for example An NMOS region 102 and a PMOS region 104 are formed, and a plurality of shallow trench isolation (STI) 106 for electrically insulating the transistor region are formed in the substrate 100. A first gate structure 120 and a second gate structure 122 are respectively located in the NMOS region 102 and the PMOS region 104, and each sidewall of each of the gate structures 120 and 122 has at least one sidewall, for example, a first sidewall 124 A second side wall 126. A lightly doped drain (LDD) 128 is defined in the substrate 100 below the first sidewall 124 and the second sidewall 126. At least one lightly doped drain 128 and at least one source/drain 130 are disposed between shallow trench isolation (STI) 106, and source/drain 130 is not separated by first sidewall 124 and second The side wall 126 is covered.
在此需注意的是，NMOS區域102與PMOS區域104內之源極/汲極130另可包含一磊晶層132，其可用以調整CMOS元件之載子遷移率，在本實施例中，僅於PMOS區域104中第二側壁子126兩側的基底100中設置磊晶層132，且磊晶層132較佳包含鍺化矽，並可透過單層或多層的方式形成。此外，由於本發明之金屬矽化物之位置係以接觸洞之開口位置定義，因此此時在源極/汲極130中較佳仍不會存在有金屬矽化物層(圖未示)。基底100表面可另具有一遮蓋層136，其可覆蓋第一閘極結構120與第二閘極結構122，且遮蓋層136也可以是具有適當應力的接觸洞蝕刻停止層(contact etch stop layer,CESL)。此外，一層間介電層138位於基底100表面上，覆蓋於NMOS區域102及PMOS區域104。It should be noted that the source/drain electrodes 130 in the NMOS region 102 and the PMOS region 104 may further include an epitaxial layer 132, which may be used to adjust the carrier mobility of the CMOS device. In this embodiment, only An epitaxial layer 132 is disposed in the substrate 100 on both sides of the second sidewall 126 in the PMOS region 104, and the epitaxial layer 132 preferably includes germanium oxide and may be formed by a single layer or a plurality of layers. In addition, since the position of the metal halide of the present invention is defined by the position of the opening of the contact hole, it is preferable that the metal halide layer is not present in the source/drain 130 at this time (not shown). The surface of the substrate 100 may further have a cover layer 136 covering the first gate structure 120 and the second gate structure 122, and the cover layer 136 may also be a contact etch stop layer with appropriate stress. CESL). In addition, an interlayer dielectric layer 138 is disposed on the surface of the substrate 100 to cover the NMOS region 102 and the PMOS region 104.
在本實施例中，第一閘極結構120係為一金屬閘極結構，其包含有一高介電常數介電層110、一功函數層150以及一閘極金屬層152。且根據本實施例，第二閘極結構122亦為一金屬閘極結構，其結構相似於第一閘極結構120，兩者唯一的差別在於功函數層150係為一N型功函數層，而功函數層144係為一P型功函數層。亦即，功函數層150之功函數數值需小於功函數層144之功函數數值。此外，雖然本實施例之高介電常數介電層110僅為單層之結構，然而其也可以是多層的結構。根據本發明之實施例，高介電常數介電層110可包含介電常數大致大於20之金屬氧化物層，其可以是稀土金屬氧化物層或鑭系金屬氧化物層，例如氧化鉿(hafnium oxide,HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、鋁酸鑭(lanthanum aluminum oxide,LaAlO)、氧化鉭(tantalum oxide,Ta2O5)、氧化鋯(zirconium oxide,ZrO2)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO)、氧化鐿(yttrium oxide,Yb2O3)、氧化矽鐿(yttrium silicon oxide,YbSiO)、鋁酸鋯(zirconium aluminate,ZrAlO)、鋁酸鉿(hafnium aluminate,HfAlO)、氮化鋁(aluminum nitride,AlN)、氧化鈦(titanium oxide,TiO2),氮氧化鋯(zirconium oxynitride,ZrON)、氮氧化鉿(hafnium oxynitride,HfON)、氮氧矽鋯(zirconium silicon oxynitride,ZrSiON)、氮氧矽鉿(hafnium silicon oxynitride,HfSiON)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)或鈦酸鋇驟200，以完成如第1圖或第2圖所示之半導體元件結構。接著進行步驟210，透過微影蝕刻製程在層間介電層138內形成多個接觸洞140，以定義出金屬矽化物形成之位置。接著進行一自對準矽金屬化製程，如步驟260、230、270、280所示，將金屬層160填入於接觸洞140內，使金屬層160覆蓋住半導體元件之特定區域，並進行一高溫製程，例如一快速熱退火(RTA)製程，俾使金屬層160內的金屬原子擴散進入其與半導體元件接觸之特定區域，而反應形成一金屬矽化物164。其中，另可於金屬層160形成一保護層(圖未示)，以避免金屬層160在高溫製程時氧化。繼以，去除未反應完全之金屬層160，並再進行一高溫製程，例如一快速熱退火(RTA)製程，以進行相轉換來降低金屬矽化物層之電阻。最後，於接觸洞140形成阻障層162/導電層180，便完成一接觸結構170。In the present embodiment, the first gate structure 120 is a metal gate structure including a high-k dielectric layer 110, a work function layer 150, and a gate metal layer 152. According to the embodiment, the second gate structure 122 is also a metal gate structure, and the structure is similar to the first gate structure 120. The only difference between the two is that the work function layer 150 is an N-type work function layer. The work function layer 144 is a P-type work function layer. That is, the work function value of the work function layer 150 needs to be smaller than the work function value of the work function layer 144. In addition, although the high-k dielectric layer 110 of the present embodiment is only a single-layer structure, it may also be a multi-layer structure. According to an embodiment of the invention, the high-k dielectric layer 110 may comprise a metal oxide layer having a dielectric constant substantially greater than 20, which may be a rare earth metal oxide layer or a lanthanide metal oxide layer, such as hafnium oxide (hafnium) Oxide, HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide Oxide, La 2 O 3 ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide , ZrSiO 4 ), hafnium zirconium oxide (HfZrO), yttrium oxide (Yb 2 O 3 ), yttrium silicon oxide (YbSiO), zirconium aluminate (ZrAlO), aluminum Hafnium aluminate (HfAlO), aluminum nitride (AlN), titanium oxide (TiO 2 ), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), nitrogen Zirconium silicon oxynitride (ZrSiON), nitrogen oxide Hafnium silicon oxynitride (HfSiON), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT) Or barium titanate step 200 to complete the semiconductor device structure as shown in Fig. 1 or Fig. 2. Next, in step 210, a plurality of contact holes 140 are formed in the interlayer dielectric layer 138 through a photolithography process to define a location where the metal halide is formed. Then, a self-aligned germanium metallization process is performed. As shown in steps 260, 230, 270, and 280, the metal layer 160 is filled in the contact hole 140, so that the metal layer 160 covers a specific region of the semiconductor device, and a A high temperature process, such as a rapid thermal annealing (RTA) process, causes metal atoms in the metal layer 160 to diffuse into specific regions of contact with the semiconductor components, and react to form a metal halide 164. Wherein, a protective layer (not shown) may be formed on the metal layer 160 to prevent the metal layer 160 from being oxidized during the high temperature process. Subsequently, the unreacted metal layer 160 is removed and a high temperature process, such as a rapid thermal annealing (RTA) process, is performed to perform phase inversion to reduce the resistance of the metal telluride layer. Finally, a barrier layer 162 / conductive layer 180 is formed in the contact hole 140 to complete a contact structure 170.
參照第4圖之第二較佳實施態樣，本發明另可進一步省略特定之步驟，進一步簡化接觸結構的製程。根據本實施態樣，其實質上類似於合併第一較佳實施態樣之步驟260及步驟290而成本實施態樣之步驟220，並同時合併第一較佳實施態樣之步驟280及步驟300而成本實施態樣之步驟240。此外，本發明也同時省略第一較佳實施態樣之步驟270。亦即，本發明之第二較佳實施態樣可以省略去除金屬層160之步驟，也不用額外進行相轉換(phase transition)熱處理及沈積阻障層162之步驟，因此更可以簡化接觸結構170之製程，鍶(barium strontium titanate,BaxSr1-xTiO3,BST)，但不以上述為限。於此需注意的是，根據其他較佳實施例，上述高介電常數介電層110之上、下方另可分別包含一蓋層112及介質層108，其成分包含氧化物、氮化物等之介電材料。而功函數層144、150及金屬層152間可分別包含一阻障層(圖未示)，以避免閘極金屬層152中之原子向外擴散。Referring to the second preferred embodiment of Fig. 4, the present invention further omits the specific steps to further simplify the process of the contact structure. According to this embodiment, it is substantially similar to step 220 of step 260 and step 290 of the first preferred embodiment, and step 220 of the first embodiment, and step 300 and step 300 of the first preferred embodiment. And step 240 of the cost implementation. Furthermore, the present invention also omits step 270 of the first preferred embodiment. That is, the second preferred embodiment of the present invention can omit the step of removing the metal layer 160, and does not additionally perform the phase transition heat treatment and the step of depositing the barrier layer 162, thereby simplifying the contact structure 170. Process, barium strontium titanate, Ba x Sr 1-x TiO 3 , BST, but not limited to the above. It should be noted that, according to other preferred embodiments, the cap layer 112 and the dielectric layer 108 may be respectively disposed on the upper and lower sides of the high-k dielectric layer 110, and the components thereof include oxides, nitrides, and the like. Dielectric material. A barrier layer (not shown) may be included between the work function layers 144, 150 and the metal layer 152 to prevent the atoms in the gate metal layer 152 from diffusing outward.
根據上述實施例，係提供一具有金屬閘極之CMOS元件，以其作為連接於本發明接觸結構之半導體元件。然而，根據其他實施例，本發明之半導體元件亦可以是具有傳統之多晶矽閘極或是利用前閘極製程製備而具有金屬閘極之CMOS，其結構如下文所述。第2圖是根據本發明之另一較佳實施例所繪示的一具有多晶矽閘極之互補式電晶體元件。第2圖之結構類似第1圖，然而在本實施例中，遮蓋層136係直接接觸閘極結構120、122，且閘極結構120、122內僅具有介質層108及多晶矽層116。其中，介質層108係為一氧化矽層，然而，介質層108亦可以是類似如上述實施例之高介電常數介電層。According to the above embodiment, a CMOS device having a metal gate is provided as a semiconductor element connected to the contact structure of the present invention. However, according to other embodiments, the semiconductor device of the present invention may also be a CMOS having a conventional polysilicon gate or a metal gate using a front gate process, the structure of which is as follows. 2 is a complementary transistor element having a polysilicon gate according to another preferred embodiment of the present invention. The structure of FIG. 2 is similar to that of FIG. 1. However, in the present embodiment, the mask layer 136 directly contacts the gate structures 120 and 122, and the gate structures 120 and 122 have only the dielectric layer 108 and the polysilicon layer 116. The dielectric layer 108 is a hafnium oxide layer. However, the dielectric layer 108 may also be a high-k dielectric layer similar to the above embodiment.
第3圖及第4圖分別是根據本發明不同實施態樣所繪製之形成接觸結構之方法流程圖，而第5圖至第10圖則為根據本發明較佳實施例所繪示之接觸結構之製作方法示意圖。如第3圖所示，在本發明之第一較佳實施態樣中，首先會進行步且避免過度地消耗熱預算。3 and 4 are flow charts respectively showing a method of forming a contact structure according to different embodiments of the present invention, and FIGS. 5 to 10 are contact structures according to a preferred embodiment of the present invention. Schematic diagram of the production method. As shown in Fig. 3, in the first preferred embodiment of the present invention, steps are first performed and excessive consumption of the thermal budget is avoided.
下文係就本發明第二較佳實施態樣之技術特徵加以描述，詳細流程敘述如下。如第5圖所示，首先，於層間介電層138內形成至少一接觸洞140，以暴露出相對應之矽區域。需注意的是，在本實施例中所指的矽區域係指源極/汲極130，然而根據其他實施例，矽區域可泛指任何由接觸洞140所暴露出之半導體區域，半導體區域可以是單晶矽或多晶矽之摻雜區或非摻雜區，且摻質包含磷、砷、硼、鍺及其組合，但不限於此。接著，進行一金屬層160沈積製程，較佳為一無線電波頻率物理氣相沈積(radio frequency physical vapor deposition,RFPVD)，以於接觸洞140之側壁140a及底面140b形成一金屬層160。且藉由後續之高溫製程，例如一溫度小於350℃之快速熱退火(RTA)製程，可使金屬層160內之金屬進入矽區域中，使得局部矽區域之導電率得以提升。根據本實施例，金屬層160之表面可另覆蓋有一阻障層162，例如金屬氮化物，其可用以避免後續半導體元件中之導電層180產生電遷移(electromigration)之現象。然而，阻障層162也可以作為一黏著層(圖未示)或保護層(圖未示)，以增進導電層180和金屬層160間的附著力或防止金屬層160在高溫過程中氧化。根據其他實施例，也可透過其他製程另外形成黏著層或保護層。在此需強調的是，由於此時金屬層160之上方覆蓋有一阻障層162，因此在後續的製程中便不需額外沈積阻障層162於金屬層160上。此外，上述金屬層160係可選自鎢(W)、鋁(Al)、銅(Cu)、鈦(Ti)、鉭(Ta)、鈮(Nb)、铒(Er)、鉬(Mo)、鈷(Co)、鎳(Ni)、鉑(Pt)和其合金所組成之群組，且該阻障層162包含氮化鈦(TiN)、氮化鉭(TaN)、鈦/氮化鈦(Ti/TiN)或鉭/氮化鉭(Ta/TaN)，但不限於此。The following is a description of the technical features of the second preferred embodiment of the present invention, and the detailed flow is as follows. As shown in FIG. 5, first, at least one contact hole 140 is formed in the interlayer dielectric layer 138 to expose the corresponding germanium region. It should be noted that the germanium region referred to in this embodiment refers to the source/drain 130, however, according to other embodiments, the germanium region may generally refer to any semiconductor region exposed by the contact hole 140, and the semiconductor region may It is a doped region or a non-doped region of single crystal germanium or polycrystalline germanium, and the dopant includes phosphorus, arsenic, boron, germanium, and combinations thereof, but is not limited thereto. Next, a metal layer 160 deposition process, preferably a radio frequency physical vapor deposition (RFPVD), is performed to form a metal layer 160 on the sidewall 140a and the bottom surface 140b of the contact hole 140. And by a subsequent high temperature process, such as a rapid thermal annealing (RTA) process with a temperature less than 350 ° C, the metal in the metal layer 160 can enter the germanium region, so that the conductivity of the local germanium region is improved. According to this embodiment, the surface of the metal layer 160 may be additionally covered with a barrier layer 162, such as a metal nitride, which may be used to avoid electromigration of the conductive layer 180 in subsequent semiconductor elements. However, the barrier layer 162 can also serve as an adhesive layer (not shown) or a protective layer (not shown) to enhance adhesion between the conductive layer 180 and the metal layer 160 or to prevent oxidation of the metal layer 160 during high temperature. According to other embodiments, an adhesive layer or a protective layer may be additionally formed through other processes. It should be emphasized here that since the barrier layer 162 is overlaid on the metal layer 160 at this time, it is not necessary to additionally deposit the barrier layer 162 on the metal layer 160 in the subsequent process. Further, the metal layer 160 may be selected from the group consisting of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), niobium (Nb), europium (Er), molybdenum (Mo), a group consisting of cobalt (Co), nickel (Ni), platinum (Pt) and alloys thereof, and the barrier layer 162 comprises titanium nitride (TiN), tantalum nitride (TaN), titanium/titanium nitride ( Ti/TiN) or tantalum/tantalum nitride (Ta/TaN), but is not limited thereto.
請參照第6圖，在下述製程中，將於矽區域內形成一金屬矽化物，其製程步驟詳述如下：首先，進行一高溫製程，例如溫度小於350℃之熱擴散製程，但不限於此，使金屬層160內之金屬進入源極/汲極130區域內，或是使源極/汲極130區域內之矽原子進入金屬層160，因而於接觸洞140之底部140b形成一第一金屬矽化物164。此時，第一金屬矽化物164之電阻值仍未達最佳值。此外，本發明亦可調整金屬層160的沉積厚度與高溫製程的時間、溫度等參數，來改變接觸洞140底部140b之金屬層160最終的厚度，而使本發明更具有製程彈性來符合各式產品的需求。請參照第7圖及第8圖，其分別為第6圖中圓圈處之局部放大示意圖。如第7圖所示，在此實施例中，經過高溫製程處理之後，接觸洞140底面140b之金屬層160厚度W會因為金屬與矽反應而變薄，使得金屬層160之厚度W小於側壁140a金屬層160之厚度W’。然而，如第8圖所示，在適當的製程參數下，接觸洞140底面140b之金屬層160也可能在經過高溫製程後而完全消失，因此，若金屬層160在進行高溫製程前已覆蓋有一阻障層162，則底部140b之阻障層162會實質上接觸於第一金屬矽化物164。此外，第一金屬矽化物層164所存在之區域大致會對應於接觸洞140所暴露出之區域，亦即，第一金屬矽化物層164係位於矽區域之表面且鄰近於接觸洞140之底部140b。在此需注意的是，根據上述之各實施態樣，由於在高溫製程之後皆不會去除剩餘之金屬層160，因此接觸洞140之側壁140a必定會殘留有用來進行自行對準矽金屬化製程(self-aligned silicide,salicide)的金屬層160。Referring to FIG. 6, in the following process, a metal halide is formed in the germanium region, and the process steps are as follows: First, a high temperature process, such as a thermal diffusion process with a temperature less than 350 ° C, is performed, but is not limited thereto. The metal in the metal layer 160 enters the source/drain 130 region, or the germanium atoms in the source/drain 130 region enter the metal layer 160, thereby forming a first metal at the bottom 140b of the contact hole 140. Telluride 164. At this time, the resistance value of the first metal telluride 164 is still not at an optimum value. In addition, the present invention can also adjust the deposition thickness of the metal layer 160 and the time and temperature of the high temperature process to change the final thickness of the metal layer 160 of the bottom portion 140b of the contact hole 140, so that the present invention has more process flexibility to conform to various types. Product demand. Please refer to FIG. 7 and FIG. 8 , which are respectively partial enlarged views of the circle in FIG. 6 . As shown in FIG. 7, in this embodiment, after the high-temperature process, the thickness W of the metal layer 160 of the bottom surface 140b of the contact hole 140 is thinned by the reaction of the metal with the germanium, so that the thickness W of the metal layer 160 is smaller than the sidewall 140a. The thickness of the metal layer 160 is W'. However, as shown in FIG. 8, under appropriate process parameters, the metal layer 160 of the bottom surface 140b of the contact hole 140 may completely disappear after being subjected to a high temperature process. Therefore, if the metal layer 160 is covered before the high temperature process is performed, The barrier layer 162, the barrier layer 162 of the bottom portion 140b is substantially in contact with the first metal germanide 164. In addition, the region in which the first metal telluride layer 164 is present substantially corresponds to the region exposed by the contact hole 140, that is, the first metal telluride layer 164 is located on the surface of the germanium region and adjacent to the bottom of the contact hole 140. 140b. It should be noted that, according to the above embodiments, since the remaining metal layer 160 is not removed after the high temperature process, the sidewall 140a of the contact hole 140 must have a residual self-alignment metallization process. (self-aligned silicide, salicide) metal layer 160.
接著如第9圖所示，進行一沈積製程以及平坦化製程，以在各接觸洞140內填滿導電層180，其詳細製程步驟描述如下：首先，進行一沈積製程，例如鎢金屬沈積，使得一導電層180覆蓋於層間介電層138之上。根據本發明之第二實施態樣，由於上述沈積製程之溫度約等於400℃，因此在進行沈積製程的同時，第一金屬矽化物164可相轉換成導電率較高之第二金屬矽化物168，舉例而言，由Ni2Si相轉換成NiSi。比較於第一實施態樣之矽金屬化製程，本實施態樣在沈積導電層180之前不需透過另外的相轉換高溫製程，而是將其整合於導電層180沈積製程中，因此可以節省製程步驟。最後，進行一平坦化製程，例如化學機械研磨製程，平坦化導電層180並同時移除層間介電層138上的金屬層160及阻障層162。此外根據不同實施例，本發明之導電層180不限於鎢，其另可包含鋁(Al)、鈦(Ti)、鉭(Ta)、鈮(Nb)、鉬(Mo)、銅(Cu)等金屬或其合金，且沈積製程之溫度也可大於400℃。Next, as shown in FIG. 9, a deposition process and a planarization process are performed to fill the contact holes 140 with the conductive layer 180. The detailed process steps are as follows: First, a deposition process, such as tungsten metal deposition, is performed. A conductive layer 180 overlies the interlayer dielectric layer 138. According to the second embodiment of the present invention, since the temperature of the deposition process is approximately equal to 400 ° C, the first metal telluride 164 can be phase-converted into a second metal telluride 168 having a higher conductivity while the deposition process is being performed. For example, it is converted from Ni 2 Si phase to NiSi. Compared with the first metallization process of the first embodiment, the present embodiment does not need to pass through another phase-conversion high-temperature process before depositing the conductive layer 180, but integrates it into the conductive layer 180 deposition process, thereby saving process. step. Finally, a planarization process, such as a chemical mechanical polishing process, is performed to planarize the conductive layer 180 while simultaneously removing the metal layer 160 and the barrier layer 162 on the interlayer dielectric layer 138. In addition, according to various embodiments, the conductive layer 180 of the present invention is not limited to tungsten, and may further include aluminum (Al), titanium (Ti), tantalum (Ta), niobium (Nb), molybdenum (Mo), copper (Cu), and the like. The metal or its alloy, and the temperature of the deposition process can also be greater than 400 ° C.
如第10圖所示，第10圖所繪示的是第9圖中接觸結構170之設計佈局俯視圖。本發明之各實施態樣之接觸結構170之設計佈局可以是柱狀或長條狀。在本實施例中，NMOS區域102之接觸結構170皆為條狀接觸洞(slot contact hole)，而PMOS區域104之接觸結構170皆為接觸插塞洞(contact plug hole)。然而，上述之接觸結構佈局僅為例示，根據不同之製程需求，NMOS區域102及PMOS區域104之接觸結構170之佈局可隨意組合。舉例而言，位於NMOS區域102左側及右側之接觸結構170可分別為條狀接觸洞及/或接觸插塞洞。As shown in FIG. 10, FIG. 10 is a plan view showing the layout of the contact structure 170 in FIG. The design layout of the contact structure 170 of each embodiment of the present invention may be columnar or elongated. In this embodiment, the contact structures 170 of the NMOS regions 102 are all slot contact holes, and the contact structures 170 of the PMOS regions 104 are contact plug holes. However, the above-described contact structure layout is merely an example, and the layout of the contact structures 170 of the NMOS region 102 and the PMOS region 104 can be arbitrarily combined according to different process requirements. For example, the contact structures 170 on the left and right sides of the NMOS region 102 may be strip contact holes and/or contact plug holes, respectively.
根據上述之各實施態樣，係提供一CMOS元件，其採用後閘極(gate-last)製程搭配前高介電常數介電層(high-K first)製程，因此閘極結構120、122中具有U字形之功函數層150、144位於一字形之高介電常數介電層110上方。然而，根據本發明之其他實施例，CMOS元件也可以經由後閘極(gate last)製程搭配後高介電常數介電層(high-k last)製程而得到U字形之高介電常數介電層。此外，為了簡潔起見，上文之實施態樣僅以CMOS元件作為本發明之半導體元件。然而，本發明之接觸結構170不僅只適用於CMOS元件，其可均等地被替代為其他之半導體元件。舉例而言，本發明之接觸結構170亦可以應用在電連接於NMOS、PMOS、電阻器(resistor)、二極體元件、感光元件(photosensitive device)或雙極性電晶體(Bipolar Junction Transistor,BJT)等半導體元件的接觸插塞製程中。According to the above embodiments, a CMOS device is provided which adopts a gate-last process and a high-k first process, so that the gate structures 120 and 122 are The U-shaped work function layers 150, 144 are located above the in-line high-k dielectric layer 110. However, according to other embodiments of the present invention, the CMOS device can also be U-shaped with a high dielectric constant dielectric via a gate-last process followed by a high-k last process. Floor. Further, for the sake of brevity, the above embodiment has only a CMOS element as the semiconductor element of the present invention. However, the contact structure 170 of the present invention is not only applicable to CMOS components, but can be equally replaced with other semiconductor components. For example, the contact structure 170 of the present invention can also be applied to be electrically connected to an NMOS, a PMOS, a resistor, a diode element, a photosensitive device, or a Bipolar Junction Transistor (BJT). In the contact plug process of semiconductor components.
綜上所述，本發明係提供一種接觸結構170及其製作方法，其可省略去除金屬層160之製程步驟，也不用額外進行相轉換熱處理及沈積阻障層162之步驟。因此可以簡化接觸結構170之製程步驟，並且避免過度地消耗熱預算。In summary, the present invention provides a contact structure 170 and a method of fabricating the same, which can omit the process steps of removing the metal layer 160 without additionally performing the phase change heat treatment and the step of depositing the barrier layer 162. It is thus possible to simplify the process steps of the contact structure 170 and to avoid excessive consumption of the thermal budget.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100．．．基底100. . . Base
102．．．NMOS區域102. . . NMOS region
104．．．PMOS區域104. . . PMOS area
106．．．淺溝隔離106. . . Shallow trench isolation
108．．．介質層108. . . Dielectric layer
110．．．高介電常數介電層110. . . High dielectric constant dielectric layer
112．．．蓋層112. . . Cover
116．．．多晶矽層116. . . Polycrystalline layer
120．．．第一閘極結構120. . . First gate structure
122．．．第二閘極結構122. . . Second gate structure
124．．．第一側壁子124. . . First side wall
126．．．第二側壁子126. . . Second side wall
128．．．輕摻雜汲極128. . . Lightly doped bungee
130．．．源極/汲極130. . . Source/bungee
132．．．磊晶層132. . . Epitaxial layer
136．．．遮蓋層136. . . Cover layer
138．．．層間介電層138. . . Interlayer dielectric layer
140．．．接觸洞140. . . Contact hole
140a．．．側壁140a. . . Side wall
140b．．．底面140b. . . Bottom
144．．．功函數層144. . . Work function layer
150．．．功函數層150. . . Work function layer
152．．．閘極金屬層152. . . Gate metal layer
160．．．金屬層160. . . Metal layer
162．．．阻障層162. . . Barrier layer
164．．．第一金屬矽化物164. . . First metal telluride
168．．．第二金屬矽化物168. . . Second metal telluride
170．．．接觸結構170. . . Contact structure
180．．．導電層180. . . Conductive layer
W．．．厚度W. . . thickness
W’．．．厚度W’. . . thickness
第1圖至第10圖為根據本發明較佳實施例所繪示之接觸結構之製作方法示意圖，其中：1 to 10 are schematic views showing a method of fabricating a contact structure according to a preferred embodiment of the present invention, wherein:
第1圖是根據本發明之一實施例所繪示的一具有金屬閘極之互補式電晶體元件；1 is a complementary transistor element having a metal gate according to an embodiment of the invention;
第2圖是根據本發明之一實施例所繪示的一具有多晶矽閘極之互補式電晶體元件；2 is a complementary transistor element having a polysilicon gate according to an embodiment of the invention;
第3圖為根據本發明之第一較佳實施態樣所繪製之接觸結構之製作方法流程圖；3 is a flow chart showing a method of fabricating a contact structure according to a first preferred embodiment of the present invention;
第4圖是根據本發明之第二較佳實施態樣所繪製之製作接觸結構之方法流程圖；以及4 is a flow chart showing a method of fabricating a contact structure according to a second preferred embodiment of the present invention;
第5圖至第10圖為根據本發明較佳實施例所繪示之接觸結構之製作方法示意圖。5 to 10 are schematic views showing a method of fabricating a contact structure according to a preferred embodiment of the present invention.
100．．．基底100. . . Base
102．．．NMOS區域102. . . NMOS region
104．．．PMOS區域104. . . PMOS area
106．．．淺溝隔離106. . . Shallow trench isolation
108．．．介質層108. . . Dielectric layer
110．．．高介電常數介電層110. . . High dielectric constant dielectric layer
112．．．蓋層112. . . Cover
120．．．第一閘極結構120. . . First gate structure
122．．．第二閘極結構122. . . Second gate structure
124．．．第一側壁子124. . . First side wall
126．．．第二側壁子126. . . Second side wall
128．．．輕摻雜汲極128. . . Lightly doped bungee
130．．．源極/汲極130. . . Source/bungee
132．．．磊晶層132. . . Epitaxial layer
136．．．遮蓋層136. . . Cover layer
138．．．層間介電層138. . . Interlayer dielectric layer
144．．．功函數層144. . . Work function layer
150．．．功函數層150. . . Work function layer
152．．．閘極金屬層152. . . Gate metal layer
160．．．金屬層160. . . Metal layer
162．．．阻障層162. . . Barrier layer
168．．．第二金屬矽化物168. . . Second metal telluride
170．．．接觸結構170. . . Contact structure
180．．．導電層180. . . Conductive layer
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| TW101103231A TWI518783B (en) | 2012-02-01 | 2012-02-01 | Structure of electrical contact and fabrication method thereof |
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| Country | Link |
|---|---|
| TW (1) | TWI518783B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI761466B (en) * | 2017-11-29 | 2022-04-21 | 國立大學法人東北大學 | Semiconductor devices including cobalt alloys and fabrication methods thereof |
| TWI833184B (en) * | 2021-07-08 | 2024-02-21 | 台灣積體電路製造股份有限公司 | Semiconductor devices and methods of manufacturing thereof |
-
2012
- 2012-02-01 TW TW101103231A patent/TWI518783B/en active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI761466B (en) * | 2017-11-29 | 2022-04-21 | 國立大學法人東北大學 | Semiconductor devices including cobalt alloys and fabrication methods thereof |
| US11380619B2 (en) | 2017-11-29 | 2022-07-05 | Tohoku University | Semiconductor devices including cobalt alloys and fabrication methods thereof |
| TWI833184B (en) * | 2021-07-08 | 2024-02-21 | 台灣積體電路製造股份有限公司 | Semiconductor devices and methods of manufacturing thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI518783B (en) | 2016-01-21 |
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