CN112396981A

CN112396981A - Display panel

Info

Publication number: CN112396981A
Application number: CN202011411098.1A
Authority: CN
Inventors: 黄景亮; 洪嘉泽; 郭庭玮; 郑君丞
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-01-14
Filing date: 2020-12-04
Publication date: 2021-02-23
Anticipated expiration: 2040-12-04
Also published as: CN112396981B

Abstract

A display panel, comprising: the display device comprises a first substrate, a second substrate, a plurality of pixel circuits and a plurality of through holes. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a third surface and a fourth surface opposite to the third surface. The pixel circuits respectively have a first part and a second part, wherein the first parts of the pixel circuits are arrayed on the first surface, and the second parts of the pixel circuits are arrayed on the third surface. The through holes are formed on the first substrate and the second substrate to electrically connect the first part and the second part of each pixel circuit.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel with high pixel density.

Background

With the gradual popularization of color screens of mobile phones, the material of the screens of the mobile phones is more and more important. The color screens of mobile phones are different due to different screen materials and development technologies, and the types of the color screens include Thin Film Transistor (TFT), Thin Film Diode (TFD), UFB, Super Twisted Nematic (STN), Organic Light Emitting Diode (OLED), and the like. Generally, in addition to the color gamut of the display panel, the higher the resolution of the display panel, the more complex images can be displayed, and the more rich the gradation of the screen can be. However, due to the number of transistors in the pixel circuit, the resolution of the display panel is increasingly difficult to improve, and a new display panel structure is required.

Disclosure of Invention

The invention provides a display panel, which can increase the resolution ratio or space utilization rate of the display panel and achieve the purpose of narrow frame.

The display panel of the present invention includes: the display device comprises a first substrate, a second substrate, a plurality of pixel circuits and a plurality of through holes. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a third surface and a fourth surface opposite to the third surface. The pixel circuits respectively have a first part and a second part, wherein the first parts of the pixel circuits are arrayed on the first surface, and the second parts of the pixel circuits are arrayed on the third surface. The through holes are formed on the first substrate and the second substrate to electrically connect the first part and the second part of each pixel circuit.

In view of the above, the display panel according to the embodiment of the invention increases the circuit layout space of the display panel by using the first substrate and the second substrate stacked in the vertical direction, so as to increase the resolution or the space utilization rate of the display panel, and achieve the purpose of narrow frame.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.

Fig. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the invention.

Fig. 4 is a schematic diagram of a pixel circuit according to an embodiment of the invention.

Fig. 5 is a schematic diagram of a pixel circuit according to another embodiment of the invention.

FIG. 6 is a schematic diagram of a pixel circuit according to another embodiment of the present invention.

Fig. 7 is a schematic layout diagram of power lines and signal lines of a display panel according to an embodiment of the invention.

Description of reference numerals:

100: display panel

110: first substrate

111: first surface

113: second surface

120: adhesive layer

130: second substrate

131: third surface

133: the fourth surface

140: gate drive circuit

APX: pixel array region

C1, C2, C3: capacitor with a capacitor element

d 1: first direction of extension

d 2: second direction of extension

DATA: data voltage

And (3) ECS: control switch element

EDR (electric double layer reactor): driving element

EIL, LDX 1-LDX 3: light emitting element

EM: luminous signal

LDX: data signal line

LEM: light emitting signal line

Lf 1: a first active device layer

Lf 2: a second active device layer

Lpw 1: first power line

Lpw 2: second power line

LSC: scanning signal line

LSE: detection signal line

Ltg: detection switch signal line

PIX, PIXa to PIXc: pixel circuit

PT 1: the first part

PT 2: the second part

S1: first scanning signal

S2: second scanning signal

And (2) SCAN: scanning signal

SENSE: detecting the signal

Stg: detecting a switching signal

T11-T13, T21-T23, T31-T37: transistor with a metal gate electrode

VA11, VA12, VA21, VA22, VA 31-VA 33: inner bore

VAX: perforation

VDD: high voltage of system

VREF: reference voltage

VSS: low voltage of system

Detailed Description

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "portion" discussed below could be termed a second element, component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the invention. Referring to fig. 1, in the present embodiment, a display panel 100 at least includes a first substrate 110, an adhesive layer 120, a second substrate 130, a plurality of pixel circuits PIX, a plurality of first power lines Lpw1, a plurality of second power lines Lpw2, a plurality of scan signal lines LSC, a plurality of data signal lines LDX, and a plurality of through holes VAX. The first power lines Lpw1 may be respectively substantially perpendicular to the second power lines Lpw2, and the first power lines Lpw1 may be respectively substantially perpendicular to the second power lines Lpw 2.

The first substrate 110 has a first surface 111 and a second surface 113 opposite to the first surface 111, and the second substrate 130 has a third surface 131 and a fourth surface 133 opposite to the third surface 131. The pixel circuits PIX are disposed in the pixel array area APX and each have a first portion PT1 and a second portion PT 2. The first portions PT1 of the pixel circuits PIX are arranged in an array on the first surface 111, and the second portions PT2 of the pixel circuits PIX are arranged in an array on the third surface 131.

The first portion PT1 of each pixel circuit PIX includes at least one light emitting element EIL and at least one driving element EDR, and the second portion PT1 of each pixel circuit PIX includes at least one control switching element ECS. The light emitting element EIL includes, for example, one of a light emitting diode and an organic light emitting diode.

The first power lines Lpw1 and the second power lines Lpw2 are disposed on the first surface 111 to respectively connect to the first portions PT1 of the corresponding pixel circuits PIX. The scan signal lines LSC and the data signal lines LDX are disposed on the third surface 131 to be respectively connected to the second portions PT2 of the corresponding pixel circuits PIX.

The adhesive layer 120 is disposed between the first substrate 110 and the second substrate 130 for adhering the first substrate 110 and the second substrate 130. The through holes VAX are formed on the first substrate 110, the adhesive layer 120, and the second substrate 130 to electrically connect the first portion PT1 and the second portion PT2 of each pixel circuit PIX. Therefore, by using the circuit layout space overlapped in the vertical direction, the resolution or the space utilization of the display panel 100 can be increased, and the purpose of a narrow bezel can be achieved. In other words, a pixel compensation circuit accommodating a larger number of thin film transistors can be formed to achieve a high value of display effect per inch of pixels. In addition, the power lines (such as the first power line Lpw1 and the second power line Lpw2) can have better resistance and heat dissipation effects, and the design of four narrow sides is provided.

In the embodiment of the invention, the material of the semiconductor layer of the first substrate 110 may be the same as the material of the semiconductor layer of the second substrate 130. In the embodiment of the present invention, the material of the semiconductor layer of the first substrate 110 may also be different from the material of the semiconductor layer of the second substrate 130. For example, the semiconductor layer of the first substrate 110 may be made of low temperature polysilicon to have better driving capability (e.g., higher driving current), and the semiconductor layer of the second substrate 130 is made of metal oxide semiconductor to have lower leakage current, so as to avoid the influence of excessive leakage current on the display of the image when data is not written.

Fig. 2 is a schematic cross-sectional view of a display panel according to an embodiment of the invention. Referring to fig. 1 and fig. 2, in the present embodiment, a first active device layer Lf1 is formed on the first surface 111 of the first substrate 110 to form a first portion PT1 of the pixel circuit PIX. A second active device layer Lf2 is formed on the third surface 131 of the second substrate 130 to form a second portion PT2 of the pixel circuit PIX. The adhesive layer 120 is used to adhere the second surface 113 of the first substrate 110, the third surface 131 of the second substrate 130 and the second active device layer Lf2, that is, the third surface 131 is opposite to the second surface 113 based on the adhesive layer 120. Also, a gate driving circuit 140 may be formed on the fourth surface 133.

Fig. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the invention. Referring to fig. 1 and fig. 3, similar to the embodiment shown in fig. 2, a first active device layer Lf1 is formed on the first surface 111 of the first substrate 110, and a second active device layer Lf2 is formed on the third surface 131 of the second substrate 130. However, the adhesive layer 120 is used to adhere the second surface 113 of the first substrate 110 and the fourth surface 133 of the second substrate 130, i.e. the fourth surface 133 is opposite to the second surface 113 based on the adhesive layer 120.

Fig. 4 is a schematic diagram of a pixel circuit according to an embodiment of the invention. Referring to fig. 1 and 4, in the present embodiment, the second portion PT2 of the pixel circuit PIXa includes a transistor T11, and the first portion PT1 includes transistors T12, T13, a capacitor C1 and a light emitting device LDX 1. The first terminal of the transistor T11 is electrically connected to the DATA signal line LDX for receiving the DATA voltage DATA, and the control terminal of the transistor T11 is electrically connected to the SCAN signal line LSC for receiving the SCAN signal SCAN.

The first terminal of the transistor T12 is electrically connected to the first power line Lpw1 for receiving the system high voltage VDD, and the control terminal of the transistor T12 is electrically connected to the second terminal of the transistor T11 through the inner via VA 11. The capacitor C1 is electrically connected between the first terminal of the transistor T12 and the control terminal of the transistor T12. The first terminal of the transistor T13 is electrically connected to the second terminal of the transistor T12, and the control terminal of the transistor T12 is electrically connected to the light emitting signal line LEM through the inner via VA12 for receiving the light emitting signal EM. The anode terminal of the light emitting device LDX1 is electrically connected to the second terminal of the transistor T13, and the cathode terminal of the light emitting device LDX1 is electrically connected to the second power line Lpw2 for receiving the system low voltage VSS.

In the embodiment of the present invention, the inner vias VA11 and VA12 are disposed in the pixel circuits PIXa, that is, the inner vias VA11 and VA12 are disposed in the pixel array area APX where the pixel circuits PIXa are disposed. The light emitting signal line LEM may be disposed outside the pixel array area APX, and the signal through holes electrically connected to the scan signal line LSC, the data signal line LDX, and the light emitting signal line LEM may be disposed in the pixel array area APX where the pixel circuits PIXa are disposed or outside the pixel array area APX, which may be determined according to a circuit design.

Fig. 5 is a schematic diagram of a pixel circuit according to another embodiment of the invention. Referring to fig. 1 and 5, in the present embodiment, the second portion PT2 of the pixel circuit PIXb includes a transistor T21, and the first portion PT1 includes transistors T22, T23, a capacitor C2 and a light emitting element LDX 2. The first terminal of the transistor T21 is electrically connected to the DATA signal line LDX for receiving the DATA voltage DATA, and the control terminal of the transistor T21 is electrically connected to the SCAN signal line LSC for receiving the SCAN signal SCAN.

The first terminal of the transistor T22 is electrically connected to the first power line Lpw1 for receiving the system high voltage VDD, and the control terminal of the transistor T22 is electrically connected to the second terminal of the transistor T21 through the inner via VA 21. The capacitor C2 is electrically connected between the first terminal of the transistor T22 and the control terminal of the transistor T22. The first terminal of the transistor T23 is electrically connected to the second terminal of the transistor T12, the control terminal of the transistor T22 is electrically connected to the detection switch signal line Ltg through the internal via VA22 to receive the detection switch signal Stg, and the second terminal of the transistor T23 is electrically connected to the detection signal line LSE to provide the detection signal SENSE. The anode terminal of the light emitting device LDX1 is electrically connected to the second terminal of the transistor T22, and the cathode terminal of the light emitting device LDX1 is electrically connected to the second power line Lpw2 for receiving the system low voltage VSS. The transistor T23 as a detection circuit switch is disposed on the first surface 111 of the first backplane 110 to form a shorter signal path, thereby providing a better resistance.

In the embodiment of the present invention, the inner vias VA21 and VA22 are disposed in the pixel circuits PIXb, i.e., the inner vias VA21 and VA22 are disposed in the pixel array area APX where the pixel circuits PIXb are disposed. The detection switch signal Stg may be disposed outside the pixel array area APX, and the signal through holes electrically connected to the scan signal line LSC, the data signal line LDX, and the detection switch signal Stg may be disposed inside the pixel array area APX where the pixel circuits PIXb are disposed or outside the pixel array area APX, which may be determined according to circuit design.

FIG. 6 is a schematic diagram of a pixel circuit according to another embodiment of the present invention. Referring to fig. 1 and 6, in the present embodiment, the second portion PT3 of the pixel circuit PIXc includes transistors T31-T35 and a capacitor C3, and the first portion PT1 includes transistors T36, T37 and a light emitting device LDX 3.

A first terminal of the transistor T31 is electrically connected to a reference voltage line (not shown) to receive the reference voltage VREF, and a control terminal of the transistor T31 is electrically connected to the light emitting signal line (LEM shown in fig. 4) to receive the light emitting signal EM. The first terminal of the transistor T32 is electrically connected to the second terminal of the transistor T31, the control terminal of the transistor T32 is electrically connected to a second scan signal line (not shown) for receiving the second scan signal S2, and the second terminal of the transistor T32 is electrically connected to the DATA signal line LDX for receiving the DATA voltage DATA.

One end of the capacitor C3 is electrically connected to the second end of the transistor T31. The first terminal of the transistor T33 is electrically connected to the other terminal of the capacitor C3, and the control terminal of the transistor T33 is electrically connected to a second scan signal line (not shown) for receiving the second scan signal S2. The first terminal of the transistor T34 is electrically connected to the second terminal of the transistor T33, and the control terminal of the transistor T34 is electrically connected to a second scan signal line (not shown) for receiving the second scan signal S2.

The first terminal of the transistor T35 is electrically connected to the second terminal of the transistor T33, the control terminal of the transistor T35 is electrically connected to a first scan signal line (not shown) for receiving the first scan signal S1, and the second terminal of the transistor T35 is electrically connected to a reference voltage line (not shown) for receiving the reference voltage VREF. The first terminal of the transistor T36 is electrically connected to the first power line Lpw1 for receiving the system high voltage VDD, the control terminal of the transistor T36 is electrically connected to the other terminal of the capacitor C3 through the inner via VA31, and the second terminal of the transistor T36 is electrically connected to the second terminal of the transistor T33 through the inner via VA 32. The first terminal of the transistor T37 is electrically connected to the second terminal of the transistor T36, and the control terminal of the transistor T37 is electrically connected to the light emitting signal line (LEM shown in fig. 4) through the inner via VA33 for receiving the light emitting signal EM. The anode terminal of the light emitting device LDX3 is electrically connected to the second terminal of the transistor T37, and the cathode terminal of the light emitting device LDX3 is electrically connected to the second power line Lpw2 for receiving the system low voltage VSS. The transistors T31-T35 as different control switch elements are all disposed on the third surface 131 of the second substrate 130, so that they can be driven synchronously to reduce the delay problem and the number of through holes.

In the embodiment of the invention, the inner vias VA31 through VA33 are disposed in the pixel circuits PIXc, i.e., the inner vias VA31 through VA33 are disposed in the pixel array area APX where the pixel circuits PIXc are disposed. The reference voltage line and the light emitting signal line may be disposed outside the pixel array area APX, and the signal through holes electrically connected to the reference voltage line, the light emitting signal line, the first scanning signal line, the second scanning signal line, and the signal through holes may be disposed inside the pixel array area APX where the pixel circuits PIXc are disposed or outside the pixel array area APX, which may be determined according to circuit design.

Fig. 7 is a schematic layout diagram of power lines and signal lines of a display panel according to an embodiment of the invention. Referring to fig. 1 and 7, in the embodiment, the power line Lpw1 disposed on the first substrate 110 may be in a mesh shape. An angle θ between the extending direction d2 (corresponding to the first extending direction) of the mesh of the power line Lpw1 disposed on the first substrate 110 and the extending direction d1 (corresponding to the second extending direction) of the scan signal line LSC disposed on the second substrate 130 may be 0 to 90 degrees. Furthermore, the included angle θ between the extending direction d2 of the power line Lpw1 and the extending direction d1 of the scan signal line LSC may be 30 to 60 degrees, which may be determined according to the circuit layout requirement, but the embodiment of the invention is not limited thereto. Therefore, the moire (moire pattern) problem can be improved by different pitches (pitch) and angles.

In summary, in the display panel according to the embodiment of the invention, the first substrate and the second substrate stacked in the vertical direction are used to increase the circuit layout space of the display panel, so as to increase the resolution or the space utilization of the display panel, and achieve the purpose of narrow frame.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A display panel, comprising:

a first substrate having a first surface and a second surface opposite to the first surface;

a second substrate having a third surface and a fourth surface opposite to the third surface;

a plurality of pixel circuits each having a first portion and a second portion, wherein the first portions of the pixel circuits are arranged on the first surface in an array, and the second portions of the pixel circuits are arranged on the third surface in an array; and

and a plurality of through holes formed on the first substrate and the second substrate to electrically connect the first part and the second part of each pixel circuit.

2. The display panel of claim 1, further comprising an adhesive layer for adhering the first substrate and the second substrate.

3. The display panel of claim 2, wherein the third surface is opposite the second surface based on the adhesion layer.

4. The display panel of claim 2, wherein the fourth surface is opposite the second surface based on the adhesion layer.

5. The display panel of claim 1, wherein a plurality of inner through holes of the through holes are disposed in a pixel array region where the pixel circuits are disposed.

6. The display panel of claim 1, wherein a plurality of signal vias of the plurality of vias are disposed in a pixel array region in which the plurality of pixel circuits are disposed.

7. The display panel of claim 1, wherein a plurality of signal vias of the plurality of vias are disposed outside a pixel array region in which the plurality of pixel circuits are disposed.

8. The display panel of claim 1, wherein the first portions of the pixel circuits comprise at least one light emitting element.

9. The display panel of claim 8, wherein the at least one light emitting element comprises one of a light emitting diode and an organic light emitting diode.

10. The display panel of claim 8, further comprising a gate driving circuit disposed on the fourth surface.

11. The display panel of claim 1, wherein the semiconductor layer of the first substrate is the same as the semiconductor layer of the second substrate.

12. The display panel of claim 1, wherein the semiconductor layer of the first substrate is different from the semiconductor layer of the second substrate.

13. The display panel according to claim 12, wherein the semiconductor layer of the first substrate is made of low temperature polysilicon, and the semiconductor layer of the second substrate is made of metal oxide semiconductor.

14. The display panel of claim 1, wherein an angle between a first extending direction of the power line disposed on the first substrate and a second extending direction of the signal line disposed on the second substrate is 0 to 90 degrees.

15. The display panel of claim 14, wherein an angle between the first extending direction and the second extending direction is 30 to 60 degrees.