CN112349705A - Electronic packaging device - Google Patents

Electronic packaging device Download PDF

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Publication number
CN112349705A
CN112349705A CN201911218158.5A CN201911218158A CN112349705A CN 112349705 A CN112349705 A CN 112349705A CN 201911218158 A CN201911218158 A CN 201911218158A CN 112349705 A CN112349705 A CN 112349705A
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CN
China
Prior art keywords
carrier
external terminal
electronic package
package device
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911218158.5A
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Chinese (zh)
Inventor
高靖尧
王政杰
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Publication of CN112349705A publication Critical patent/CN112349705A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides an electronic packaging device, which comprises a first carrier plate, a second carrier plate, a plurality of semiconductor elements arranged on one of the first carrier plate or the second carrier plate, and a packaging colloid arranged between the first carrier plate and the second carrier plate. The first carrier has a first surface and a second surface opposite to the first surface. The first carrier includes at least one first external terminal disposed on the first surface. The second carrier is arranged opposite to the first carrier and is provided with a third surface and a fourth surface opposite to the third surface. The second carrier includes at least one second external terminal disposed on the fourth surface. The third surface faces the second surface. The encapsulant encapsulates the first carrier, the second carrier, and the plurality of semiconductor devices. The plurality of semiconductor elements are respectively electrically connected with the at least one first external terminal and the at least one second external terminal.

Description

Electronic packaging device
Technical Field
The present disclosure relates to electronic packaging devices, and particularly to an electronic packaging device.
Background
With the change of payment habits of users, the integration of electronic wallets and prepaid stored value into portable electronic devices is one of the trends of future development of electronic products. Generally, a portable electronic device can achieve functions of computing, encrypting, two-way communication, security function and data storage by using a Smart Card (Smart Card) and a Memory Card (Memory Card), respectively.
As portable electronic devices are continuously developed toward small size, multifunction and high performance, the internal space of the electronic devices is miniaturized. However, the design of separately configuring the smart card and the memory card may prevent the electronic device from realizing a small size and may affect the configuration of the components in the electronic device. Therefore, a smart card capable of integrating communication, security functions and data storage is a problem to be solved in the art.
Disclosure of Invention
The invention provides an electronic packaging device which can combine communication and safety functions and data storage functions and has double-sided output to achieve the plug-and-play effect.
The electronic packaging device comprises a first carrier plate, a second carrier plate, a plurality of semiconductor elements and a packaging colloid, wherein the first carrier plate is provided with a first surface and a second surface opposite to the first surface, the second carrier plate is provided with a third surface and a fourth surface opposite to the third surface, the plurality of semiconductor elements are arranged on one of the first carrier plate and the second carrier plate, and the packaging colloid is arranged between the first carrier plate and the second carrier plate. The first carrier includes at least one first external terminal disposed on the first surface. The second carrier is arranged opposite to the first carrier and comprises at least one second external terminal arranged on the fourth surface. The third surface faces the second surface. The encapsulant encapsulates the first carrier, the second carrier, and the plurality of semiconductor devices. The plurality of semiconductor elements are respectively electrically connected with the at least one first external terminal and the at least one second external terminal.
In an embodiment of the invention, the first carrier further includes a first conductive pattern disposed on the second surface. The first conductive pattern includes a plurality of first inner pads and a plurality of first contacts. The first contacts are electrically connected to the first inner pads. The semiconductor elements are electrically connected to the first inner pads.
In an embodiment of the invention, a portion of the plurality of conductive structures is disposed between the first carrier and the second carrier and electrically connected to the plurality of first contacts and the plurality of second contacts of the second carrier, so as to transmit signals of the plurality of semiconductor devices to the second carrier. The packaging colloid wraps the plurality of conductive structures.
In an embodiment of the invention, the plurality of conductive structures include conductive wires or solder balls.
In an embodiment of the invention, the plurality of semiconductor devices further include a plurality of first memory chips, at least one second memory chip, and a control chip. The plurality of semiconductor elements are arranged on the second surface of the first carrier plate.
In an embodiment of the invention, the plurality of first Memory chips are Flash Memory chips (Flash memories), and the at least one second Memory chip is a Subscriber Identity Module (SIM) chip.
In an embodiment of the invention, the at least one second memory chip is disposed on the second carrier and electrically connected to the second external terminal. The electronic packaging device also comprises a sealing colloid which completely seals at least one second memory chip and is configured on the second surface of the first carrier plate, wherein the sealing colloid is coated by the packaging colloid for the second time.
In an embodiment of the invention, the plurality of first memory chips are electrically connected to the first carrier through metal bonding wires.
In an embodiment of the invention, the second carrier is a metal conductor.
In an embodiment of the invention, a Film On Wire (FOW) is disposed On the third surface of the second carrier.
Based on the above, in the electronic package device according to an embodiment of the present invention, the semiconductor device having the communication and security functions and the data storage function can be integrated into the electronic package device, and then the signals with different functions are respectively conducted to the first external terminal on the first surface and the second external terminal on the fourth surface, so as to achieve the effect of dual-sided output. Therefore, the electronic packaging device can be applied to the existing electronic equipment, and the plug and play effect is achieved. In addition, the manufacturing method of the electronic packaging device can be simplified, the manufacturing time can be saved, the manufacturing cost can be reduced, and the requirement of the electronic device for small size can be met.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic cross-sectional view of an electronic package device according to an embodiment of the invention;
fig. 2 is a schematic cross-sectional view of an electronic package device according to another embodiment of the invention;
fig. 3 is a schematic cross-sectional view of an electronic package device according to still another embodiment of the invention;
fig. 4 is a schematic cross-sectional view of an electronic package device according to still another embodiment of the invention.
The reference numbers illustrate:
10. 10A, 10B, 10C: electronic packaging device
100: first carrier plate
101: first surface
102: second surface
110: first external terminal
120: first conductive pattern
122: first inner pad
124: first contact
140: conductive structure
142: solder ball
144: conducting wire
160: metal welding wire
200. 200A, 200B, 200C: second carrier plate
201: third surface
202: the fourth surface
210: second external terminal
224: second contact
230: metal conductor
240: glue film
300: semiconductor device with a plurality of semiconductor chips
320: control chip
340: first memory chip
360: second memory chip
400: packaging colloid
420: sealing colloid
Detailed Description
Fig. 1 is a schematic cross-sectional view of an electronic package device according to an embodiment of the invention. Referring to fig. 1, an electronic package device 10 includes a first carrier 100, a second carrier 200, a plurality of semiconductor devices 300, and a molding compound 400. In the present embodiment, the second carrier 200 is disposed opposite to the first carrier 100, and the plurality of semiconductor devices 300 are disposed on the first carrier 100 and located between the first carrier 100 and the second carrier 200. The encapsulant 400 is disposed between the first carrier 100 and the second carrier 200 to encapsulate the first carrier 100, the second carrier 200 and the plurality of semiconductor devices 300, so as to complete the package of the electronic package device 10. In the present embodiment, the first carrier 100 and the second carrier 200 are, for example, circuit carriers (circuit carriers) capable of carrying semiconductor devices 300 (e.g., chips), but the invention is not limited thereto.
Referring to fig. 1, the first carrier 100 has a first surface 101 and a second surface 102 opposite to the first surface 101. For example as shown in fig. 1. The first surface 101 faces downward in fig. 1, for example, and the second surface 102 faces upward in fig. 1, for example, but the invention is not limited thereto. The material of the first carrier 100 is, for example, a multi-layer substrate manufactured by FR-4 substrate lamination technology, or pre-molded epoxy resin (Molding compound) or ceramic substrate lamination technology, but the invention is not limited thereto. In other embodiments, the first carrier 100 may also be a substrate made of a flexible insulating material.
In the embodiment, the first carrier 100 includes at least one first external terminal 110 disposed on the first surface 101. The first carrier 100 further includes a first conductive pattern 120 disposed on the second surface 102. The first conductive pattern 120 includes a plurality of first inner pads 122 disposed on the second surface 102 and a plurality of first contacts 124 disposed on the second surface 102. The first inner pads 122 and the first contacts 124 are made of the same conductive material by patterning, for example, and the plurality of first contacts 124 and the plurality of first inner pads 122 can be electrically connected. In the present embodiment, the material of the first external terminal 110 and the first conductive pattern 120 is generally selected from a metal material or a metal alloy, for example, a conductive metal material such as gold, copper, silver, palladium, aluminum or an alloy thereof, but the invention is not limited thereto. In addition, the material of the first external terminal 110 and the material of the first conductive pattern 120 may be the same or different, and the invention is not limited thereto.
In the present embodiment, for clarity and convenience of illustration, it is not shown that the first external connection terminal 110 and the first inner pad 122 of the first conductive pattern 120 can be conducted. In practice, the first external terminal 110 may be electrically connected to the first conductive pattern 120 to transmit signals from the second surface 102 to the first surface 101. Under the above configuration, the first carrier 100 of the present embodiment is, for example, a circuit carrier (circuit carrier) capable of carrying the semiconductor device 300 (e.g., a chip), but the invention is not limited thereto.
As shown in fig. 1, the second carrier 200 may be disposed adjacent to the second surface 102 of the first carrier 100, and the second carrier 200 has a third surface 201 and a fourth surface 202 opposite to the third surface 201. In this embodiment, the third surface 201 of the second carrier 200 may face the second surface 102 of the first carrier 100. In other words, the first surface 101 and the fourth surface 202 may be used as outer surfaces of the electronic package device 10 and face opposite directions (for example, respectively face downward and upward in fig. 1), in this embodiment, the material of the second carrier 200 may be the same as that of the first carrier 100, such as a multi-layer substrate manufactured by FR-4 substrate lamination technology, or pre-molded epoxy (Molding compound) or ceramic substrate lamination technology, but the invention is not limited thereto.
In this embodiment, the second carrier 200 includes at least one second external terminal 210 disposed on the fourth surface 202 of the second carrier 200. In other words, the second external terminal 210 and the first external terminal 110 are disposed to face in opposite directions, respectively. For example, the first external terminal 110 faces downward in fig. 1, and the second external terminal 210 faces upward in fig. 1. The number of the first external terminal 110 and the second external terminal 210 is not limited to the number shown in fig. 1. In fact, the number of the first external terminal 110 and the second external terminal 210 can be set according to the user's requirement. In the embodiment, the material of the second external terminal 210 may be the same as or different from the material of the first external terminal 110, and for example, the second external terminal is made of a conductive metal material such as gold, copper, silver, palladium, aluminum or an alloy thereof, but the invention is not limited thereto.
As shown in fig. 1, a plurality of second contacts 224 are further disposed on the third surface 201 of the second carrier 200. A plurality of second contacts 224 may be disposed corresponding to the overlapping first contacts 124. In the present embodiment, for clarity and convenience of illustration, it is not shown that the second external terminal 210 and the second contact 224 can be conducted. In practice, the second external terminal 210 may be electrically connected to the second contact 224 to transmit the signal from the third surface 201 to the fourth surface 202. In the present embodiment, the material of the second contact 224 may be the same as or different from the material of the second external terminal 210, and for example, the second contact is made of a conductive metal material such as gold, copper, silver, palladium, aluminum or an alloy thereof, but the invention is not limited thereto.
In the embodiment, the plurality of semiconductor devices 300 are disposed on the second surface 102 of the first carrier 100, but the invention is not limited thereto. In some embodiments, the plurality of semiconductor devices 300 may be disposed on one of the first carrier 100 or the second carrier 200 or disposed on the first carrier 100 and the second carrier 200, respectively. In the manufacturing process, the semiconductor devices 300 are disposed on the same carrier, which simplifies the manufacturing process and reduces the manufacturing cost.
As shown in fig. 1, the plurality of semiconductor devices 300 are disposed on the second surface 102 of the first carrier 100, and the plurality of semiconductor devices 300 are electrically connected to the plurality of first inner pads 122, respectively. In detail, the plurality of semiconductor devices 300 includes a plurality of first memory chips 340, at least one second memory chip 360, and a control chip 320. The plurality of first memory chips 340 may be stacked on the second surface 102 to form a stacked structure of a plurality of chips. It should be noted that fig. 1 only illustrates two first memory chips 340 stacked on the second surface 102, but the invention is not limited thereto. In practice, the stacking number of the first memory chips 340 may be single or more, and is set according to the user's requirement.
In the present embodiment, at least one second memory chip 360 and the control chip 320 are also respectively disposed on the second surface 102. Fig. 1 illustrates only one second memory chip 360 and one control chip 320 disposed on the second surface 102, but the invention is not limited thereto. In fact, the number of the second memory chips 360 and the control chip 320 may be single or more, and is set according to the user's requirement.
In the embodiment, the plurality of first Memory chips 340 are, for example, Flash Memory chips (Flash memories), and the second Memory chip 360 is, for example, a Subscriber Identity Module (SIM).
As shown in fig. 1, the semiconductor devices 300 may be electrically connected to the first carrier 100 through bonding wires 160. In detail, the plurality of first memory chips 340 may be electrically connected to the first inner pads 122 on the first carrier 100 through the metal bonding wires 160. In more detail, the plurality of first memory chips 340 can also be electrically connected to each other through the metal bonding wires 160, and then electrically connected to the first carrier 100. In addition, the second memory chip 360 and the control chip 320 can also be electrically connected to the first inner pads 122 on the first carrier 100 by the metal bonding wires 160. Under the above arrangement, the semiconductor devices 300 may be electrically connected to the first carrier 100. In the present embodiment, the material of the metal bonding wire 160 is, for example, a conductive metal material such as gold, copper, silver, palladium, aluminum or an alloy thereof, but the invention is not limited thereto.
It is noted that the electronic package device 10 of the present embodiment can electrically connect the semiconductor device 300 on the first carrier 100 to the second external terminal 210 on the second carrier 200. In detail, the electronic package device 10 further includes a plurality of conductive structures 140 disposed between the first carrier 100 and the second carrier 200. As shown in fig. 1, the plurality of conductive structures 140 are electrically connected between the plurality of first contacts 124 of the first carrier 100 and the plurality of second contacts 224 of the second carrier 200, so as to transmit signals of the semiconductor device 300 to the second carrier 200. More specifically, the first memory chip 340 may be electrically connected to the first external terminal 110 through the first inner pad 122 to transmit a signal to the first external terminal 110 on the first surface 101. The second memory chip 360 can be electrically connected to the second contact 224 through the first inner pad 122 electrically connected to the first contact 124 and the conductive structure 140. Since the second contacts 224 can be electrically connected to the second external terminals 210, signals of the second memory chips 360 can be transmitted from the first carrier 100 to the second external terminals 210 on the second carrier 200. In this way, the first memory chips 340 and the second memory chips 360 of the plurality of semiconductor devices 300 can be electrically connected to the first external terminal 110 and the second external terminal 210, respectively.
Since the first external terminal 110 and the second external terminal 210 can face opposite directions, the first memory chip 340 is a flash memory chip with a data storage function and the second memory chip 360 is a sim chip with a communication and security function. Therefore, the electronic package device 10 can combine the communication and security functions and the data storage function, and can conduct the chips with different functions to the first external terminal 110 on the first surface 101 and the second external terminal 210 on the fourth surface 202, thereby achieving the effect of dual-sided output. In this way, the electronic package device 10 of the present embodiment can be applied to the existing electronic equipment or electronic adapter, and can achieve the plug and play effect without designing a connection interface. In addition, the electronic package device 10 can meet the demand for small size of the electronic device.
In the present embodiment, the conductive structure 140 includes, for example, a solder ball 142. The conductive structure 140 is generally made of a metal material or a metal alloy, such as gold, copper, silver, palladium, aluminum or an alloy thereof, but the invention is not limited thereto. In the present embodiment, the encapsulant 400 may further encapsulate the plurality of conductive structures 140.
The following briefly describes the fabrication process of the electronic package 10. In the process, a first carrier 100 having a first conductive pattern 120 and a first external terminal 110 is provided. The first conductive pattern 120 and the first external terminal 110 are disposed on the second surface 102 and the first surface 101, respectively. Next, the plurality of semiconductor devices 300 are disposed on the second surface 102 of the first carrier 100, and the plurality of semiconductor devices 300 are electrically connected to the first carrier 100 by wire bonding (wire bonding) through the metal bonding wires 160. Then, the solder balls 142/the conductive structures 140 are disposed on the first carrier 100. Then, the second carrier 200 having the second contact 224 and the second external terminal 210 is disposed opposite to the first carrier 100 and is bonded to the conductive structure 140. The second contact 224 and the second external terminal 210 are disposed on the third surface 201 and the fourth surface 202, respectively. The third surface 201 faces the second surface 102. As a result, the semiconductor device 300 and the conductive structure 140 are located between the first carrier 100 and the second carrier 200, and the conductive structure 140 is electrically connected to the first contact 124 and the second contact 224. Next, the encapsulant 400 is disposed between the first carrier 100 and the second carrier 200 to encapsulate the first carrier 100, the second carrier 200, the semiconductor device 300 and the conductive structure 140. In the embodiment, the material of the encapsulant 400 is, for example, epoxy resin or other polymer materials, but the invention is not limited thereto. To this end, the electronic packaging device 10 is packaged.
In short, since the electronic package device 10 can integrate the semiconductor device 300 with communication and security functions and data storage functions onto the first carrier 100, and then respectively conduct signals with different functions to the first external terminal 110 on the first surface 101 and the second external terminal 210 on the fourth surface 202, a dual-sided output effect is achieved. Thus, the electronic package device 10 of the present embodiment can be applied to the existing electronic equipment without designing a connection interface, and can achieve the plug and play effect. In addition, the electronic package device 10 can meet the demand for small size of the electronic device.
Fig. 2 is a schematic cross-sectional view of an electronic package device according to another embodiment of the invention. It should be noted that the electronic package device 10A and the manufacturing process thereof in the present embodiment are similar to the electronic package device 10 and the manufacturing process thereof in the previous embodiment, so the same or similar components are denoted by the same or similar reference numerals, and the same or similar technical contents may refer to the previous embodiment, which is not repeated herein.
Referring to fig. 2, the electronic package 10A of fig. 2 is substantially similar to the electronic package 10 of fig. 1, except that: in the present embodiment, the second carrier 200A of the electronic package device 10A is a metal conductor 230. The metal conductor 230 is, for example, a metal plate or a metal sheet, and the material thereof is, for example, made of a conductive metal material such as gold, copper, silver, palladium, aluminum or an alloy thereof, but the invention is not limited thereto. In the embodiment, the material of the metal conductor 230 and the second external terminal 210 may be the same or different, but the invention is not limited thereto.
In this embodiment, the second external terminal 210 may be disposed on the fourth surface 202 of the metal conductor 230. In some embodiments, the second external terminal 210 may also be directly formed by the metal conductor 230 and be integrally formed. In other words, the second external terminal 210 may be formed by patterning the metal conductor 230, but the invention is not limited thereto.
As shown in fig. 2, a Film 240(Film On Wire, FOW) is disposed On the third surface 201 of the metal conductor 230/the second carrier 200A. The adhesive film 240 is disposed between the second carrier 200A and the plurality of semiconductor devices 300 on the first carrier 100. For example, the adhesive film 240 may contact and fix the second carrier 200A to the first memory chip 340, but the invention is not limited thereto. In some embodiments, a Die Attach Film (DAF) or a B-Stage adhesive Film (B-Stage) may be used instead of the adhesive Film.
In the embodiment, a portion of the conductive structure 140 is disposed between the first carrier 100 and the second carrier 200A. Specifically, the conductive structure 140 includes a wire 144, and the second carrier 200A and the first carrier 100 can be electrically connected by wire bonding through the wire 144. As such, a portion of the conductive wire 144 can be bonded to the fourth surface 202 of the metal conductor 230 and the first contact 124 of the first carrier 100. In the present embodiment, a portion of the metal conductor 230 not in contact with the second external terminal 210 may be defined as the second contact 224. That is, the second contact 224 may be a portion of the metal conductor 230 and be integrally formed. The wires 144 may be electrically connected to the first contacts 124 and the second contacts 224, so as to conduct the first carrier 100 to the second carrier 200A.
Under the above arrangement, the second semiconductor chip 360 can be electrically connected to the first contact 124 through the metal wire 160, and then electrically connected to the second contact 224 and the metal conductor 230 through the wire 144, so as to transmit the second semiconductor chip 360 to the second external terminal 210. Thus, the electronic package device 10A of the present embodiment can obtain the same effects as the above embodiments, and therefore, the description thereof is omitted.
In the embodiment, the encapsulant 400 encapsulates the first carrier 100, the second carrier 200A, the semiconductor device 300, the adhesive film 240 and the wires 144 after the second carrier 200A completes the electrical connection with the first carrier 100. Therefore, the manufacturing process can be simplified, and the manufacturing time and cost can be saved.
As shown in fig. 2, a portion of the encapsulant 400 may cover the fourth surface 202 of the second carrier 200A. In addition, the surface of the encapsulant 400 may be aligned with the surface of the second external terminal 210, but the invention is not limited thereto. Under the above configuration, the encapsulant 400 may further protect the second carrier 200A, thereby improving the reliability of the electronic package device 10A. In addition, the encapsulant 400 may also make the surface of the electronic package 10A flat.
Fig. 3 is a schematic cross-sectional view of an electronic package device according to still another embodiment of the invention. The structure and the manufacturing method of the electronic package device 10B of the present embodiment are similar to those of the electronic package device 10A of the previous embodiment, and only the difference therebetween will be described below.
Referring to fig. 3, the electronic package device 10B of fig. 3 is substantially similar to the electronic package device 10A of fig. 2, except that: in the present embodiment, the second carrier 200B of the electronic package device 10B is not a metal conductor, but a circuit carrier similar to the second carrier 200 of the electronic package device 10 of fig. 1 is used. In the embodiment, the adhesive film 240 is disposed between the second carrier 200B and the plurality of semiconductor devices 300 to fix the second carrier 200B to the first carrier 100.
In this embodiment, the second carrier 200B has a first height H1 and a second height H2. The first height H1 is greater than the second height H2. As shown in fig. 3, the first height H1 may be defined by a distance between the third surface 201 and the fourth surface 202. In addition, a portion of the second carrier 200B having the second height H2 may be configured with the second contact 224. The conductive wires 144 can be wire bonded to electrically connect the first contacts 124 and the second contacts 224.
Since the height difference may exist between the first height H1 and the second height H2, the portion of the conductive wires 144 may be located in the space generated by the height difference and electrically connected to the second contacts 224, so that the encapsulant 400 may cover the second contacts 224 and the conductive wires 144 when encapsulating the second carrier 200B. As a result, the encapsulant 400 can further protect the second contacts 224 and the wires 144, thereby improving the reliability of the electronic package device 10B.
In the present embodiment, the encapsulant 400 may be located in the space generated by the height difference and aligned with the fourth surface 202 and the second external terminal 210. Thus, the encapsulant 400 can also make the surface of the electronic package device 10B flat. Through the above design, the electronic package device 10B of the present embodiment can achieve the same effects as those of the above embodiments, and therefore, the detailed description thereof is omitted.
Fig. 4 is a schematic cross-sectional view of an electronic package device according to still another embodiment of the invention. The structure and the manufacturing method of the electronic package device 10C of the present embodiment are similar to those of the electronic package device 10 of the above embodiments, and only the difference therebetween will be described below.
Referring to fig. 4, the electronic package device 10C of fig. 4 is substantially similar to the electronic package device 10 of fig. 1, except that: in the present embodiment, at least one second memory chip 360 is disposed on the second carrier 200C. The second memory chip 360 is electrically connected to the second contact 224 of the second carrier 200C through the metal bonding wire 160, so as to be electrically connected to the second external terminal 210. Accordingly, the second memory chip 360 may transfer a signal to the second external terminal 210 on the fourth surface 202. In addition, the first memory chip 340 is electrically connected to the first inner pad 122 of the first carrier 100 through the metal bonding wire 160. In this way, the electronic package device 10C can conduct the semiconductor element 300 to the first external terminal 110 and the second external terminal 210 respectively without using a conductive structure. Accordingly, the first memory chip 340 may transmit a signal to the first external terminal 110 on the first surface 101. Under the above configuration, the electronic package device 10C can achieve the effect of dual-sided output, and further achieve the effect of plug and play.
In addition, the electronic package device 10C further includes a sealant 420 that completely encapsulates the second memory chip 360, and the sealant 420 is disposed on the second surface 102 of the first carrier 100. Specifically, in the manufacturing process, the second memory chip 360 may be first disposed on the third surface 201 of the second carrier 200C, and then wire bonding is performed to conduct the second memory chip 360 to the second external terminal 210. Then, the encapsulant 420 is disposed on the third surface 201 to encapsulate the second memory chip 360 and the second carrier 200C. The material of the encapsulant 420 is, for example, epoxy resin or other polymer materials, but the invention is not limited thereto. Then, the first memory chip 340 and the control chip 320 are disposed on the second surface 102 of the first carrier 100, and wire bonding is performed to conduct the first memory chip 340 to the first external terminal 110. Then, the encapsulant 420 encapsulating the second carrier 200C is disposed on the second surface 102 of the first carrier 100, such that the encapsulant 420 is located between the first carrier 100 and the second carrier 200C. Next, the encapsulant 400 encapsulates the first carrier 100, the first memory chip 340, the control chip 320, the second carrier 200C and the encapsulant 420. That is, the encapsulant 420 may be secondarily coated by the encapsulant 400.
Under the above arrangement, the packaged second carrier 200C with communication and security functions can be simply disposed on the first carrier 100 with data storage function and packaged, so as to obtain the plug-and-play electronic packaging device 10C with dual-sided output, which can simplify the process steps and reduce the manufacturing cost.
In summary, the electronic package device of the present invention can integrate the semiconductor devices with communication and security functions (e.g., Subscriber Identity Module (SIM)) and data storage functions (e.g., SD Card and Micro SD Card) into the electronic package device, and then respectively conduct signals with different functions to the first external connection terminal on the first surface and the second external connection terminal on the fourth surface, thereby achieving the effect of dual-sided output. Therefore, the electronic packaging device can be applied to the existing electronic equipment without additionally designing a connecting interface, and can achieve the plug and play effect. In addition, the manufacturing method of the electronic packaging device can be simplified, the manufacturing time can be saved, the manufacturing cost can be reduced, and the requirement of the electronic device for small size can be met.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. An electronic packaging apparatus, comprising:
the first carrier plate is provided with a first surface and a second surface opposite to the first surface, and the first carrier plate comprises at least one first external terminal which is configured on the first surface;
the second carrier is arranged opposite to the first carrier and is provided with a third surface and a fourth surface opposite to the third surface, the second carrier comprises at least one second external terminal arranged on the fourth surface, and the third surface faces the second surface;
the plurality of semiconductor elements are configured on one of the first carrier plate or the second carrier plate; and
the encapsulant is disposed between the first carrier and the second carrier and encapsulates the first carrier, the second carrier and the plurality of semiconductor devices,
the plurality of semiconductor elements are electrically conducted to the at least one first external terminal and the at least one second external terminal respectively.
2. The electronic package device of claim 1, wherein the first carrier further comprises a first conductive pattern disposed on the second surface, the first conductive pattern comprising:
a plurality of first inner pads; and
a plurality of first contacts, wherein the plurality of first contacts are in electrical communication with the plurality of first inner pads;
the plurality of semiconductor elements are electrically connected to the plurality of first inner pads.
3. The electronic package device according to claim 2, wherein portions of the conductive structures are disposed between the first carrier and the second carrier and electrically connected to the first contacts and the second contacts of the second carrier for transmitting signals of the semiconductor devices to the second carrier;
the packaging colloid coats the plurality of conductive structures.
4. The electronic package device of claim 3, wherein the plurality of conductive structures comprise wires or solder balls.
5. The electronic package device of claim 1, wherein the plurality of semiconductor devices further comprises a plurality of first memory chips, at least one second memory chip, and a control chip, wherein the plurality of semiconductor devices are disposed on the second surface of the first carrier.
6. The electronic package device of claim 5, wherein the plurality of first memory chips are flash memory chips and the at least one second memory chip is a subscriber identity module chip.
7. The electronic package device of claim 6, wherein the at least one second memory chip is disposed on the second carrier and electrically connected to the second external terminal,
the electronic packaging device further comprises a sealing colloid which completely seals the at least one second memory chip and is configured on the second surface of the first carrier, wherein the sealing colloid is coated by the packaging colloid for the second time.
8. The electronic package device of claim 5, wherein the plurality of first memory chips are electrically connected to the first carrier via metal bonding wires.
9. The electronic package device of claim 1, wherein the second carrier is a metal conductor.
10. The electronic package device according to claim 1 or 9, wherein the third surface of the second carrier has a glue film disposed thereon.
CN201911218158.5A 2019-08-08 2019-12-03 Electronic packaging device Pending CN112349705A (en)

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TW108128171A TWI706528B (en) 2019-08-08 2019-08-08 Electronic package device

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