CN112331652A - Bit line driving structure and three-dimensional memory structure - Google Patents
Bit line driving structure and three-dimensional memory structure Download PDFInfo
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- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention provides a bit line driving structure and a three-dimensional memory structure, wherein the bit line driving structure comprises: a first substrate; a driving device array formed on the first surface side of the first substrate and composed of a plurality of driving devices arranged; the driving device comprises an active device region, a source region, a drain region and a grid structure; the source region and the drain region are respectively positioned at two sides of the grid structure; intervals are arranged among the active device regions; in the same row of driving devices arranged in the row direction, the widths of the source region and the drain region of the driving device positioned at the two side edges are larger than the widths of the source region and the drain region of the driving device positioned at the non-two side edges. The invention introduces the driving device with wider source and drain region widths in the edge regions at two sides in the row direction, increases the junction area of the device by increasing the source and drain region widths in the edge regions, widens the depletion region, and reduces the electric field, thereby improving the source and drain breakdown voltage of the device; the whole voltage-resistant performance of the driving device array is improved by improving the weak point of the voltage resistance of the driving device array.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a bit line driving structure and a three-dimensional memory structure.
Background
With the increasing capacity and the number of layers of the 3D NAND memory, the operating voltage for driving the memory to operate is increased, and the related circuit needs to operate under a higher voltage condition without breakdown or other abnormalities. For example, in some memory cell erase operations, the bit line driver circuit needs to withstand at least a high voltage of 23V or more, and the voltage value is further increased as the device design requires more convergence of the array cell threshold voltage distribution.
At present, the peripheral bit line driving circuits corresponding to the array structure of the memory strings in the 3D NAND are also in an array structure, and are connected to the bit lines of the memory string array structure correspondingly. When an erase operation is performed on the entire memory block, the adjacent bit line driver devices in the same array will all be subjected to high voltages at the same time. At this time, the withstand voltage value will be increased by several volts compared to the case where a single bit line driver device alone is subjected to a high voltage. The design can enable the bit line driving circuit to have a higher voltage withstanding value so as to meet the requirement of high-voltage erasing operation, and meanwhile, the driving circuit can be ensured not to break down.
However, in the array structure of the above-described driving circuit, as for the driving device located at the edge position of the array, it is adjacent to other driving devices only at one side. Compared with the driving device which is arranged at the middle position of the array and provided with other driving devices at the left side and the right side, the voltage withstanding value of the driving device at the edge position of the array is obviously reduced, so that the driving device becomes a weak link which is easy to break down in the whole driving circuit array.
Therefore, it is necessary to provide a new bit line driving structure and a three-dimensional memory structure to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a bit line driving structure and a three-dimensional memory structure, which are used to solve the problem of weak edge withstand voltage of the driving circuit array in the prior art.
To achieve the above and other related objects, the present invention provides a bit line driving structure, comprising:
a first substrate having a first surface and a second surface disposed opposite to each other;
a driving device array formed on a first surface side of the first substrate, the driving device array being formed by arranging a plurality of driving devices;
the driving device comprises an active device region formed in the first substrate, a source region and a drain region formed in the active device region, and a gate structure formed above the active device region; the source region and the drain region are respectively positioned at two sides of the grid structure; a plurality of the active device regions have a space therebetween;
defining the direction of the source region pointing to the drain region as a source-drain direction, wherein the plurality of driving devices are arranged along mutually orthogonal row directions and column directions, and the source-drain direction is perpendicular to the row direction; defining the width of the source region in the direction vertical to the source and drain regions as the width of the source region, and defining the width of the drain region in the direction vertical to the source and drain regions as the width of the drain region; in the same row of the driving devices arranged in the row direction, the width of the source region of the driving device positioned at the two side edges is larger than that of the source region of the driving device positioned at the non-two side edges, and the width of the drain region of the driving device positioned at the two side edges is larger than that of the drain region of the driving device positioned at the non-two side edges.
As an alternative of the present invention, in the same row of the driving devices arranged in the row direction, the widths of the source regions of the driving devices located at both side edges are greater than the widths of the source regions of the driving devices located at non-both side edges by more than 25%, and the widths of the drain regions of the driving devices located at both side edges are greater than the widths of the drain regions of the driving devices located at non-both side edges by more than 25%.
As an alternative of the present invention, in the same row of the driving devices arranged in the row direction, the width of the source region of the driving device located at the two side edges is in the range of 0.65 to 0.75 μm; the width range of the source region of the driving device located at the non-two side edges is 0.5-0.6 μm.
As an alternative of the present invention, the width of the active device region in the direction perpendicular to the source-drain direction is defined as the active region width; in the same driving device, the width of the source region is equal to the width of the active region, and the width of the drain region is smaller than the width of the active region.
As an alternative of the present invention, in the same row of the driving devices arranged in the row direction, the intervals of the adjacent active device regions are equal.
As an alternative of the present invention, in the same row of the driving devices arranged in the row direction, the source-drain directions of the plurality of drivers are the same.
As an alternative of the present invention, the source-drain directions of the drivers of adjacent rows in the driving device array are opposite.
As an alternative of the present invention, in a row of the driving devices arranged in the row direction, the gate structures of a plurality of the driving devices are connected to each other.
As an alternative of the present invention, the structure for improving the withstand voltage of the bit line driving circuit of the three-dimensional memory further includes:
a shallow trench isolation structure formed in the first substrate, which isolates the active device regions of a plurality of the driving devices;
a first interconnect layer formed on the first surface of the first substrate, including an interlevel dielectric layer and an electrical connection structure; the interlayer dielectric layer covers the driving device; the electric connection structure penetrates through the interlayer dielectric layer and electrically leads out the driving device.
The present invention also provides a three-dimensional memory structure, comprising:
a second substrate having a third surface and a fourth surface disposed opposite to each other;
a memory array structure formed on a third surface of the second substrate, the memory array structure including a plurality of memory strings and a bit line structure connecting the memory strings;
according to the bit line driving structure of the present invention, the bit line driving structure is connected to the bit line structure.
As an alternative of the present invention, the memory array structure further includes an array common source structure, the array common source structure is used for controlling all memory strings in one memory block of the three-dimensional memory structure, and the bit line structures connected to the same memory block are connected to the same bit line driving structure.
As described above, the present invention provides a bit line driving structure and a three-dimensional memory structure, which have the following advantages:
aiming at the voltage resistance problem generated by a driving device array which integrally bears high voltage in the operations of erasing of a three-dimensional memory and the like, the invention introduces the driving device with wider source and drain region widths in the edge regions at two sides in the row direction, increases the junction area of the device by increasing the source and drain region widths in the edge regions, widens the depletion region, and reduces the electric field, thereby improving the source and drain breakdown voltage of the device; the whole voltage-resistant performance of the driving device array is improved by improving the weak point of the voltage resistance of the driving device array.
Drawings
Fig. 1 is a partial top view of a bitline driving structure according to a first embodiment of the invention.
FIG. 2 is a schematic cross-sectional view along AA' of FIG. 1.
Fig. 3 is a schematic cross-sectional view in the direction of BB' in fig. 1.
Fig. 4 is a schematic diagram illustrating a connection relationship between a single driving device and a single memory string of a memory array structure according to an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating a boundary of a depletion region of a driving device when performing an erase operation for the three-dimensional memory according to the first embodiment of the invention.
Fig. 6 is a schematic cross-sectional view illustrating a three-dimensional memory structure according to a second embodiment of the invention.
Description of the element reference numerals
101 first substrate
102 array of driving devices
103 drive device
103a active device region
103b source region
103c drain region
103d gate structure
104 shallow trench isolation structure
105 first interconnect layer
106 second substrate
106a doped well region
107 stack structure
107a gate layer
107b isolation layer
107c top select gate
107d bottom select gate
108 store string
108a gate dielectric layer
108b conductive layer
108c insulating layer
109 bit line architecture
110 array common source structure
111 second interconnect layer
111a interlayer dielectric layer
111b electrical connection structure
112 word line structure
113 bonding metal structure
114 bonding layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 6, the present embodiment provides a bit line driving structure, which is characterized in that: the method comprises the following steps:
a first substrate 101 having a first surface and a second surface disposed opposite to each other;
a driving device array 102 formed on a first surface side of the first substrate 101, the driving device array 102 being formed by arranging a plurality of driving devices 103;
the driving device 103 comprises an active device region 103a formed in the first substrate 101, a source region 103b and a drain region 103c formed in the active device region 103a, and a gate structure 103d formed above the active device region 103 a; the source region 103b and the drain region 103c are respectively located at two sides of the gate structure 103 d; a plurality of the active device regions 103a have a space therebetween;
defining a direction in which the source region 103b points to the drain region 103c as a source-drain direction, wherein the plurality of driving devices 103 are arranged along mutually orthogonal row and column directions, and the source-drain direction is perpendicular to the row direction; defining the width of the active device region 103a in the direction perpendicular to the source and drain direction as an active region width, defining the width of the source region in the direction perpendicular to the source and drain direction as a source region width, and defining the width of the drain region in the direction perpendicular to the source and drain direction as a drain region width; in the same row of the driving devices arranged in the row direction, the source region width W1 of the driving device 103 located at two side edges is greater than the source region width W2 of the driving device 103 located at non-two side edges, and the drain region width of the driving device located at two side edges is greater than the drain region width of the driving device located at non-two side edges. Optionally, in the present invention, in the same driving device 103, the source region width is equal to the active region width, and the drain region width is smaller than the active region width. In this embodiment, by setting the width of the drain region to be smaller than the width of the active region, and setting the distance from the drain region to the gate to be greater than the distance from the source region to the gate, the voltage resistance of the drain region of the device can be relatively improved, so that the region of the device has a higher breakdown voltage, and the voltage resistance between adjacent driving devices can also be improved by setting the width of the drain region to be relatively smaller.
Fig. 1 is a top view of the bit line driving structure provided in this embodiment. Fig. 2 is a schematic cross-sectional view in the direction of AA 'in fig. 1, and fig. 3 is a schematic cross-sectional view in the direction of BB' in fig. 1. As can be seen from fig. 1 to 3, a first surface of the first substrate 101 faces upward, and the driving device array 102 formed by arranging a plurality of driving devices 103 is formed on the first substrate 101. The driving device 103 includes an active device region 103a, a source region 103b, a drain region 103c, and a gate structure 103 d. The source region 103b and the drain region 103c are respectively located at two sides of the gate structure 103 d. The active device regions 103a have intervals therebetween, and in the driving device 103 in the same row, the intervals between the adjacent active device regions are equal. The active device region 103a, the source region 103b and the drain region 103c are doped region structures formed on the first substrate 101 by furnace diffusion or ion implantation. Not shown in the figure, the active device region 103a may further include other doped regions with different doping concentrations and types, such as a Lightly Doped Drain (LDD) structure. The direction C indicated by the arrow pointing from the source region 103b to the drain region 103C in fig. 1 and 2 is defined as a source-drain direction. The row direction is the X direction in fig. 1, and the column direction is the Y direction in fig. 1. As can be seen from fig. 1, in the same row of the driving devices 103 arranged in the X direction, the source region width W1 of the driving devices 103 located at two side edges is greater than the source region width W2 of the driving devices 103 located at non-two side edges. It should be noted that the driving device array described in the present invention controls an array of a memory block (block) in the three-dimensional memory correspondingly, all memory strings in a memory block are connected to the same array common source structure, and when the entire memory block is erased, the driving devices in the same driving device array will bear high voltage at the same time. And a three-dimensional memory may have a plurality of memory blocks, and the driving device array corresponding to each memory block may satisfy the definition of the source-drain region width, respectively.
As an example, in the same row of the driving devices 103 arranged in the row direction, the source region width W1 of the driving devices 103 located at both side edges is 25% or more larger than the source region width W2 of the driving devices 103 located at non-both side edges, and the drain region width of the driving devices 103 located at both side edges is 25% or more larger than the drain region width of the driving devices 103 located at non-both side edges. Optionally, in the same row of the driving devices 103 arranged in the row direction, the source region width W1 of the driving devices 103 located at two side edges ranges from 0.65 μm to 0.75 μm, and specifically, may be selected to be 0.7 μm; the source region width W2 of the driving device 103 at the non-two side edges ranges from 0.5 μm to 0.6 μm, and specifically, may be selected to be 0.55 μm.
As an example, as shown in fig. 1, in the same row of the driving devices 103 arranged in the X direction, the source-drain directions of a plurality of the drivers 103 are the same.
As an example, as shown in fig. 1, the source-drain directions of the drivers 103 of adjacent rows in the driving device array 102 are opposite. That is, two adjacent rows of the drivers 103 are adjacent with their drain regions 103c or adjacent with their source regions 103b in the column direction.
As an example, as shown in fig. 1, in a row of the driving devices 103 arranged in the row direction, a plurality of the driving devices 103 have the same gate structure 103d connecting them to each other. As shown in fig. 1, in the same row, a plurality of the driving devices 103 have the same gate structure 103d extending in the X direction.
Optionally, in this embodiment, the driving device 103 refers to a bit line driver of a three-dimensional memory, which is electrically connected to a bit line structure of a memory string of the three-dimensional memory.
As shown in fig. 4, a connection relationship diagram of a single driver device connecting a certain memory string 108 of a memory array structure is shown. In fig. 4, the bit line driver device is schematically represented as a MOS transistor element having a drain d, a gate g, a source s, and a base b. The memory array structure includes a stack structure 107 formed on a second substrate 106, a plurality of memory strings 108 formed in the stack structure 107, and an array common source structure 110 electrically connected to the memory strings 108. The stack structure 107 includes gate layers 107a and isolation layers 107b, which are alternately stacked, and top select gates 107c at the top and bottom select gates 107d at the bottom. The memory string comprises a gate dielectric layer 108a which is positioned at the outer layer and is in contact with a gate structure such as a gate layer 107a, a conductive layer 108b which is in contact with the gate dielectric layer 108a, and an insulating layer 108c which is filled in the middle. Optionally, the gate dielectric layer 108a includes a stacked structure formed by a silicon dioxide layer and a silicon nitride layer, the conductive layer 108b includes a polysilicon layer, and the insulating layer 108c includes a silicon dioxide layer. The memory array structure also includes a bit line structure 109 coupled to the driver device. A doped well region 106a is formed on the second substrate 106, and the memory string 108 is electrically connected to the array common source structure 110 through the doped well region 106a at the bottom. The sidewalls of the array common source structure 110 have insulating isolation dielectric layers that are electrically isolated from the stacked structure 107. When the memory string 108 is erased, the array common source structure 110 applies an erase voltage from the doped well region 106a side, which may be above 23V. In the driving device, the drain d is connected to the memory string 108 through the bit line structure 107b, and the gate g, the source s, and the base b are all grounded. That is, in the erase operation, the driving device will also bear high voltage, and the source-drain Breakdown Voltage (BVDS) of the driving device will become an important parameter for ensuring the normal operation of the device. For an erase operation of a driver array composed of a plurality of driver devices, when an erase voltage of, for example, about 23V is applied, the adjacent bit line driver devices will simultaneously receive a high voltage, and the high voltage that can be received by the bit line driver devices of the array structure will be increased by about 3V compared to a case where a single transistor receives a high voltage. For the driving device in the edge area of the array, since it is adjacent to other devices only on one side, the voltage that it can bear can be raised by only about 2V, and thus it will become the weak point of the whole driving array bearing high voltage. In addition, fig. 4 is a schematic diagram of a single driver device connected to a single memory string, and in an actual three-dimensional memory structure, one driver device can be connected to control a plurality of memory strings at the same time.
Fig. 5 is a schematic diagram of a driving device depletion region boundary of each of the drivers of the driving device array in the X direction in the cross-sectional diagram of fig. 3 when the three-dimensional memory performs an erase operation. As can be seen from fig. 5, the boundary of the depletion region of each driving device indicated by the thick solid line when a high voltage is applied varies according to the width of the source/drain region, and since the width of the source/drain region in the edge region of the array is increased in this embodiment, the junction area is increased, and the curvature radius of the junction area is larger than that of the driving device having a narrow width of the source/drain region, this expands the depletion layer of the device, reduces the electric field at the position at the same erase voltage, and increases the source/drain Breakdown Voltage (BVDS) of the driving device in the edge region. The weak point of the driving device array for bearing high voltage is improved, and the voltage resistance value of the whole driving device array is improved.
As an example, as shown in fig. 1 to 3 and 6, the bit line driving structure further includes:
a shallow trench isolation structure 104 formed in the first substrate 101, which isolates the active device regions 103a of the plurality of driving devices 103;
a first interconnect layer 105 formed on the first surface of the first substrate 101, including an interlayer dielectric layer 105a and an electrical connection structure 105 b; the interlayer dielectric layer 105a covers the driving device 103; the electrical connection structure 105b penetrates through the interlayer dielectric layer 105a and electrically leads out the driving device 103.
Optionally, the shallow trench isolation structure 104 is formed by etching an isolation trench and filling an isolation medium, and can electrically isolate the adjacent driving devices 103. The first interconnect layer 105 includes an interlayer dielectric layer 105a and an electrical connection structure 105 b. The interlayer dielectric layer 105a includes an insulating dielectric layer such as a silicon dioxide layer, and the electrical connection structure 105b further includes a conductive structure such as a contact hole structure and a metal interconnection layer.
Example two
Referring to fig. 6, the present embodiment provides a three-dimensional memory structure, which includes:
the driving structure for improving the withstand voltage of the bit line driving circuit according to the first embodiment;
a second substrate 106 having a third surface and a fourth surface disposed opposite to each other;
a memory array structure formed on a third surface of the second substrate 106, the memory array structure comprising a plurality of memory strings 108 and bit line structures 109 connecting the memory strings 108;
the bit line driving structure according to the first embodiment is connected to the bit line structure 109.
As an example, the memory string 108 is plural and formed in the stack structure 107. The stack structure 107 includes gate layers 107a and isolation layers 107b, which are alternately stacked, and top select gates 107c at the top and bottom select gates 107d at the bottom. The memory string comprises a gate dielectric layer 108a which is positioned at the outer layer and is in contact with a gate structure such as a gate layer 107a, a conductive layer 108b which is in contact with the gate dielectric layer 108a, and an insulating layer 108c which is filled in the middle.
The first substrate 101 and the second substrate 106 are bonded to each other through the first interconnect layer 105 and the second interconnect layer 108, and the bit line structure 109 of the memory array structure is electrically connected to the drain region 103c of the driving device 103 through the first interconnect layer 105 and the second interconnect layer 111.
In fig. 6, the third surface of the second substrate 106 faces downward, and the memory array structure is formed on one side of the third surface of the second substrate 106. The first substrate 101 and the second substrate 106 are bonded to each other through the first interconnect layer 105 and the second interconnect layer 111. Specifically, the two structures to be bonded are each formed with a bonding metal structure 113 to be electrically connected, and the surfaces to be bonded are each formed with a bonding layer 114 to be bonded by being attached to each other. The second interconnect layer 111 further includes an interlayer dielectric layer 111a and an electrical connection structure 111 b. The interlayer dielectric layer 111a includes an insulating dielectric layer such as a silicon dioxide layer, and the electrical connection structure 111b further includes a conductive structure such as a contact hole structure and a metal interconnection layer. The interlayer dielectric layer 111a covers the storage array structure; the electrical connection structure 111b penetrates through the interlayer dielectric layer 111a and electrically leads out the bit line structure 109. After bonding, the electrical connection relationship between the driving device 103 and the memory string 108 can be referred to as shown in fig. 4.
As an example, the memory array structure 107 further includes a word line structure 112 and an array common source structure 110. As shown in fig. 4, the bottom of the array common source structure 110 is connected to the memory string 108 through the doped well region 106a of the second substrate 106. The array common source structure 110 controls all memory strings 108 in a memory block (block) array, and the bitline structures connected to the same memory block are connected to the same bitline driver structure. The array common-source structure 110 of fig. 4 is not shown in fig. 6. A plurality of word line structures 112 are formed on the step region of the stack structure 107, and connect the gate layers 107 a. It is to be noted that fig. 6 only schematically shows a part of the general structure of the existing three-dimensional memory structure, and the specific structure thereof can be modified according to actual needs with reference to the prior art.
In summary, the present invention provides a bit line driving structure and a three-dimensional memory structure, wherein the driving structure includes: a first substrate having a first surface and a second surface disposed opposite to each other; a driving device array formed on a first surface side of the first substrate, the driving device array being formed by arranging a plurality of driving devices; the driving device comprises an active device region formed in the first substrate, a source region and a drain region formed in the active device region, and a gate structure formed above the active device region; the source region and the drain region are respectively positioned at two sides of the grid structure; a plurality of the active device regions have a space therebetween; defining the direction of the source region pointing to the drain region as a source-drain direction, wherein the plurality of driving devices are arranged along mutually orthogonal row directions and column directions, and the source-drain direction is perpendicular to the row direction; defining the width of the source region in the direction vertical to the source and drain regions as the width of the source region, and defining the width of the drain region in the direction vertical to the source and drain regions as the width of the drain region; in the same row of the driving devices arranged in the row direction, the width of the source region of the driving device positioned at the two side edges is larger than that of the source region of the driving device positioned at the non-two side edges, and the width of the drain region of the driving device positioned at the two side edges is larger than that of the drain region of the driving device positioned at the non-two side edges. Aiming at the voltage resistance problem generated by a driving device array which integrally bears high voltage in the operations of erasing of a three-dimensional memory and the like, the invention introduces the driving device with wider source and drain region widths in the edge regions at two sides in the row direction, increases the junction area of the device by increasing the source and drain region widths in the edge regions, widens the depletion region, and reduces the electric field, thereby improving the source and drain breakdown voltage of the device; the whole voltage-resistant performance of the driving device array is improved by improving the weak point of the voltage resistance of the driving device array.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A bitline driving structure, comprising:
a first substrate having a first surface and a second surface disposed opposite to each other;
a driving device array formed on a first surface side of the first substrate, the driving device array being formed by arranging a plurality of driving devices;
the driving device comprises an active device region formed in the first substrate, a source region and a drain region formed in the active device region, and a gate structure formed above the active device region; the source region and the drain region are respectively positioned at two sides of the grid structure; a plurality of the active device regions have a space therebetween;
defining the direction of the source region pointing to the drain region as a source-drain direction, wherein the plurality of driving devices are arranged along mutually orthogonal row directions and column directions, and the source-drain direction is perpendicular to the row direction; defining the width of the source region in the direction vertical to the source and drain regions as the width of the source region, and defining the width of the drain region in the direction vertical to the source and drain regions as the width of the drain region; in the same row of the driving devices arranged in the row direction, the width of the source region of the driving device positioned at the two side edges is larger than that of the source region of the driving device positioned at the non-two side edges, and the width of the drain region of the driving device positioned at the two side edges is larger than that of the drain region of the driving device positioned at the non-two side edges.
2. The bit line driving structure of claim 1, wherein: in the same row of the driving devices arranged in the row direction, the widths of the source regions of the driving devices at the two side edges are more than 25% larger than the widths of the source regions of the driving devices at the non-two side edges, and the widths of the drain regions of the driving devices at the two side edges are more than 25% larger than the widths of the drain regions of the driving devices at the non-two side edges.
3. The bit line driving structure of claim 1, wherein: in the same row of the driving devices arranged in the row direction, the width range of the source regions of the driving devices positioned at the two side edges is between 0.65 and 0.75 mu m; the width range of the source region of the driving device located at the non-two side edges is 0.5-0.6 μm.
4. The bit line driving structure of claim 1, wherein: defining the width of the active device region in the direction vertical to the source and drain direction as the width of the active region; in the same driving device, the width of the source region is equal to the width of the active region, and the width of the drain region is smaller than the width of the active region.
5. The bit line driving structure of claim 1, wherein: in the same row of the driving devices arranged in the row direction, the intervals of the adjacent active device regions are equal.
6. The bit line driving structure of claim 1, wherein: in the same row of the driver devices arranged in the row direction, the source-drain directions of the plurality of drivers are the same.
7. The bit line driving structure of claim 6, wherein: and the source-drain directions of the drivers of adjacent rows in the driving device array are opposite.
8. The bit line driving structure of claim 1, wherein: in a row of the driving devices arranged in the row direction, the gate structures of a plurality of the driving devices are connected to each other.
9. The bit line driving structure of claim 1, wherein: further comprising:
a shallow trench isolation structure formed in the first substrate, which isolates the active device regions of a plurality of the driving devices;
a first interconnect layer formed on the first surface of the first substrate, including an interlevel dielectric layer and an electrical connection structure; the interlayer dielectric layer covers the driving device; the electric connection structure penetrates through the interlayer dielectric layer and electrically leads out the driving device.
10. A three-dimensional memory structure, characterized by: the method comprises the following steps:
a second substrate having a third surface and a fourth surface disposed opposite to each other;
a memory array structure formed on a third surface of the second substrate, the memory array structure including a plurality of memory strings and a bit line structure connecting the memory strings;
the bit line driver architecture as claimed in any one of claims 1 to 9, connected to the bit line structure.
11. The three-dimensional memory structure of claim 10, wherein: the memory array structure further comprises an array common source structure, the array common source structure is used for controlling all memory strings in one memory block of the three-dimensional memory structure, and bit line structures connected with the same memory block are connected with the same bit line driving structure.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050528A (en) * | 2011-10-17 | 2013-04-17 | 中芯国际集成电路制造(上海)有限公司 | LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor and manufacturing method thereof |
| US20140286103A1 (en) * | 2013-03-25 | 2014-09-25 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
| US8969945B2 (en) * | 2012-09-05 | 2015-03-03 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
| CN107430878A (en) * | 2015-06-30 | 2017-12-01 | 桑迪士克科技有限责任公司 | Nonvolatile memory system and method |
| CN107507833A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and preparation method thereof |
| CN110870061A (en) * | 2019-10-14 | 2020-03-06 | 长江存储科技有限责任公司 | Structure and method for isolation of bit line drivers for three-dimensional NAND |
| CN111370423A (en) * | 2020-03-16 | 2020-07-03 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
-
2020
- 2020-10-23 CN CN202011145768.XA patent/CN112331652A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050528A (en) * | 2011-10-17 | 2013-04-17 | 中芯国际集成电路制造(上海)有限公司 | LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor and manufacturing method thereof |
| US8969945B2 (en) * | 2012-09-05 | 2015-03-03 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
| US20140286103A1 (en) * | 2013-03-25 | 2014-09-25 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
| CN107430878A (en) * | 2015-06-30 | 2017-12-01 | 桑迪士克科技有限责任公司 | Nonvolatile memory system and method |
| CN107507833A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and preparation method thereof |
| CN110870061A (en) * | 2019-10-14 | 2020-03-06 | 长江存储科技有限责任公司 | Structure and method for isolation of bit line drivers for three-dimensional NAND |
| CN111370423A (en) * | 2020-03-16 | 2020-07-03 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
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