CN112331648A - 半导体部件及其制造方法 - Google Patents
半导体部件及其制造方法 Download PDFInfo
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- CN112331648A CN112331648A CN202011188497.6A CN202011188497A CN112331648A CN 112331648 A CN112331648 A CN 112331648A CN 202011188497 A CN202011188497 A CN 202011188497A CN 112331648 A CN112331648 A CN 112331648A
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- dielectric layer
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- 238000000034 method Methods 0.000 title claims description 85
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- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 1
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- 238000000059 patterning Methods 0.000 description 1
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- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
本发明提供了半导体部件及其制造方法。本发明提供了一种半导体部件,该半导体部件包括衬底、设置在衬底上的界面层、设置在衬底上的第一金属栅极结构和第二金属栅极结构。第一金属栅极结构包括设置在界面层上的第一高k介电层和设置在第一高k介电层上的第一金属栅极层。第二金属栅极结构包括设置在界面层上的第二高k介电层、设置在第二高k介电层上的第三高k介电层,以及设置在第三高k介电层上的第二金属栅极层。
Description
本申请是分案申请,其母案申请的申请号为201510783719.1、申请日为2015年11月16日、发明名称为“半导体部件及其制造方法”。
技术领域
本发明涉及半导体部件及其制造方法。
背景技术
半导体集成电路(IC)产业已经经历了指数增长。在IC材料和设计上的技术进步已经生产了多代IC,其中,每代IC都具有比前一代更小和更复杂的电路。在IC的进化过程中,功能密度(即每个芯片区域的互连器件的数量)得到普遍增加但是几何尺寸(即,使用制造工艺能够生产的最小部件(或线))却减小了。通常这种比例减小工艺以提高生产效率并降低相关成本的方式提供益处。这种比例减小还增加了IC的加工和制造复杂度,为了实现这些进步,在IC加工和制造上也需要类似的发展。
更小的部件尺寸使用诸如鳍式场效应晶体管(FinFET)器件的多栅极器件。FinFET这么命名的原因是栅极形成在从衬底延伸出的“鳍”上并且围绕该“鳍”。正如该术语在本发明中所实施的,FinFET器件是任意基于鳍的多栅极晶体管。FinFET器件可以在在包括沟道区域的鳍的侧面和/或顶部提供栅极时允许缩小器件的栅极宽度。随着技术节点的缩小而实现的另一个进步在于,在一些IC设计中,利用金属栅电极替代了典型的多晶硅栅电极,利用减小的部件尺寸改善了器件性能。形成金属栅电极的一种方法是“栅极最后”或“替换栅极”方法,在“替换栅极”方法中,来形成一个将通常为多晶硅的伪栅极被金属栅极替换。在工艺的后期提供金属栅极可以避免在加工期间功函金属的稳定性问题。
但是,在诸如金属栅极FinFET的器件中提供合适的应力和/或栅极电阻仍有挑战。例如,在栅极上的低应力和/或高栅极电阻可以引起器件性能的降低。
发明内容
为解决现有技术中的问题,根据本发明的一个方面,提供了一种半导体部件,包括:
衬底;
设置在所述衬底上的界面层;
设置在所述衬底上的第一金属栅极结构,包括:
设置在所述界面层上的第一高k介电层;以及
设置在所述第一高k介电层上的第一金属栅极层;以及
设置在所述衬底上的第二金属栅极结构,包括:
设置在所述界面层上的第二高k介电层;
设置在所述第二高k介电层上的第三高k介电层;以及
设置在所述第三高k介电层上的第二金属栅极层。
根据本发明的一个实施例,所述第二高k介电层的介电常数大于或小于所述第三高k介电层的介电常数。
根据本发明的一个实施例,所述第一高k介电层和所述第二高k介电层由相同的材料制成。
根据本发明的一个实施例,其中,所述第一高k介电层和所述第三高k介电层由相同的材料制成。
根据本发明的一个实施例,进一步包括:设置在所述第一高k介电层上的第一功函金属层。
根据本发明的一个实施例,进一步包括:设置在所述第一高k介电层和所述第一功函金属层之间的阻挡层。
根据本发明的一个实施例,进一步包括:设置所述第三高k介电层上的第二功函金属层。
根据本发明的一个实施例,进一步包括:设置在所述第三高k介电层和所述第二功函金属层之间的阻挡层。
根据本发明的又一方面,提供了一种半导体部件,包括:
第一器件,包括:
第一源极;
第一漏极;以及
设置在所述第一源极和所述第一漏极之间的第一金属栅极结构,所述第一金属栅极结构包括:
第一高k介电层;以及
设置在所述第一高k介电层上的第一金属栅极层;
以及
第二器件,包括:
第二源极;
第二漏极;以及
设置在所述第二源极和所述第二漏极之间的第二金属栅极结构,所述第二金属栅极结构包括:
第二高k介电层;
设置在所述第二高k介电层上的第三高k介电层;以及
设置在所述第三高k介电层上的第二金属栅极层。
根据本发明的一个实施例,其中所述第一器件的阈值电压不同于所述第二器件的阈值电压。
根据本发明的一个实施例,其中所述第一器件和所述第二器件为FinFET器件。
根据本发明的一个实施例,进一步包括设置在所述第一高k介电层和所述第一金属栅极层之间的第一功函金属层。
根据本发明的一个实施例,进一步包括设置在所述第三高k介电层和所述第二金属栅极层之间的第二功函金属层。
根据本发明的一个实施例,其中所述第一高k介电层和所述第二高k介电层的材料相同。
根据本发明的一个实施例,其中所述第一高k介电层和所述第三高k介电层的材料相同。
根据本发明的再一方面,提供了一种用于制造半导体部件的方法,包括:
在衬底上形成界面层;
在所述界面层上形成第一高k介电层;
在所述第一高k介电层的一部分上形成第二高k介电层;
在所述第二高k介电层上和所述第一高k介电层的暴露部分上形成阻挡层;以及
在所述阻挡层上形成金属栅极层。
根据本发明的一个实施例,其中所述第一高k介电层的介电常数大于所述第二高k介电层的介电常数。
根据本发明的一个实施例,其中所述第一高k介电层的介电常数小于所述第二高k介电层的介电常数。
根据本发明的一个实施例,进一步包括在所述阻挡层和所述金属栅极层之间形成功函金属层。
根据本发明的一个实施例,所述阻挡层、所述功函金属层和所述金属栅极层形成FinFET器件的金属栅极结构。
附图说明
在结合附图阅读以下详细说明时可以对本发明的各个方面得到最好理解。值得注意的是,根据行业中的标准实践,各种部件没有以比例绘制。实际上,为了清楚地讨论本发明,各种部件的尺寸可以任意增加或减小。
图1是根据本发明一些实施例的FinFET器件实施例的立体图;
图2A至图2G是根据本发明一些实施例的用于说明FinFET器件的形成方法的立体图;
图3是根据本发明一些实施例的半导体部件的截面图;
图4A至图4E是根据本发明一些实施例的制造FinFET器件的不同阶段的示意图;
图5是根据本发明一些实施例的半导体部件的截面图。
具体实施方式
为了实现提供的目标问题的不同部件,以下公开内容提供了许多不同的实施例或实例。下文详述了部件和布置的具体实例以简化本发明。当然,这些仅仅是实例并不旨在限制本发明。例如,在以下描述中第一部件形成在第二部件的上方或之上可以包括第一和第二部件以直接接触形成的实施例,还可以包括在第一和第二部件之间可以形成额外部件,例如第一和第二部件可以不直接接触的实施例。此外,本发明可以在不同实例中重复引用数字和/或符号。这个重复是为了简化和清楚的目的,而其本身并不决定本发明的各个实施例和/或配置之间的关系。
此外,在此可使用诸如“在…之下”、“在…下面”、“下面的”、“在…上面”、以及“上面的”等的空间关系术语,以容易的描述如图中所示的一个元件或部件与另一元件(多个元件)或部件(多个部件)的关系。除图中所示的方位之外,空间关系术语将包括使用或操作中的装置的各种不同的方位。装置可以以其他方式定位(旋转90度或在其他方位),并且通过在此使用的空间关系描述符进行相应地解释。
通常本发明涉及半导体部件,例如FinFET器件和制造FinFET器件的方法或部分器件。随着部件尺寸的持续减小,有一个期望去将栅极氧化层和具有高k栅极介电层和金属栅电极的多晶硅栅电极替换以改善器件性能。一个gate last(或栅替换)方法已经实现了对金属材料的高温处理的关注。但是,在例如金属栅极FinFET的器件中提供合适的压力和/或栅阻力的挑战仍在增加。例如,在栅极上的低压力和/或高栅极阻力可以引起器件性能的降低。因此,有必要在例如金属栅极FinFET的器件中平衡压力和/或栅阻力,这样可以改善栅泄露和/或功能加工。
图1是根据本发明一些实施例的FinFET器件的实施例的立体图。FinFET器件100包括衬底102。在一些实施例中,衬底102包括体型硅衬底。衬底102可以是晶体结构的硅。在其他实施例中,衬底102可以包括诸如锗的其他元素半导体,或者包括诸如碳化硅、砷化镓、砷化铟以及磷化铟的化合物半导体。在一些其他实施例中,衬底102包括绝缘体上硅(SOI)衬底。SOI衬底可以通过使用通过氧注入的分离、晶圆接合和/或其他合适的方法来制造。
FinFET器件100进一步包括从衬底102延伸出的鳍结构104、106(例如,硅鳍)。在一些实施例中,鳍结构104、106可可选地包括锗。鳍结构104、106可以通过使用诸如光刻和蚀刻的合适工艺来制造。在一些实施例中,使用干法蚀刻或等离子处理来从衬底102蚀刻鳍结构104、106。浅沟槽隔离(STI)结构108围绕鳍104、106。STI结构108可以包括任何合适的绝缘材料。应当理解,虽然这里示出了两个鳍结构,但是额外的平行鳍可以以类似的方法形成。
FinFET器件100进一步包括栅极结构110。栅极结构110形成在鳍结构104、106的中央部分上。在一些实施例中,多栅极结构形成在鳍结构的上方。栅极结构110包括栅极介电层和栅电极。应当理解,许多其他层也可以存在,例如覆盖层、界面层、间隔元件和/或其他合适的部件。在一些实施例中,栅极介电层可以包括例如氧化硅的界面层。栅极介电层可以进一步包括诸如氮化硅、氮氧化硅、具有高介电常数(高k)的电介质,和/或它们的组合的其他介电材料。高k介电材料的实例包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金、氧化铪硅、氮氧化铪硅、铪钽氧化物、铪钛氧化物、铪锆氧化物和/或它们的组合。栅电极可以包括多晶硅和/或金属,该金属包括诸如TiN、TaN、NiSi、CoSi、Mo、Cu、W、Al、Co和/或其他合适的导电材料的金属化合物。栅电极可以形成在下文将要解释的栅极最后(gate last)工艺(或栅极替换工艺)中。
鳍结构104、106包括被栅极结构110围绕的沟道区域112。鳍结构104、106可以被掺杂以为N型FinFET(NMOS器件)或P型FinFET(PMOS器件)提供合适的沟道。鳍结构104、106可以使用诸如离子注入、扩散、退火和/或其他合适的工艺的工艺来掺杂。鳍结构104、106包括与FinFET器件100相关的源极区114和漏极区116。源极区114和漏极区116可以包括用于NMOS器件的外延的(外延)硅(Si)或外延碳化硅(SiC),以及用于PMOS器件的外延硅锗(SIGe)或外延锗(Ge)。FinFET器件100可以是包括在微处理器、存储单元(例如,SRAM)和/或其他集成电路中的器件。
图2A至图2F是根据本发明一些实施例的说明FinFET器件形成方法的立体图。在图2A中,提供了半导体衬底。该半导体衬底可以是具有以第一方向延伸的多个鳍结构202的含硅衬底200。此后,形成绝缘层204以填充鳍结构202之间的沟槽的下部部分作为STI。绝缘层204的材料可以但不限于是氧化硅。形成绝缘层204的方法包括在衬底200上沉积绝缘材料覆盖鳍结构202,然后可选地执行平坦化工艺以使绝缘层204平坦,接着执行回蚀刻工艺直到鳍结构202的上部部分暴露。鳍结构202可以包括源极区、漏极区和连接源极区与漏极区的沟道区域。
参考图2B,界面层206共形地形成在衬底200上覆盖鳍结构202。该界面层206包括氧化硅、氮化硅或氮氧化硅。界面层206通过诸如原子层沉积(ALD)工艺、化学气相沉积(CVD)工艺、物理气相沉积(PVD)工艺或溅射沉积工艺的沉积工艺来形成。值得注意的是,界面层206通过沉积工艺而非热氧化处理来形成。由于不会发生热氧化处理导致的硅消耗的情况,所以在形成界面层206的步骤期间鳍102的形状不会变形。正如图2B所示,界面层206沿着每个鳍202的表面共形地形成。在本实施例中,由于通过没有任何硅消耗的沉积工艺来形成界面层206,所以在形成界面层206之后,鳍结构202的形状保持完好。
然后,伪栅极材料层208和掩模层210依次地形成在界面层206上。该伪栅极材料层208包括多晶硅。掩模层210包括氧化硅、氮化硅、氮氧化硅或它们的组合。可以通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺来形成每个伪栅极材料层208和掩模层210。在图2B中,为了说明目的提供了单个掩模层210,但是本发明对此并不限制于此。在另一个实施例中,例如,掩模层210可以是包括下部氮化硅层和上部氧化硅层的多层结构。
参考图2C,对掩模层210、伪栅极材料层208和界面层206图案化以形成包括依次地形成在衬底200上的界面层206、伪栅极材料层208和掩模层210的堆叠结构212。该堆叠结构212以不同于第一方向的第二方向延伸横穿鳍结构202。在一些实施例中,第二方向垂直于第一方向。该图案化步骤包括执行光刻和蚀刻工艺。
参考图2D,在堆叠结构212的旁边形成间隔件214。形成间隔件214的方法包括在衬底200上形成氧化硅层,然后执行各向异性蚀刻工艺以去除该氧化硅层的一部分。接着源极区和漏极区(见图1)在间隔件214的旁边形成在衬底200中。之后,接触蚀刻停止层(CESL)216和层间介电(ILD)层218依次地形成在衬底200上以覆盖堆叠结构212。该CESL 216包括氮化硅。该ILD层218包括氧化硅、氮化硅、氮氧化硅、碳化硅、低介电常数介电材料或它们的组合。CESL 216和ILD层218中的每个可以通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺来形成。之后,分别去除ILD层218的一部分和CESL 216的一部分来暴露堆叠结构212的顶部。
参考图2E,去除了堆叠结构212以在ILD层218中形成沟槽220。该去除步骤包括执行回蚀刻工艺。值得注意的是,在去除堆叠结构212的步骤中,由于将界面层206去除了,所以该界面层206可以作为牺牲层。
参考图2F,另一个界面层222和第一高k介电层224依次形成在至少沟槽220的表面上。该界面层222包括氧化硅、氮化硅或氮氧化硅。该界面层222通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成。值得注意的是,界面层222通过沉积工艺而非热氧化处理来形成。不会发生由于热氧化处理引起的硅消耗,所以在形成界面层222的步骤期间鳍结构202的形状不会变形。界面层222沿着每个鳍202的表面共形地形成。在一些实施例中,由于通过没有任何硅消耗的沉积工艺来形成界面层222,所以在形成界面层222之后,鳍结构202的形状保持完好。
第一高k介电层224包括具有高介电常数的高k材料。该高k材料可以是金属氧化物,例如稀土金属氧化物。该高k材料可以选自由以下材料构成的组:氧化铪(HfO2)、氧化铪硅(HfSiO4)、氮氧化铪硅(HfSiON)、氧化铝(Al2O3)、氧化镧(La2O3)、氧化钽(Ta2O5)、氧化钇(Y2O3)、氧化锆(ZrO2)、钛酸锶(SrTiO3)、硅酸锆(ZrSiO4),锆酸铪(HfZrO4),锶铋钽(SrBi2Ta2O9,SBT),锆钛酸铅(PbZrxTi1-xO3,PZT),以及钛酸锶钡(BaxSr1-xTiO3,BST),其中x在0和1之间。第一高k介电层224通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成。
然后,在衬底200上形成复合金属层236以至少使沟槽220填充满而作为堆叠金属栅极。对于复合金属层236的细节则在图4A至图4E中论述。复合金属层236中的每层可以通过诸如ALD工艺、CVD工艺、PVD工艺、溅射沉积工艺的类似沉积工艺形成。
在一些实施例中,FinFET器件可选地可包括如在图2E之后的图2G所示的位于第一高k介电层224上的第二高k介电层226。该第一高k介电层224和第二高k介电层226由不同的高k材料组成。第二高k介电层226所具有的介电常数可以低于或高于第一高k介电层224所具有的介电常数。该高k第二高k介电层226可以由氧化铪(HfO2)、氧化铪硅(HfSiO4)、氮氧化铪硅(HfSiON)、氧化铝(Al2O3)、氧化镧(La2O3)、氧化钽(Ta2O5)、氧化钇(Y2O3)、氧化锆(ZrO2)、钛酸锶(SrTiO3)、硅酸锆(ZrSiO4),锆酸铪(HfZrO4),锶铋钽(SrBi2Ta2O9,SBT),锆钛酸铅(PbZrxTi1-xO3,PZT),以及钛酸锶钡(BaxSr1-xTiO3,BST)(其中x在0和1之间)组成。第二高k介电层226通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成。
之后,去除位于沟槽220外侧的界面层222、第一高k介电层224、第二高k介电层226(可选地)和复合金属层236。因此得到了FinFET器件,其中,第一高k介电层224和第二高k介电层226(可选地)作为栅极介电层,而复合层236则作为金属栅电极。在图1中显示有接触蚀刻停止层(CESL)216和层间介电(ILD)层218。
参考图3,图3是根据本发明的一些实施例的半导体部件的截面图。在一些实施例中,半导体部件包括具有第一高k介电层224的FinFET器件300a和具有第一高k介电层224和第二高k介电层226的FinFET器件300b。可以根据不同期望将具有单层高k介电层的FinFET器件300a和具有双层高k介电层的FinFET器件300b的数量比例进行设计。例如,在一些实施例中,FinFET器件300a的数量多于FinFET器件300b的数量。然而,FinFET器件300a的数量也可以小于或等于FinFET器件300b的数量。同样的,FinFET器件300a和FinFET器件300b的位置与布置也可以根据不同需求而不同。
FinFET器件300a和FinFET器件300b的比值可以用来调节阈值电压(VT)。例如,与FinFET器件300a的阈值电压相比,将FinFET器件300b的阈值电压向负方向移动。因此,半导体部件的饱和电流(Isat)和漏电流可以通过适当地设计FinFET器件300a与FinFET器件300b的比及其布置来改善。
此外,由于阈值电压可以通过使FinFET器件300b包含有双层高k介电层来调节,所以形成金属栅极的复合金属层236的堆叠层可以减少。形成金属栅极的层的减少可以节约形成半导体部件的成本和制造时间。
图4A至图4E是根据本发明一些实施例的制造FinFET器件300a和FinFET器件300b的不同阶段的视图。更特别地,图4A至图4E是与FinFET器件300a和FinFET器件300b的复合金属层236的制造相关联的,其中,该复合金属层236填充沟槽220(见图2E)而形成。在图4A中,界面层222形成在衬底200上,并且第一高k介电层224形成在界面层222上。该界面层222包括氧化硅、氮化硅或氮氧化硅。该界面层可以通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成。第一高k介电层224包括具有高介电常数的高k材料。高k材料可以是金属氧化物,诸如稀土金属氧化物。第一高k介电层224通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成。
参考图4B,第二高k介电层226形成在第一高k介电层224的一部分上。该第二高k介电层226包括具有高介电常数的高k材料。该高k材料可以是金属氧化物,例如稀土金属氧化物。第一高k介电层224的介电常数可以大于或小于第二高k介电层226的介电常数。第一高k介电层224的厚度可以大于、等于或小于第二高k介电层226的厚度。该第二高k介电层226通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成。
参考图4C,阻挡层240形成在第二高k介电层226和第一高k介电层224暴露的部分上并覆盖第二高k介电层226和第一高k介电层224暴露的部分。该阻挡层240可以是金属层,例如氮化钛(TiN)层。该阻挡层240可以通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成。
阻挡层240还可以通过例如在氨气(NH3)和四氯化钛(TiCl4)之间使用热化学气相沉积反应的渗氮工艺来形成。在一些实施例中,阻挡层240的表面可以进一步的通过渗氮工艺(例如使用氨气)来处理。可选地,在一些实施例中,可以使用后金属退火(PMA)工艺来改善第一高k介电层224、第二高k介电层226和阻挡层240的密度和质量。
在图4D中,功函金属层242形成在阻挡层240上。在一些实施例中,FinFET器件可以是NMOS器件,并且功函金属层242可以由例如Ti、Ag、Al、TiAlMo、Ta、TaN、TiAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr或它们的组合制成。可选地,FinFET器件可以是PMOS器件,并且,功函金属层242可以由例如TiN、W、Ta、Ni、Pt、Ru、Mo、Al、WN或它们的组合制成。功函金属层242可以通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成。
在图4E中,金属栅极层244形成在功函金属层242上。该金属栅极层244可以通过ALD、PVD、CVD或其他工艺沉积在功函金属层242上。该金属栅极层244例如由Al、W、Co、Cu制成。
第一高k介电层224或第一高k介电层224和第二高k介电层226用作FinFET器件300a和FinFET器件300b(见图3)中的栅极介电层。从底部到顶部包括阻挡层240、功函金属层242和功函金属层242的复合金属层236被形成并用作FinFET器件300a和FinFET器件300b中的金属栅极结构。
半导体部件可以利用具有第一高k介电层224的FinFET器件300a和具有第一高k介电层224和第二高k介电层226二者的FinFET器件300b,这样可以通过布置FinFET器件300a和FinFET器件300b来调节半导体部件的性能。因此,可以减少金属栅极层244的厚度和层数。
然而,该概念还可以用在其他有源器件中,例如P沟道场效应晶体管(PFET)、N沟道场效应晶体管(NFET)、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极型晶体管、高电压晶体管、和高频晶体管、和其他的存储单元、以及它们的任何组合和/或其他半导体部件。
图5是根据本发明一些实施例的半导体部件的截面图。半导体部件400包括器件410a和器件410b,其中,器件410a形成在衬底420的第一区域430上,并且器件410b形成在衬底420的第二区域440上。器件410a具有位于衬底420中的源极432和漏极434,以及位于衬底420上的金属栅极结构450。金属栅极结构450从下至上包括界面层452、第一高k介电层454、功函金属层456、以及金属栅极层458,其中第一高k介电层454用作栅极介电层,并且,功函金属层456和金属栅极层458用作金属栅极。器件410b具有位于衬底420中的源极442和漏极444,以及位于衬底420上的金属栅极结构460。金属栅极结构460从下至上包括界面层462、第一高k介电层464、第二高k介电层466、功函金属层468、以及金属栅极层470,其中第一高k介电层464和第二高k介电层466用作栅极介电层,并且,功函金属层468和金属栅极层470用作金属栅极。可以通过相同的工艺形成界面层452和462。在一些实施例中,第一高k介电层454和464由相同的材料以及相同的工艺制成。在一些实施例中,第一高k介电层454和第二高k介电层466由相同的材料以及相同的工艺制成。
正如前文所述,可以通过使用器件410a和器件410b来调节半导体部件的性能。因此,金属栅极层458和470的厚度和层数可以减少。随着金属栅极450和460的制作环节减少,成本和制作时间也减少。
根据以上实施例,由于半导体器件使用具有单层高k介电层的器件,以及具有双层高k介电层的器件,因此,诸如阈值电压、饱和电流和漏电流的性能可以由器件的布置和比例而改善。因此,可以减少金属栅极层的层数和厚度,以及简化金属栅极的制造环节。
本发明的一方面提供了一种半导体部件,其包括衬底、设置在衬底上的界面层、设置在衬底上的第一金属栅极结构和第二金属栅极结构。该第一金属栅极结构包括设置在界面层上的第一高k介电层,和设置在第一高k介电层上的第一金属栅极层。第二金属栅极结构包括设置在界面层上的第二高k介电层、设置在第二高k介电层上的第三k介电层,和设置在第三高k介电层上的第二金属栅极层。
本发明的另一方面提供了一种包括第一器件和第二器件的半导体部件。第一器件包括第一源极、第一漏极,和设置在第一源极和第一漏极之间的第一金属栅极结构。第一金属栅极结构包括第一高k介电层、和设置在第一高k介电层上的第一金属栅极层。第二器件包括第二源极、第二漏极,和设置在第二源极与第二漏极之间的第二金属栅极结构。第二金属栅极结构包括第二高k介电层、设置在第二高k介电层上的第三高k介电层,和设置在第三高k介电层上的第二金属栅极层。
本发明的再一方面提供了一种制造半导体部件的方法。该方法包括在衬底上形成界面层,在界面层上形成第一高k介电层,在第一高k介电层的一部分上形成第二高k介电层,在第二高k介电层以及第一高k介电层的暴露部分上形成阻挡层,以及在阻挡层上形成金属栅极层。
上文概述了几个实施例的部件使得本领域技术人员可以更好的理解本发明的各方面。本领域的技术人员应当意识到他们可以容易地使用本发明作为基础来设计或修改其他的工艺和结构以达到本文介绍的实施例的同样的目的和/或实现本文介绍的实施例的相同的优点。本领域技术人员还应理解,这种等同的构造不背离本发明的精神和范围,并且它们可以做出各种改变、替换和修改而不背离本发明的精神和范围。
Claims (10)
1.一种半导体部件,包括:
衬底;
设置在所述衬底上的界面层;
设置在所述衬底上的第一器件的第一金属栅极结构,所述第一金属栅极结构包括:
设置在所述界面层上的第一高k介电层;以及
直接设置在所述第一高k介电层上的具有多个金属层的第一金属栅电极,所述第一金属栅电极的多个金属层包括直接设置在所述第一高k介电层上的阻挡层和设置在所述阻挡层上方的第一金属栅极层;以及
设置在所述衬底上的第二器件的第二金属栅极结构,所述第二金属栅极结构包括:
设置在所述界面层上的第二高k介电层;
设置在所述第二高k介电层上的第三高k介电层,使得所述第一器件的阈值电压不同于所述第二器件的阈值电压;以及
直接设置在所述第三高k介电层上的具有多个金属层的第二金属栅电极,所述第二金属栅电极的多个金属层包括直接设置在所述第三高k介电层上的所述阻挡层和设置在所述阻挡层上方的第二金属栅极层;
其中,所述第二金属栅电极的多个金属层的数量与所述第一金属栅电极的多个金属层的数量相同,所述第一高k介电层和所述第三高k介电层由不同的材料制成。
2.根据权利要求1所述的半导体部件,其中,所述第二高k介电层的介电常数大于或小于所述第三高k介电层的介电常数。
3.根据权利要求1所述的半导体部件,其中,所述第一高k介电层和所述第二高k介电层由相同的材料制成。
4.根据权利要求1所述的半导体部件,所述第一金属栅电极的多个金属层进一步包括:设置在所述第一高k介电层上的第一功函金属层。
5.根据权利要求4所述的半导体部件,其中,所述阻挡层直接设置在所述第一高k介电层和所述第一功函金属层之间,所述第一金属栅电极直接设置在所述第一功函金属层上。
6.根据权利要求5所述的半导体部件,所述第二金属栅电极的多个金属层进一步包括:设置所述第三高k介电层上的第二功函金属层。
7.根据权利要求6所述的半导体部件,其中,所述阻挡层直接设置在所述第三高k介电层和所述第二功函金属层之间,所述第二金属栅电极直接设置在所述第二功函金属层上。
8.一种半导体部件,包括:
第一器件,包括:
第一源极;
第一漏极;以及
设置在所述第一源极和所述第一漏极之间的第一金属栅极结构,所述第一金属栅极结构包括:
第一高k介电层;以及
设置在所述第一高k介电层上方的具有多个金属层的第一金属栅电极,所述第一金属栅电极的多个金属层包括直接设置在所述第一高k介电层上的阻挡层和设置在所述阻挡层上方的第一金属栅极层;
以及
第二器件,包括:
第二源极;
第二漏极;以及
设置在所述第二源极和所述第二漏极之间的第二金属栅极结构,所述第二金属栅极结构包括:
第二高k介电层;
设置在所述第二高k介电层上的第三高k介电层,使得所述第一器件的阈值电压不同于所述第二器件的阈值电压;以及
直接设置在所述第三高k介电层上的具有多个金属层的第二金属栅电极,所述第二金属栅电极的多个金属层包括直接设置在所述第三高k介电层上的所述阻挡层和设置在所述阻挡层上方的第二金属栅极层;
其中,所述第二金属栅电极的多个金属层的数量与所述第一金属栅电极的多个金属层的数量相同,所述第一高k介电层和所述第三高k介电层由不同的材料制成。
9.根据权利要求8所述的半导体部件,其中,所述第一金属栅电极和所述第二金属栅电极均只具有一个单层的功函金属层。
10.一种用于制造半导体部件的方法,包括:
在衬底上形成界面层;
在所述界面层上形成第一高k介电层,所述第一高k介电层具有形成第一器件的第一金属栅极结构的第一部分和形成第二器件的第二金属栅极结构的第二部分;
在所述第一高k介电层的第一部分上形成第二高k介电层以使得所述第一器件的阈值电压不同于所述第二器件的阈值电压,其中,所述第一高k介电层的所述第一部分位于所述第二高k介电层和所述界面层之间;以及
直接在所述第二高k介电层上和直接在所述第一高k介电层的第二部分上形成具有多个金属层的金属栅电极,其中,形成所述金属栅电极包括:
直接在所述第二高k介电层上和直接在所述第一高k介电层的第二部分上形成阻挡层;以及
直接在所述阻挡层上形成金属栅极层,所述金属栅极层在所述第一部分上方的多个金属层的数量与在所述第二部分上方的多个金属层的数量相同。
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US11031291B2 (en) | 2018-11-28 | 2021-06-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of forming the same |
US11302818B2 (en) * | 2019-09-16 | 2022-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate resistance reduction through low-resistivity conductive layer |
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