CN112309878A - Method for forming welding metal layer on device substrate and packaging method - Google Patents
Method for forming welding metal layer on device substrate and packaging method Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 132
- 239000002184 metal Substances 0.000 title claims abstract description 132
- 239000000758 substrate Substances 0.000 title claims abstract description 94
- 238000000034 method Methods 0.000 title claims abstract description 77
- 238000003466 welding Methods 0.000 title claims abstract description 46
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 230000008569 process Effects 0.000 claims abstract description 40
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 60
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 claims description 58
- 229910000679 solder Inorganic materials 0.000 claims description 58
- 238000004544 sputter deposition Methods 0.000 claims description 27
- 229910052757 nitrogen Inorganic materials 0.000 claims description 23
- 239000010936 titanium Substances 0.000 claims description 16
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 14
- 229910052719 titanium Inorganic materials 0.000 claims description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000007769 metal material Substances 0.000 claims description 10
- 238000005275 alloying Methods 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 239000010953 base metal Substances 0.000 claims 1
- 239000011800 void material Substances 0.000 abstract description 9
- 230000004907 flux Effects 0.000 abstract description 5
- 239000003344 environmental pollutant Substances 0.000 abstract description 2
- 231100000719 pollutant Toxicity 0.000 abstract description 2
- 230000005855 radiation Effects 0.000 abstract 1
- 238000005476 soldering Methods 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000000356 contaminant Substances 0.000 description 10
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- 238000011160 research Methods 0.000 description 5
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- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical group [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention provides a method for forming a welding metal layer on a device substrate and a packaging method. The welding metal layer on the device substrate is optimized to reduce the content of pollutants in the welding metal layer and enable the welding surface of the welding metal layer to be smoother. Therefore, the bonding performance between the welding metal layer and the welding flux in the subsequent welding process can be effectively improved, and the void ratio in the welding flux layer is reduced, so that the heat radiation performance of the packaging structure of the device can be further improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming a solder metal layer on a device substrate, a device substrate having a solder metal layer formed thereon, and a packaging method.
Background
In the semiconductor field, after the component is prepared, the component needs to be packaged to maintain the electrical performance of the component and the like, and the prepared component is further used. In the packaging process, a chip on which a component is formed is generally soldered to a package substrate by using solder, and therefore, the soldering process directly affects the soldering condition between the chip and the package substrate. Specifically, in the soldering process, differences in soldering parameters, tool structures, accessory structures, and the like all affect the form of the solder after melting and solidification at high temperature, and further affect the packaging quality of the device.
The solder is easy to generate holes after being solidified, which is a phenomenon easy to generate in a welding process, and the occurrence of the holes in the solder layer can directly cause the problems of overlarge thermal resistance, poor heat dissipation performance and the like of the whole packaging structure. To solve this technical problem, the art generally aims at research and improvement of the welding process, such as improvement of welding environment, adoption of different welding materials, and the like. However, with the heavy use of high power devices, how to further optimize the packaging process remains an important research direction in the field.
Disclosure of Invention
The invention aims to provide a method for forming a welding metal layer on a device substrate, which is used for optimizing the film quality of the welding metal layer and is beneficial to further improving the problem that cavities are easy to appear in the welding metal layer.
In order to solve the above technical problem, the present invention provides a method for forming a solder metal layer on a device substrate, comprising:
providing a device substrate, and forming a bottom metal layer on the device substrate;
performing a sputtering process of nickel vanadium in a nitrogen environment to form a nickel vanadium layer on the bottom metal layer; and the number of the first and second groups,
and forming a top metal layer on the nickel vanadium layer, wherein the top metal layer is used for welding with a solder.
Optionally, an insulated gate bipolar transistor is formed on the device substrate, and the bottom metal layer is formed on the surface of the device substrate corresponding to the collector region to make ohmic contact with the collector region.
Optionally, the forming method of the bottom metal layer includes:
performing a sputtering process to sputter form a metal material layer on the device substrate; and the number of the first and second groups,
and performing alloying treatment to enable the metal in the metal material layer and the silicon in the device substrate to react on the contact surface of the metal material layer and the silicon in the device substrate to form metal silicide.
Optionally, before forming the nickel vanadium layer, the method further comprises: and performing a sputtering process to sputter a titanium layer on the bottom metal layer.
Optionally, the method for forming the nickel vanadium layer includes: and placing the device substrate in a sputtering chamber, introducing nitrogen into the sputtering chamber, and performing a nickel-vanadium sputtering process.
Optionally, the flow rate of the nitrogen is 3sccm to 10 sccm.
Optionally, the device substrate is a wafer.
Based on the method, the invention also provides a device substrate with the welding metal layer, wherein the welding metal layer comprises a bottom metal layer, a nickel-vanadium layer and a top metal layer which are sequentially formed on the device substrate. Furthermore, nitrogen elements can be doped into the nickel vanadium layer.
In addition, the invention also provides a packaging method, which comprises the following steps:
providing the device substrate and performing a cutting process on the device substrate to divide the device substrate into a plurality of chips; and the number of the first and second groups,
performing a welding process comprising: and soldering the chip to the packaging substrate by using solder in the direction that the soldering metal layer faces the packaging substrate.
According to the method for forming the welding metal layer on the device substrate, the nickel vanadium layer is formed by performing the nickel vanadium sputtering process in the nitrogen environment, so that the content of pollutants in the nickel vanadium layer is reduced, the roughness, the film thickness uniformity and the like of the nickel vanadium layer can be improved, a good film forming surface can be provided for the top metal layer above the nickel vanadium layer, the integral optimization of the welding metal layer formed on the device substrate is realized, the matching degree between the welding metal layer and a welding material in the welding process is improved, and the problem that cavities are easy to appear in the welding material layer can be effectively solved. It should be appreciated that by improving the void phenomenon in the solder layer, the heat dissipation performance of the formed package structure can be further improved, and the device performance in the package structure can be guaranteed.
Furthermore, the method provided by the invention is particularly suitable for the preparation process of the power device. For example, it is easy for an insulated gate bipolar transistor device to generate large power, so heat dissipation of the IGBT device is an important factor affecting its reliability. By applying the method provided by the invention to the preparation process of the IGBT device, the voidage of a solder layer in the finally formed IGBT packaging structure can be effectively reduced, and the heat dissipation performance of the IGBT packaging structure is improved.
It should be noted that the present invention improves the problem of generating voids in the solder layer during the soldering process by optimizing the quality of the solder metal layer on the device substrate. Compared with the idea that the traditional method is mostly improved aiming at the welding process, the invention develops a new method and optimizes the processing process of the device substrate, thereby realizing the improvement of the welding process in another improvement direction.
Drawings
FIG. 1 is a schematic flow chart of forming a solder metal layer on a device substrate in one embodiment of the present invention;
fig. 2 is a schematic structural diagram of a device substrate having a solder metal layer according to an embodiment of the invention.
Wherein the reference numbers are as follows:
100-a device substrate;
200-welding a metal layer;
210-a bottom metal layer;
220-titanium layer;
230-nickel vanadium layer;
240-top metal layer.
Detailed Description
As described in the background, in order to solve the phenomenon of voids in the solder layer, the current research direction and improvement idea are basically directed to the soldering process.
Different from the traditional solution idea, the invention researches the influence of the processing technology of the device substrate on the subsequent welding technology. Specifically, the inventors of the present invention have found, after extensive studies, that the morphology of the solder metal layer on the device substrate also affects the void phenomenon in the solder layer to some extent.
Thus, the present invention provides a method for forming a solder metal layer on a device substrate, and particularly referring to fig. 1, the nickel-vanadium layer in the solder metal layer is formed in a nitrogen atmosphere. The overall shape of the welding metal layer on the device substrate is improved by improving the film quality of the nickel-vanadium layer, so that the welding performance of the welding metal layer and the welding flux is improved in the subsequent welding process, and the contribution degree of the device substrate to the cavity in the welding metal layer is reduced.
The method for forming a solder metal layer on a device substrate, the device substrate with the solder metal layer and a packaging method according to the present invention will be described in further detail with reference to fig. 2 and the specific embodiments. Fig. 2 is a schematic structural diagram of a device substrate having a solder metal layer according to an embodiment of the present invention. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring collectively to fig. 1 and 2, a device substrate 100 is provided. Specifically, the device substrate 100 is, for example, a wafer, and the wafer may further be a silicon wafer. And a plurality of semiconductor devices (not shown), such as power devices, are also formed on the device substrate 100.
In this embodiment, an insulated gate bipolar transistor device (IGBT) is formed on the device substrate 100. Wherein the emitter region and the collector region of the igbt correspond to two opposite surfaces of the device substrate 100, respectively (e.g., the emitter region corresponds to the front surface of the device substrate 100, and the collector region corresponds to the back surface of the device substrate 100). And the surface of the device substrate 100 corresponding to the collector region is a bonding surface, and when a bonding metal layer is subsequently prepared, the bonding metal layer is formed on the surface of the device substrate 100 corresponding to the collector region.
With continued reference to fig. 2, the solder metal layer 200 includes a bottom metal layer 210, a nickel vanadium layer (NiV)230, and a top metal layer 240, which are sequentially stacked on the device substrate.
The bottom metal layer 210 can be used for electrical connection with a semiconductor device in the device substrate 100. For example, the semiconductor device is an IGBT device, and in this case, the bottom metal layer 210 is formed on a surface of a collector region to form an ohmic contact layer electrically connected to the collector region. In this embodiment, the device substrate 100 is a silicon wafer, and therefore, when the bottom metal layer 210 is formed, the bottom metal layer 210 and the silicon wafer may react on a contact surface of the two to form a metal-silicon alloy, so as to reduce contact resistance between the bottom metal layer 210 and a collector region in the silicon wafer.
Specifically, the forming method of the bottom metal layer 210 includes, for example: first, a sputtering process is performed to sputter form a metal material layer on the device substrate 100, the metal material layer including, for example, aluminum (Al); then, an alloying treatment is carried out to make the metal in the metal material layer and the silicon in the silicon wafer react to form a metal silicide on the contact surface of the metal material layer and the silicon wafer. In this embodiment, the metal silicide formed on the contact surface between the underlying metal layer 210 and the silicon wafer is an aluminum-silicon alloy (AlSi), and the mass ratio of silicon in the aluminum-silicon alloy is, for example, 0.7% to 1.5%. Wherein the temperature of the alloying treatment is, for example, 280 to 350 ℃, and the time of the alloying treatment is, for example, 30 to 90 min.
The inventors of the present invention have found that when a sputtering process is performed to deposit the bottom metal layer 210 on the device substrate 100, a certain force is applied to the surface of the device substrate 100, and one of the phenomena that easily occurs at this time is: the contaminants (organic substances, volatile substances, etc.) attached to the device substrate 100 are volatilized, and the volatilized contaminants may further attach to the underlying metal layer 210.
With continued reference to fig. 2, the nickel vanadium layer 230 is formed on the bottom metal layer 210. One of the functions of the nickel vanadium layer 230 is, for example, to block metal diffusion of the underlying metal layer 210, thereby constituting a metal diffusion barrier layer. And, the nickel vanadium layer 230 may also function to include: the adhesion between the multiple metal layers is improved, so that the solder metal layer 200 can be firmly attached to the device substrate 100.
In addition, a titanium layer (Ti)220 is formed between the nickel vanadium layer 230 and the underlying metal layer 210. That is, in this embodiment, the solder metal layer 200 includes a bottom metal layer 210, a titanium layer 220, a nickel-vanadium layer 230, and a top metal layer 240, which are sequentially disposed. Wherein, the bottom metal layer 210 and the titanium layer 220 may have the same thickness, for example, the thickness is 0.08 μm to 0.12 μm; and the thickness of the nickel vanadium layer 230 may be greater than the thickness of the titanium layer 220 and the bottom metal layer 210, for example, the thickness of the nickel vanadium layer 230 is 0.15 μm to 0.25 μm; and the top metal layer 240 has a maximum film thickness relative to the film layer below the top metal layer, for example, the thickness of the top metal layer 240 is 0.7 μm to 0.9 μm.
The titanium layer (Ti)220 may also serve as a barrier to metal diffusion of the underlying metal layer 210, and may also serve as an adhesion layer to further improve adhesion of the solder metal layer 200 to the device substrate 100. It is understood that, in the present embodiment, the titanium layer 220 and the nickel vanadium layer 230 together function as a metal diffusion barrier and improve the adhesion property of the solder metal layer 200.
As shown in fig. 1, the titanium layer 220 may also be formed by a sputtering process. As described above, when the sputtering process is performed to form the bottom metal layer 210, one phenomenon that easily occurs is "the contamination on the device substrate 100 volatilizes and further adheres to the bottom metal layer 210". Also, when performing a sputtering process to deposit titanium layer 220, one phenomenon that is likely to occur is: contaminants on the underlying metal layer 210 volatilize and further adhere to the titanium layer 220. Of course, some of the volatilized contaminants may also be trapped in the metal layer during deposition of the metal layer.
Further, after the titanium layer 220 is formed, a nickel vanadium layer 230 is formed on the titanium layer 220. Specifically, the method for forming the nickel vanadium layer 230 includes: the device substrate 100 is placed in a sputtering chamber, and nitrogen (N) gas is introduced into the sputtering chamber2) Therefore, the sputtering process of nickel vanadium can be performed in a nitrogen environment based on a nickel vanadium target, and at this time, for example, the formed nickel vanadium layer can be doped with nitrogen. The flow rate of the introduced nitrogen is preferably less than 15sccm, for example, the flow rate of the introduced nitrogen is 3sccm to 10 sccm. Of course, the specific flow setting of the nitrogen gas can be correspondingly adjusted according to the actual condition.
In the embodiment, nitrogen can be continuously introduced in the sputtering process, so that on one hand, enough nitrogen is ensured in the sputtering chamber; on the other hand, the continuously introduced nitrogen also has a purging effect on the device substrate 100 during the sputtering process, and at this time, the contaminants attached to the device substrate 100 and the contaminants (organic substances, volatile substances) volatilized during the sputtering process can be taken away in time by the nitrogen, so that the nickel-vanadium layer 230 can be formed on a clean surface, the volatilized contaminants are effectively reduced from being wrapped in the formed nickel-vanadium layer 230 again, and the film quality of the formed nickel-vanadium layer 230 is effectively improved. That is, by reducing the amount of contaminants (particularly volatiles) in the solder metal layer 200, the probability of the contaminants volatilizing to form voids during subsequent soldering is greatly reduced.
After research, the inventors of the present invention also found that the nickel vanadium layer 230 prepared in a nitrogen environment also has better film thickness uniformity and lower roughness, so that the surface flatness of the nickel vanadium layer 230 is better.
The film uniformity and roughness of the nickel vanadium layer formed by sputtering in a nitrogen environment are further verified by using a specific experimental data. Table 1 shows a comparison of properties when preparing a nickel vanadium layer in a nitrogen atmosphere and a nickel vanadium layer in a nitrogen-free atmosphere. The substrate 1 is a substrate for preparing a nickel vanadium layer in a nitrogen-free environment; the substrate 2 is a substrate on which a nickel vanadium layer is prepared in a nitrogen atmosphere.
TABLE 1
As is apparent from the test results shown in table 1, the arithmetic mean roughness (Ra) and the root mean square roughness (Rq) of the nickel vanadium layer formed by introducing nitrogen gas (nitrogen-introduced) were lower than those of the nickel vanadium layer formed without introducing nitrogen gas (nitrogen-free) both in the edge region and in the middle region, that is, the nickel vanadium layer formed by introducing nitrogen gas (nitrogen-introduced) had a smoother surface.
And, with continued reference to table 1, the nickel vanadium layer formed without nitrogen (no nitrogen) also had a large difference in the thickness variation value in the middle region and the thickness variation value in the edge region (difference of 6.8 nm). However, the difference between the thickness fluctuation value of the nickel vanadium layer formed by introducing nitrogen gas (introducing nitrogen gas) in the middle region and the thickness fluctuation value of the edge region was only 2.6 nm. That is, the nickel vanadium layer formed by introducing nitrogen gas (nitrogen introduction) has better film thickness uniformity between the middle region and the edge region thereof.
It should be noted that, by improving the surface roughness of the nickel vanadium layer 230, it is equivalent to providing a better film-forming surface for the top metal layer 240 above the nickel vanadium layer, which is beneficial to improve the film quality of the subsequently formed top metal layer 240, for example, the roughness of the top metal layer 240 can be correspondingly reduced. Therefore, in the soldering process, the solder can be fully contacted with the surface of the top metal layer 240, the soldering performance between the top metal layer 240 and the solder is improved, the pores between the solder and the top metal layer 240 are reduced, and the problem that the solder is easy to generate voids after being solidified is further improved.
Referring specifically to fig. 1 and 2, the top metal layer 240 may also be formed by a sputtering process. And, the top metal layer 240 is used for soldering with solder in a subsequent soldering process.
Further, the material of the top metal layer 240 includes, for example, gold (Au) or silver (Ag), etc. to ensure that the top metal layer 240 can be well adhered to the solder, and because the top metal layer 240 has low activity, the film layer below the top metal layer can be protected from being oxidized.
In this embodiment, the overall film quality of the weld metal layer 200 is improved by optimizing the film quality of the nickel vanadium layer 230, which includes: the content of contaminants (particularly volatiles) in the solder metal layer 200 is reduced; and, the bonding surface of the bonding metal layer 200 (i.e., the surface of the top metal layer 240) is made smoother and smoother. Therefore, the bonding performance between the welding metal layer 200 and the welding flux in the subsequent welding process can be effectively improved, and the phenomenon that the welding flux is easy to generate a cavity after being solidified is reduced.
Specifically, the method of packaging the device includes the following steps, for example.
In a first step, a device substrate having a solder metal layer as described above is provided. At this point, the device substrate remains a complete wafer, and a plurality of semiconductor devices (e.g., IGBT devices) are formed on the wafer.
And a second step of performing a dicing process on the device substrate to divide the device substrate into a plurality of chips. Wherein each die has a solder metal layer on its back side.
A third step of performing a welding process comprising: the chip is soldered to the package substrate with a solder, such as solder paste, in a direction in which the solder metal layer faces the package substrate.
In order to improve the void ratio of the solder layer, the device substrate is often divided into a plurality of chips and then optimized for the soldering process (i.e., corresponding to step three in the present embodiment).
However, in this embodiment, after creatively finding that the film quality of the solder metal layer may affect the void ratio of the solder layer, i.e., before the device substrate is cut, the film quality of the solder metal layer (including the preparation of the nickel vanadium layer in a nitrogen environment) is optimized to achieve the improvement of the void ratio of the solder layer from different angles, so that the void ratio may be much lower than the specification of 0.8% required by the current industrial module, and the heat dissipation performance of the formed package structure is improved.
Particularly, in this embodiment, the flow rate of nitrogen gas is further controlled during the preparation of the nickel vanadium layer, so as to optimize the occurrence of voids in the solder layer. Specifically, the flow rate of the nitrogen gas can be controlled to be less than 15sccm (for example, the flow rate of the introduced nitrogen gas is 3sccm to 10sccm) when the nickel vanadium layer is prepared, so that the nitrogen gas flow rate is prevented from being too large (namely, the flow rate of the nitrogen gas is prevented from being more than 15 sccm). Wherein, when the flow rate of the nitrogen is more than 15sccm, the void ratio of the solder layer can reach 0.4% for example; when the flow rate of nitrogen gas is less than 15sccm, the void ratio of the solder layer can be reduced to about 0.1%, or even less than 0.1%.
It should be understood that the above description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and that any changes and modifications by one of ordinary skill in the art in light of the above disclosure are intended to be included within the scope of the appended claims.
Claims (10)
1. A method of forming a solder metal layer on a device substrate, comprising:
providing a device substrate, and forming a bottom metal layer on the device substrate;
performing a sputtering process of nickel vanadium in a nitrogen environment to form a nickel vanadium layer on the bottom metal layer; and the number of the first and second groups,
and forming a top metal layer on the nickel vanadium layer, wherein the top metal layer is used for welding with a solder.
2. The method of forming a solder metal layer of claim 1, wherein an insulated gate bipolar transistor is formed on the device substrate, a collector region of the insulated gate bipolar transistor is formed on a surface of the device substrate, and the underlying metal layer is formed on the surface of the device substrate corresponding to the collector region to make ohmic contact with the collector region.
3. The method of forming a solder metal layer of claim 2, wherein the method of forming the base metal layer comprises:
performing a sputtering process to sputter form a metal material layer on the device substrate; and the number of the first and second groups,
and performing alloying treatment to enable the metal in the metal material layer and the silicon in the device substrate to react on the contact surface of the metal material layer and the silicon in the device substrate to form metal silicide.
4. The method of forming a weld metal layer of claim 1, further comprising, prior to forming the nickel vanadium layer: and performing a sputtering process to sputter a titanium layer on the bottom metal layer.
5. The method of forming a weld metal layer of claim 1, wherein the method of forming the nickel vanadium layer comprises: and placing the device substrate in a sputtering chamber, introducing nitrogen into the sputtering chamber, and performing a nickel-vanadium sputtering process.
6. The method for forming a solder metal layer according to claim 5, wherein the nitrogen gas is introduced at a flow rate of 3sccm to 10 sccm.
7. The method of forming a solder metal layer according to any of claims 1 to 6, wherein the device substrate is a wafer.
8. A device substrate having a solder metal layer formed using the method of any one of claims 1 to 7, the solder metal layer comprising a bottom metal layer, a nickel vanadium layer and a top metal layer formed in that order on the device substrate.
9. The device substrate of claim 8, wherein the device substrate is a wafer.
10. A method of packaging, comprising:
providing a device substrate having a solder metal layer as claimed in claim 8 or 9;
performing a dicing process on the device substrate to divide into a plurality of chips; and the number of the first and second groups,
and performing a welding process to weld the chip to the packaging substrate by using the welding metal layer in a direction facing the packaging substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011187552.XA CN112309878A (en) | 2020-10-30 | 2020-10-30 | Method for forming welding metal layer on device substrate and packaging method |
Applications Claiming Priority (1)
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