CN112289362A - CCI noise pre-judgment equalization method of Nand memory and related equipment - Google Patents
CCI noise pre-judgment equalization method of Nand memory and related equipment Download PDFInfo
- Publication number
- CN112289362A CN112289362A CN202011167890.7A CN202011167890A CN112289362A CN 112289362 A CN112289362 A CN 112289362A CN 202011167890 A CN202011167890 A CN 202011167890A CN 112289362 A CN112289362 A CN 112289362A
- Authority
- CN
- China
- Prior art keywords
- threshold voltage
- cci
- data
- memory
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 240
- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000013507 mapping Methods 0.000 claims description 39
- 230000008878 coupling Effects 0.000 claims description 10
- 238000010168 coupling process Methods 0.000 claims description 10
- 238000005859 coupling reaction Methods 0.000 claims description 10
- 238000004590 computer program Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 14
- 238000009826 distribution Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Read Only Memory (AREA)
Abstract
The embodiment of the invention discloses a CCI noise pre-judging and balancing method and related equipment of a Nand memory. The method can effectively reduce the CCI interference phenomenon among the storage units, minimize the influence of the CCI interference on the read-write of the Nand memory, and improve the data accuracy of the Nand memory.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a CCI noise pre-judgment equalization method of a Nand memory and related equipment.
Background
The Nand memory is one of Flash memories, belongs to a Non-volatile storage device (Non-volatile memory device), adopts a nonlinear macro-unit mode inside, has the advantages of large capacity, high rewriting speed and the like, and is suitable for storing a large amount of data. As the most common memory chip, Nand memory has been widely used, especially in consumer electronics, and thus, while the memory density is continuously increasing, the cost is more and more sensitive. Since the cost of memory depends on its chip area, Nand memory is more cost effective if more data can be stored in the same area.
The memory cells of Nand memories currently in the mainstream are of three types: the first is Single Level Cell (SLC), and 1 memory Cell (Cell) can store 1bit of data, corresponding to two kinds of storage data, 0 and 1. The second type is Multi Level Cell (MLC), 1 memory Cell can store 2bit data, and can store four kinds of data of 00, 01, 10 and 11. The third type is Triple Level Cell (TLC), one storage unit can store 3 bits of data and can store eight types of data of 000, 001, 010, 011, 100, 101, 110 and 111.
Because parasitic coupling capacitance exists between memory cells of the Nand memory, threshold voltage of the memory cells fluctuates and shifts due to CCI (Cell-to-Cell Interference) caused by the parasitic coupling capacitance, taking a TLC Nand memory as an example, referring to fig. 1, fig. 1 is a TLC threshold voltage statistical histogram after CCI noise Interference can be obtained by a Monte Carlo statistical simulation method, and threshold voltage distributions of adjacent cells have an overlapping region, which may cause a decision error and further cause an error in reading stored data. In the prior art, the above technical problem is solved by using a CCI post-compensation algorithm, which usually improves such fluctuation and offset by Hard-Decision Sensing (Hard-Decision Sensing) or Soft-Decision Sensing (Soft-Decision Sensing). However, in a scenario of severe CCI interference (e.g., after Nand memory has passed through multiple erase, program (P/E) cycles), the CCI post-compensation algorithm does not have good effect in eliminating CCI noise.
Disclosure of Invention
The embodiment of the invention provides a CCI noise pre-judgment balancing method of a Nand memory and related equipment, which can effectively reduce the CCI interference phenomenon among memory units and improve the data accuracy of the Nand memory.
In a first aspect, an embodiment of the present invention provides a CCI noise pre-judgment equalization method for a Nand memory, where the Nand memory includes N pages of data pages, and the method includes:
starting from the data page of the Nth page, the data pages are processed page by page as follows:
judging whether the data page is interfered by CCI;
when the data page is determined to be interfered by CCI, acquiring the threshold voltage of a memory unit interfered by CCI in the data page;
and correcting the threshold voltage according to the threshold voltage variation estimated value corresponding to the storage unit and a first preset mapping relation, wherein the first preset mapping relation is the corresponding relation between a plurality of reference voltages and a storage state of the Nand memory, one storage state corresponds to one type of storage data, and the threshold voltage is corrected into one of the plurality of reference voltages.
Optionally, the determining whether the data page is interfered by CCI includes:
obtaining threshold voltages of memory cells in the data page;
matching the threshold voltage with the first preset mapping relation;
if the threshold voltage is not matched with the reference voltage, the memory cell is a memory cell interfered by CCI, and the data page is a data page interfered by CCI;
if the threshold voltage is matched with the reference voltage, the memory cell is a memory cell which is not interfered by CCI, and the data page is a data page which is not interfered by CCI.
Optionally, the determining whether the data page is interfered by CCI includes:
acquiring incremental voltage values of memory cells in the data page;
matching the incremental voltage value with a second preset mapping relation, wherein the second preset mapping relation is a corresponding relation between standard incremental voltage and the storage state of the Nand memory;
if the incremental voltage value is not matched with the standard incremental voltage, the memory cell is a memory cell interfered by CCI, and the data page is a data page interfered by CCI;
and if the incremental voltage value is matched with the standard incremental voltage, the memory unit is a memory unit which is not interfered by CCI, and the data page is a data page which is not interfered by CCI.
Optionally, the method further comprises:
when the data page is determined not to be interfered by CCI, acquiring storage data corresponding to the threshold voltage of a storage unit in the data page;
judging whether the storage data is consistent with the storage data corresponding to the storage state matched with the incremental voltage value;
and correcting the threshold voltage when the stored data are determined to be inconsistent.
Optionally, the method for predicting the threshold voltage variation prediction value includes:
determining a threshold voltage variation pre-estimated value corresponding to a memory unit interfered by CCI (channel information channel) according to the threshold voltage of the memory unit
The threshold voltage variation pre-estimated value
The estimated formula of (c) is:
wherein the content of the first and second substances,
is the threshold voltage, μ, of the kth memory cell disturbed by CCIeγ is the coupling coefficient between memory cells for the expected value of the threshold voltage of the memory cell in the erased state.
Optionally, the correcting the threshold voltage according to the predicted threshold voltage variation value corresponding to the storage unit and a first preset mapping relationship includes:
determining a first difference value between the threshold voltage of the storage unit and the threshold voltage variation estimated value;
and determining a second difference value between the first difference value and the plurality of reference voltages, and correcting the threshold voltage to the reference voltage corresponding to the minimum second difference value.
Optionally, the correcting the threshold voltage according to the predicted threshold voltage variation value corresponding to the storage unit and a first preset mapping relationship includes:
subtracting the threshold voltage of the storage unit from the threshold voltage variation estimated value to obtain a third difference value; adding the threshold voltage and the threshold voltage variation estimated value to obtain a voltage sum;
respectively matching the third difference, the voltage and the reference voltages, and if the third difference, the voltage and the reference voltages are not matched, subtracting the threshold voltage variation pre-estimated value from the third difference to update the third difference; and adding the voltage sum to the threshold voltage variation pre-estimated value to update the voltage sum until the voltage sum or the third difference matches the reference voltage, and correcting the threshold voltage to the matched reference voltage.
In a second aspect, an embodiment of the present invention provides a CCI noise pre-judging equalization apparatus for Nand memory, where the Nand memory includes N pages of data pages, and the apparatus includes:
the processing module is used for processing the data pages page by page from the Nth page of data pages:
judging whether the data page is interfered by CCI;
when the data page is determined to be interfered by CCI, acquiring the threshold voltage of a memory unit interfered by CCI in the data page;
and correcting the threshold voltage according to the threshold voltage variation estimated value corresponding to the storage unit and a first preset mapping relation, wherein the first preset mapping relation is the corresponding relation between a plurality of reference voltages and a storage state of the Nand memory, one storage state corresponds to one type of storage data, and the threshold voltage is corrected into one of the plurality of reference voltages.
In a third aspect, an embodiment of the present invention provides a storage device, including: a processor and a memory;
the processor is connected to the memory, wherein the memory is used for storing a program code, and the processor is used for calling the program code to execute the CCI noise pre-judging equalization method for Nand memory according to the first aspect.
In a fourth aspect, an embodiment of the present invention provides a computer storage medium storing a computer program, the computer program comprising program instructions that, when executed by a processor, perform the CCI noise pre-judgment equalization method for Nand memory according to the first aspect.
In the embodiment of the invention, for the data page interfered by the CCI, the threshold voltage of the storage unit is corrected according to the threshold voltage variation pre-estimated value of the storage unit interfered by the CCI and the first preset mapping relation, and the threshold voltage is corrected to one of a plurality of reference voltages of the Nand memory. The method can effectively reduce the CCI interference phenomenon among the storage units, minimize the influence of the CCI interference on the read-write of the Nand memory, and improve the data accuracy of the Nand memory.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a prior art statistical histogram of TLC threshold voltages after CCI noise interference;
FIG. 2 is a simplified block diagram of a Nand memory of the prior art;
fig. 3 is a schematic diagram of a prior art floating gate MOSFET structure;
FIG. 4 is a schematic flow chart of a CCI noise pre-judgment equalization method for Nand memory according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an ISPP incremental step pulse programming;
FIG. 6 is a schematic diagram of the data storage state of a memory cell after ISPP programming;
FIG. 7 is a schematic diagram of a data storage state in which memory cells store data in the form of Gray code after ISPP programming;
FIG. 8 is a voltage domain distribution diagram of a data page subjected to CCI interference according to an embodiment of the present invention;
FIG. 9 is a voltage domain distribution diagram of a modified data page according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a storage device according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
It should be understood that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and the drawings, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by the person skilled in the art that the described embodiments of the invention can be combined with other embodiments.
Referring to fig. 2, a simple structure diagram of a Nand memory in the prior art is shown, which is composed of a memory cell array 101, a word line selection unit 102, a bit line selection unit 103, a voltage pump 104, and a control unit 105 of the entire Nand memory chip, wherein the memory cell array 101 includes memory cells (cells) arranged on the basis of word lines and bit lines of each memory cell. Specifically, the memory cells are connected by word lines and bit lines to form pages, and the pages form blocks, and finally the blocks form a memory cell array 101 of the Nand memory. The operation on the Nand memory comprises three parts: an erase operation, a program (write operation), and a read operation, in which the erase operation is performed in units of blocks, and the program and read operations are performed in units of pages.
One memory cell of the Nand memory can store 1bit or more of data, and can be divided into a slcland memory, a mlcnland memory, a tlcnland memory and the like. In Nand memory, a memory cell can be considered as a floating-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Fig. 3 is a structural diagram of a conventional floating gate MOSFET, which includes a gate 20, a source 21, a drain 22, and a P-type silicon semiconductor substrate 23. The mutual connection is as follows: the P-type silicon semiconductor substrate 23 is diffused with two N-type regions, two holes are formed above the N-type regions by etching, and three electrodes are formed on the insulating layer and in the two holes by metallization: the memory cell comprises a gate 20, a source 21 and a drain 22, wherein the source 21 and the drain 22 respectively correspond to two N-type regions, the gate 20 is a word line of the memory cell, and the drain 22 is a bit line of the memory cell. Further, the gate 20 includes a control gate 201, an oxide layer 203, a floating gate 202, and the floating gate 202 stores charges. The amount of charge stored on floating gate 202 in a memory cell determines the threshold voltage of the memory cell.
In the prior art, due to the parasitic coupling capacitance existing between the memory cells of the Nand memory, the threshold voltage of the memory cells fluctuates and deviates due to CCI interference caused by the parasitic coupling capacitance, so that errors occur in data reading and writing of the memory. Therefore, the CCI noise pre-judgment balancing method applied to the Nand memory can effectively reduce the CCI interference phenomenon among the memory units and improve the data reading and writing accuracy of the Nand memory.
Please refer to fig. 4, which is a schematic flow chart of a CCI noise pre-judgment equalization method for Nand memory according to an embodiment of the present invention; the Nand memory comprises N pages of data pages, each memory cell in the data pages stores data, and the CCI noise pre-judging and balancing method of the Nand memory comprises the following steps:
starting from the data page of the Nth page, the data pages are processed page by page as follows:
specifically, the data pages are processed sequentially from the nth page data page up to the 1 st page data page. Firstly, the data page currently processed is judged, and whether the data page is interfered by CCI or not is judged.
specifically, when it is determined that the currently processed data page is interfered by CCI, the threshold voltage of the memory cell in the data page, which is interfered by CCI, is obtained.
Specifically, the threshold voltage of the memory cell interfered by CCI in the data page is corrected, and for the currently processed memory cell, the threshold voltage is corrected according to the corresponding threshold voltage variation prediction value and the first preset mapping relationship, and the threshold voltage is corrected to one of the plurality of reference voltages in the first preset mapping relationship.
The first preset mapping relation is the corresponding relation between a plurality of reference voltages of the Nand memory and the storage state, and the number and specific numerical values of the corresponding reference voltages of the Nand memories with different structures are different. For example, for SLC Nand memory, it has 2 reference voltages because it has 2 memory states (1 or 0). The MLC Nand memory has 4 memory states (00, 01, 10 or 11), and therefore, it has 4 reference voltages. As such, the TLC Nand memory has 8 memory states with 8 reference voltages. It can be seen that each reference voltage corresponds to a storage state of the memory (in other words, a reference voltage corresponds to a storage data of the memory), and the first preset mapping relationship can be obtained according to a one-to-one correspondence relationship between the reference voltage and the storage state.
It should be noted that "correcting" the threshold voltage in this application is to be understood as correcting the output data of the memory cell so that the data can be correctly read and written when the memory cell is read and written, and the threshold voltage of the memory cell is not controlled. For example, the output data of the original memory cell is 111, but after correction, it can be determined that the output data of the memory cell should be 110.
By using the method of the embodiment of the invention, the CCI interference phenomenon among the storage units can be effectively reduced, the influence of the CCI interference on the read-write of the Nand memory is reduced to the minimum, and the data accuracy of the Nand memory is improved. Specifically, when reading the storage data of the Nand memory, the method of the embodiment of the invention is firstly used for correcting the storage data so that the read storage data is accurate data. Likewise, after data is written to Nand memory, the stored data can be corrected using the method of embodiments of the present invention so that the written data is correct.
It is worth pointing out that sources of CCI interference mainly include the incremental voltage value Δ Vpp of the memory cell (the difference between the voltage of the memory cell from the erase state and the voltage corresponding to the stored data), floating gate coupling, bit line-bit line coupling, source offset error, BPD, program and read interference, etc., and the present application proposes to optimize the impact of CCI interference on data reading and writing from the main interference source Δ Vpp.
FIG. 5 is a schematic diagram of an ISPP incremental step pulse programming, as shown in FIG. 5; the erasing operation and the programming operation of the Nand memory are both controlled (injecting electrons to the floating gate in the memory cell) by ISPP (incremental step pulse program). As can be seen from fig. 5, Δ Vpp is a range (within which corresponding operations can be performed, which is not a fixed value, but the range is relatively fixed), and the values written into the memory cells are different from one another. As shown in fig. 6, it can be seen from fig. 6 that, for the TLCNand memory as an example, each data state in the memory cell corresponds to a voltage K when it is read out later, and there is a range corresponding to Δ Vpp, and the read-out voltages corresponding to the respective data Di (e.g., 000, 001,.. and 111) are represented as Ki (K0,.. and K7), which are not fixed values, but the ranges are relatively fixed. Ki is the reference voltage mentioned above. Therefore, for a Nand memory, after the voltage K corresponding to each kind of stored data is determined, the corresponding Δ Vpp can be obtained, and then the mapping relationship between Δ Vppi-Ki-Di can be obtained, that is, the first preset mapping relationship can be obtained: the corresponding relation between a plurality of reference voltages K of the Nand memory and the storage state D, and a second preset mapping relation: and the standard incremental voltage delta Vpp corresponds to the storage state D of the Nand memory.
In view of CCI interference and preventing error code in reading between data in the memory unit, in practice, the storage sequence of data in the memory unit is in the form of gray code, as shown in fig. 7.
In one possible embodiment, step 401 comprises:
specifically, the threshold voltages of all memory cells of the currently processed data page are obtained.
Specifically, if a threshold voltage that does not match the reference voltage in the first preset mapping relationship exists in the current data page, it indicates that a memory cell interfered by CCI exists in the current data page, and the data page is a data page interfered by CCI, at this time, the following processing operation of correcting the threshold voltage needs to be performed on the data page. On the contrary, if all the threshold voltages of the current data page are matched with the reference voltage in the first preset mapping relationship, it indicates that no memory cell interfered by CCI exists in the current data page, and the data page is a data page not interfered by CCI.
In another possible embodiment, step 401 comprises:
specifically, after the programming operation is performed on the memory cells, the voltages of the erased states of the memory cells are known, and therefore, after the threshold voltages of the data page are read, the incremental voltage value corresponding to each memory cell can be obtained.
Specifically, the increment voltage value obtained in step 21 is compared with the standard increment voltage in the second preset mapping relationship, and if the increment voltage value that does not match the standard increment voltage exists in the current data page, it indicates that the memory cell interfered by the CCI exists in the current data page, and the data page is a data page interfered by the CCI. On the contrary, if all the incremental voltage values of the current data page are matched with the standard incremental voltage, it indicates that there is no memory cell interfered by CCI in the current data page, and the data page is a data page not interfered by CCI, and at this time, it can directly jump in to determine whether the next data page is interfered by CCI.
The threshold voltage or the incremental voltage value of the memory Cell is used to determine whether the memory Cell is interfered by CCI, and for the current data page, the number of the memory cells interfered by CCI can be obtained, taking the TLCNand memory as an example, at this time, a voltage domain distribution diagram of all the memory cells on the data page as shown in fig. 8 can be obtained, which shows the threshold voltage distribution of all the cells on a certain data page, and also represents whether there is a cross (interference) under the influence of various voltages. When a page of data is operated, the amount of data (000, 111) in each Cell is affected by the operating voltage (erase voltage, program voltage, read voltage, etc.). As m points on the waveform, when Vth ═ v, the number of affected 111 data in the Cell is m. After the data page is processed by the method of the embodiment of the invention, a new threshold voltage distribution diagram as shown in fig. 9 can be obtained.
In one possible embodiment, the method for estimating the threshold voltage variation estimation value comprises the following steps:
determining a threshold voltage variation prediction value corresponding to a memory cell according to the threshold voltage of the memory cell interfered by CCI
Threshold voltage variation prediction value
The estimated formula of (c) is:
wherein the content of the first and second substances,
is the threshold voltage, μ, of the kth memory cell disturbed by CCIeγ is the coupling coefficient between memory cells, which is the expected value of the threshold voltage of a memory cell in the erased state.
Specifically, after a certain memory cell is programmed, its threshold voltage can be obtained, and then according to the estimated μeEstimating a threshold voltage variation affected by CCI for the memory cell by using the estimation formula to obtain the corresponding memory cellIs estimated. The threshold voltage variation prediction values may be different for different memory cells. The threshold voltage variation prediction value can be estimated before the threshold voltage of the interfered memory cell is corrected.
In one possible embodiment, step 403 includes:
step A1, determining a first difference value between the threshold voltage of the memory cell and the predicted value of the threshold voltage variation;
specifically, when the threshold voltage of the current memory cell interfered by CCI is corrected, a first difference between the threshold voltage and the predicted threshold voltage variation corresponding to the memory cell, that is, a first difference between the predicted threshold voltage variation and the current threshold voltage is calculated according to the current threshold voltage
And step B1, determining a second difference between the first difference and the plurality of reference voltages, and correcting the threshold voltage to the reference voltage corresponding to the minimum second difference.
Specifically, a second difference between the current threshold voltage and the plurality of reference voltages is determined according to the first difference, and the current threshold voltage is corrected to the reference voltage with the minimum second difference, namely, the disturbed threshold voltage is corrected to one of the plurality of reference voltages of the Nand memory.
In another possible embodiment, step 403 includes:
step A2 is to subtract the threshold voltage of the memory cell from the predicted threshold voltage variation to obtain a third difference; adding the threshold voltage and the threshold voltage variation estimated value to obtain a voltage sum;
specifically, for the threshold voltage that needs to be corrected currently, the subtraction and the addition are performed according to the corresponding threshold voltage variation prediction values, i.e., the third difference is
A sum of voltages of
Step B2, matching the third difference, the voltage and the reference voltages respectively, if the third difference and the voltage are not matched, subtracting the predicted value of the threshold voltage variation from the third difference to update the third difference; and adding the voltage sum to a threshold voltage variation estimated value to update the voltage sum until the voltage sum or the third difference matches the reference voltage, and correcting the threshold voltage to the matched reference voltage.
Specifically, the third difference, the voltage sum and a plurality of reference voltages of the Nand memory are respectively matched, whether the matching exists is determined, if the third difference and the voltage sum do not match the reference voltages, a threshold voltage change amount pre-estimated value is continuously subtracted from the third difference, the difference is used as a new third difference, the voltage sum is continuously added with a threshold voltage change amount pre-estimated value, the sum is used as a new voltage sum, the new third difference, the new voltage sum and the reference voltages are continuously matched until the third difference or the voltage sum matches the reference voltages, and the threshold voltages are corrected to the matched reference voltages. Briefly, the threshold voltage variation estimation is performed by N times of addition and subtraction
The threshold voltage can be finally approximated to a correct threshold voltage (i.e., a reference voltage), so as to predict a correct output value (000.,. 111) of the memory cell.
By using the two correction methods provided above, the threshold voltage interfered by the CCI can be corrected to ensure correct reading and writing of the data page.
Further, after a certain data page is corrected, the correspondence relationship between the threshold voltage Vth before correction and the data D after correction may be recorded. By using the correspondence, when the subsequent data page is corrected, if the threshold voltage before correction is V1 and the corresponding corrected data is D1, and if the threshold voltage V2 to be corrected of the subsequent data page satisfies V2-V1, the data of the storage unit of V2 can be directly corrected to D1, so that the correction operation process is omitted, and the optimization time and the hardware resources are saved.
In one possible embodiment, the CCI noise pre-decision equalization method further includes:
step C, when the data page is determined not to be interfered by the CCI, acquiring storage data corresponding to the threshold voltage of the storage unit in the data page;
specifically, when the threshold voltage or the incremental voltage value of the memory cell is used to determine that the data page is not interfered by CCI, that is, the threshold voltage or the incremental voltage value of the memory cell may be matched to a reference voltage at this time, it may be preliminarily determined that the data output by the data page is correct, and in order to further ensure the correctness of the output data of the data page, the stored data of the data page may be determined, and the stored data of the data page may be first obtained from the register.
Step D, judging whether the storage data is consistent with the storage data corresponding to the storage state matched with the threshold voltage or the incremental voltage value; and when the stored data are determined to be inconsistent, correcting the threshold voltage.
Specifically, next, according to the step C, the storage data is obtained, and the storage data corresponding to the storage state matched with the threshold voltage or the incremental voltage value is compared to determine whether the two are consistent, and when the two are the same, it can be finally determined that the output data of the data page is correct. In contrast, when the two are not consistent, the threshold voltage of the data page needs to be corrected, i.e., the steps a1 and B1 are performed, or the steps a2 and B2 are performed.
In a possible embodiment, similarly, after correcting the threshold voltage of the memory cell of a certain data page, in order to ensure that the output data of the data page is correct, it may be determined whether the stored data of each memory cell is correct, that is, the stored data of the memory cell is read from the register and compared with the stored data corresponding to the reference voltage matched during correction, when the two are the same, it may be determined that the data page is successfully corrected, and if the two are different, the correction operation needs to be performed again until the two are the same.
The CCI noise pre-judgment equalization algorithm provided by the embodiment of the invention can effectively reduce the Cell threshold voltage crossing phenomenon of adjacent states, is beneficial to reducing the original bit error rate and enhancing the reliability of the Nand memory.
Based on the above description of the embodiment of the CCI noise pre-judging equalization method of the Nand memory, the embodiment of the present invention further discloses a CCI noise pre-judging equalization apparatus of the Nand memory, wherein the Nand memory includes N pages of data pages, and the CCI noise pre-judging equalization apparatus includes:
the processing module is used for processing the data pages page by page from the Nth page of data pages:
the first submodule is used for judging whether the data page is interfered by CCI;
the second submodule is used for acquiring the threshold voltage of the memory unit interfered by the CCI in the data page when the data page is determined to be interfered by the CCI;
and the third submodule is used for correcting the threshold voltage according to the threshold voltage variation estimated value corresponding to the storage unit and a first preset mapping relation, wherein the first preset mapping relation is the corresponding relation between a plurality of reference voltages and a storage state of the Nand memory, one storage state corresponds to one type of storage data, and the threshold voltage is corrected into one of the plurality of reference voltages.
In one possible embodiment, the first submodule is specifically configured to:
obtaining threshold voltages of memory cells in a data page;
matching the threshold voltage with a first preset mapping relation;
if the threshold voltage is not matched with the reference voltage, the memory cell is a memory cell interfered by CCI, and the data page is a data page interfered by CCI;
if the threshold voltage is matched with the reference voltage, the memory cell is a memory cell which is not interfered by CCI, and the data page is a data page which is not interfered by CCI.
In another possible embodiment, the first submodule is specifically configured to:
acquiring incremental voltage values of memory cells in a data page;
matching the incremental voltage value with a second preset mapping relation, wherein the second preset mapping relation is a corresponding relation between the standard incremental voltage and the storage state of the Nand memory;
if the incremental voltage value is not matched with the standard incremental voltage, the storage unit is a storage unit interfered by CCI, and the data page is a data page interfered by CCI;
if the incremental voltage value is matched with the standard incremental voltage, the memory cell is a memory cell which is not interfered by CCI, and the data page is a data page which is not interfered by CCI.
In one possible embodiment, the method for estimating the threshold voltage variation estimation value comprises the following steps:
determining a threshold voltage variation prediction value corresponding to a memory cell according to the threshold voltage of the memory cell interfered by CCI
Threshold voltage variation prediction value
The estimated formula of (c) is:
wherein the content of the first and second substances,
is the threshold voltage, μ, of the kth memory cell disturbed by CCIeγ is the coupling coefficient between memory cells, which is the expected value of the threshold voltage of a memory cell in the erased state.
In a possible embodiment, the third submodule is specifically configured to:
determining a first difference value between the threshold voltage of the storage unit and the threshold voltage variation estimated value;
and determining a second difference between the first difference and the plurality of reference voltages, and correcting the threshold voltage to the reference voltage corresponding to the minimum second difference.
In another possible embodiment, the third submodule is specifically configured to:
subtracting the threshold voltage of the storage unit from the threshold voltage variation estimated value to obtain a third difference value; adding the threshold voltage and the threshold voltage variation estimated value to obtain a voltage sum;
respectively matching the third difference value, the voltage and the plurality of reference voltages, and if the third difference value and the voltage are not matched, subtracting a threshold voltage variation estimated value from the third difference value to update the third difference value; and adding the voltage sum to a threshold voltage variation estimated value to update the voltage sum until the voltage sum or the third difference matches the reference voltage, and correcting the threshold voltage to the matched reference voltage.
In one possible embodiment, the processing module further comprises:
the fourth submodule is used for acquiring storage data corresponding to the threshold voltage of the storage unit in the data page when the data page is determined not to be interfered by the CCI;
the fifth submodule is used for judging whether the storage data are consistent with the storage data corresponding to the storage state matched with the incremental voltage value; and when the stored data are determined to be inconsistent, correcting the threshold voltage.
It should be noted that, for a specific implementation manner of the CCI noise pre-judging equalization apparatus of the Nand memory, reference may be made to the above description of the CCI noise pre-judging equalization method of the Nand memory, and details are not repeated here. Each unit or module in the CCI noise pre-judgment equalization device of the Nand memory may be respectively or completely combined into one or several other units or modules to form the apparatus, or some unit(s) or module(s) thereof may be further split into a plurality of units or modules with smaller functions to form the apparatus, which may implement the same operation without affecting the implementation of the technical effect of the embodiment of the present invention. The above units or modules are divided based on logic functions, and in practical applications, the functions of one unit (or module) may also be implemented by a plurality of units (or modules), or the functions of a plurality of units (or modules) may be implemented by one unit (or module).
Based on the description of the above method embodiment, an embodiment of the present invention further provides a storage device. Fig. 10 is a schematic structural diagram of a memory device according to an embodiment of the present invention. The storage device 10 may include: processor 11, DRAM12, and memory 13. The memory 13 may be a non-volatile memory (non-volatile memory), such as an SSD. The memory 13 may alternatively be at least one memory device, such as a Nand memory, located remotely from the processor 11. As shown in fig. 10, the memory 13, which is a kind of computer storage medium, may include therein an operating system, and a device control application program.
In the memory device 10 shown in fig. 10, the processor 11 may be configured to call a device control application program stored in the memory 13 to implement the steps of the CCI noise pre-judging equalization method for Nand memory described above.
It should be understood that the memory device 10 described in the embodiment of the present invention can perform the CCI noise pre-judging equalization method for Nand memory described above, and will not be described herein again. In addition, the beneficial effects of the same method are not described in detail.
Further, here, it is to be noted that: an embodiment of the present invention further provides a computer storage medium, where a computer program executed by the CCI noise pre-judging and equalizing apparatus for Nand memory is stored in the computer storage medium, and the computer program includes program instructions, and when the processor executes the program instructions, the description of the CCI noise pre-judging and equalizing method for Nand memory can be executed, so that details are not repeated here. In addition, the beneficial effects of the same method are not described in detail. For technical details not disclosed in the embodiments of the computer storage medium to which the present invention relates, reference is made to the description of the method embodiments of the present invention.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium can be a SLCNand memory, a MLCNand memory, a TLCNand memory, a QLC Nand memory and the like.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.
Claims (10)
1. A CCI noise pre-judging equalization method of Nand memory, which is characterized in that the Nand memory comprises N pages of data, and the method comprises the following steps:
starting from the data page of the Nth page, the data pages are processed page by page as follows:
judging whether the data page is interfered by CCI;
when the data page is determined to be interfered by CCI, acquiring the threshold voltage of a memory unit interfered by CCI in the data page;
and correcting the threshold voltage according to the threshold voltage variation estimated value corresponding to the storage unit and a first preset mapping relation, wherein the first preset mapping relation is the corresponding relation between a plurality of reference voltages and a storage state of the Nand memory, one storage state corresponds to one type of storage data, and the threshold voltage is corrected into one of the plurality of reference voltages.
2. The method of claim 1, wherein the determining whether the data page is interfered by CCI comprises:
obtaining threshold voltages of memory cells in the data page;
matching the threshold voltage with the first preset mapping relation;
if the threshold voltage is not matched with the reference voltage, the memory cell is a memory cell interfered by CCI, and the data page is a data page interfered by CCI;
if the threshold voltage is matched with the reference voltage, the memory cell is a memory cell which is not interfered by CCI, and the data page is a data page which is not interfered by CCI.
3. The method of claim 1, wherein the determining whether the data page is interfered by CCI comprises:
acquiring incremental voltage values of memory cells in the data page;
matching the incremental voltage value with a second preset mapping relation, wherein the second preset mapping relation is a corresponding relation between standard incremental voltage and the storage state of the Nand memory;
if the incremental voltage value is not matched with the standard incremental voltage, the memory cell is a memory cell interfered by CCI, and the data page is a data page interfered by CCI;
and if the incremental voltage value is matched with the standard incremental voltage, the memory unit is a memory unit which is not interfered by CCI, and the data page is a data page which is not interfered by CCI.
4. The method of claim 3, further comprising:
when the data page is determined not to be interfered by CCI, acquiring storage data corresponding to the threshold voltage of a storage unit in the data page;
judging whether the storage data is consistent with the storage data corresponding to the storage state matched with the incremental voltage value;
and correcting the threshold voltage when the stored data are determined to be inconsistent.
5. The method according to any one of claims 1 to 4, wherein the method for estimating the estimated threshold voltage variation comprises:
determining a threshold voltage variation pre-estimated value corresponding to a memory unit interfered by CCI (channel information channel) according to the threshold voltage of the memory unit
The threshold voltage variation pre-estimated value
The estimated formula of (c) is:
wherein the content of the first and second substances,
is the threshold voltage, μ, of the kth memory cell disturbed by CCIeγ is the coupling coefficient between memory cells for the expected value of the threshold voltage of the memory cell in the erased state.
6. The method according to any one of claims 1 to 4, wherein the correcting the threshold voltage according to the predicted threshold voltage variation value corresponding to the storage unit and the first predetermined mapping relationship comprises:
determining a first difference value between the threshold voltage of the storage unit and the threshold voltage variation estimated value;
and determining a second difference value between the first difference value and the plurality of reference voltages, and correcting the threshold voltage to the reference voltage corresponding to the minimum second difference value.
7. The method according to any one of claims 1 to 4, wherein the correcting the threshold voltage according to the predicted threshold voltage variation value corresponding to the storage unit and the first predetermined mapping relationship comprises:
subtracting the threshold voltage of the storage unit from the threshold voltage variation estimated value to obtain a third difference value; adding the threshold voltage and the threshold voltage variation estimated value to obtain a voltage sum;
respectively matching the third difference, the voltage and the reference voltages, and if the third difference, the voltage and the reference voltages are not matched, subtracting the threshold voltage variation pre-estimated value from the third difference to update the third difference; and adding the voltage sum to the threshold voltage variation pre-estimated value to update the voltage sum until the voltage sum or the third difference matches the reference voltage, and correcting the threshold voltage to the matched reference voltage.
8. An apparatus for CCI noise pre-judge equalization in Nand memory, wherein the Nand memory comprises N pages of data, the apparatus comprising:
the processing module is used for processing the data pages page by page from the Nth page of data pages:
judging whether the data page is interfered by CCI;
when the data page is determined to be interfered by CCI, acquiring the threshold voltage of a memory unit interfered by CCI in the data page;
and correcting the threshold voltage according to the threshold voltage variation estimated value corresponding to the storage unit and a first preset mapping relation, wherein the first preset mapping relation is the corresponding relation between a plurality of reference voltages and a storage state of the Nand memory, one storage state corresponds to one type of storage data, and the threshold voltage is corrected into one of the plurality of reference voltages.
9. A storage device, comprising: a processor and a memory;
the processor is connected with a memory, wherein the memory is used for storing program codes, and the processor is used for calling the program codes to execute the CCI noise prejudging and equalizing method of the Nand memory according to any one of claims 1-7.
10. A computer storage medium, characterized in that it stores a computer program comprising program instructions which, when executed by a processor, perform the CCI noise prejudgment equalization method for Nand memory as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011167890.7A CN112289362B (en) | 2020-10-27 | 2020-10-27 | CCI noise pre-judging and balancing method of Nand memory and related equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011167890.7A CN112289362B (en) | 2020-10-27 | 2020-10-27 | CCI noise pre-judging and balancing method of Nand memory and related equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112289362A true CN112289362A (en) | 2021-01-29 |
| CN112289362B CN112289362B (en) | 2024-03-15 |
Family
ID=74372587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011167890.7A Active CN112289362B (en) | 2020-10-27 | 2020-10-27 | CCI noise pre-judging and balancing method of Nand memory and related equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112289362B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113129994A (en) * | 2021-03-29 | 2021-07-16 | 深圳市国微电子有限公司 | Storage system performance adjusting method and storage system |
| CN114356221A (en) * | 2021-12-07 | 2022-04-15 | 广州致存科技有限责任公司 | Data writing method, storage device and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420012A (en) * | 2010-09-27 | 2012-04-18 | 旺宏电子股份有限公司 | Device and method for detecting interference storage unit in semiconductor storage device |
| CN103226974A (en) * | 2011-12-15 | 2013-07-31 | 马维尔国际贸易有限公司 | Inter-cell interference cancellation |
| CN106205720A (en) * | 2016-07-06 | 2016-12-07 | 记忆科技(深圳)有限公司 | A kind of method recovering Nand Flash wrong data |
| CN109032514A (en) * | 2018-07-17 | 2018-12-18 | 广东工业大学 | A kind of method for reading data, device, equipment and readable storage medium storing program for executing |
| CN110111829A (en) * | 2019-05-13 | 2019-08-09 | 广东工业大学 | A kind of method, apparatus and medium of flash-memory channels correction |
| US20200327947A1 (en) * | 2019-04-15 | 2020-10-15 | SK Hynix Inc. | Memory system for interference compensation and operating method thereof |
-
2020
- 2020-10-27 CN CN202011167890.7A patent/CN112289362B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420012A (en) * | 2010-09-27 | 2012-04-18 | 旺宏电子股份有限公司 | Device and method for detecting interference storage unit in semiconductor storage device |
| CN103226974A (en) * | 2011-12-15 | 2013-07-31 | 马维尔国际贸易有限公司 | Inter-cell interference cancellation |
| CN106205720A (en) * | 2016-07-06 | 2016-12-07 | 记忆科技(深圳)有限公司 | A kind of method recovering Nand Flash wrong data |
| CN109032514A (en) * | 2018-07-17 | 2018-12-18 | 广东工业大学 | A kind of method for reading data, device, equipment and readable storage medium storing program for executing |
| US20200327947A1 (en) * | 2019-04-15 | 2020-10-15 | SK Hynix Inc. | Memory system for interference compensation and operating method thereof |
| CN110111829A (en) * | 2019-05-13 | 2019-08-09 | 广东工业大学 | A kind of method, apparatus and medium of flash-memory channels correction |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113129994A (en) * | 2021-03-29 | 2021-07-16 | 深圳市国微电子有限公司 | Storage system performance adjusting method and storage system |
| CN113129994B (en) * | 2021-03-29 | 2023-11-28 | 深圳市国微电子有限公司 | Storage system performance adjusting method and storage system |
| CN114356221A (en) * | 2021-12-07 | 2022-04-15 | 广州致存科技有限责任公司 | Data writing method, storage device and storage medium |
| CN114356221B (en) * | 2021-12-07 | 2023-10-20 | 广州致存科技有限责任公司 | Data writing method, storage device and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112289362B (en) | 2024-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8830762B2 (en) | Methods, devices, and systems for dealing with threshold voltage change in memory devices | |
| US8189387B2 (en) | Flash memory with multi-bit read | |
| US7643348B2 (en) | Predictive programming in non-volatile memory | |
| US6108241A (en) | Leakage detection in flash memory cell | |
| US6493270B2 (en) | Leakage detection in programming algorithm for a flash memory device | |
| US7802132B2 (en) | Technique to improve and extend endurance and reliability of multi-level memory cells in a memory device | |
| US7567455B2 (en) | Method and system for programming non-volatile memory cells based on programming of proximate memory cells | |
| US10141060B1 (en) | Memory system | |
| US7551483B2 (en) | Non-volatile memory with predictive programming | |
| US7881106B2 (en) | Nonvolatile semiconductor memory device | |
| US8861269B2 (en) | Internal data load for non-volatile storage | |
| US20150016186A1 (en) | Methods and apparatuses for determining threshold voltage shift | |
| CN112289362B (en) | CCI noise pre-judging and balancing method of Nand memory and related equipment | |
| KR101199131B1 (en) | Data transfer and programming in a memory device | |
| TWI719653B (en) | Apparatus and methods for determining an expected data age of memory cells | |
| US20120269003A1 (en) | Data decision method and memory | |
| CN110908825B (en) | Data reading method and device, storage equipment and storage medium | |
| US7391672B1 (en) | Sequential memory and accessing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |