CN110908825B - Data reading method and device, storage equipment and storage medium - Google Patents
Data reading method and device, storage equipment and storage medium Download PDFInfo
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- CN110908825B CN110908825B CN201811080692.XA CN201811080692A CN110908825B CN 110908825 B CN110908825 B CN 110908825B CN 201811080692 A CN201811080692 A CN 201811080692A CN 110908825 B CN110908825 B CN 110908825B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a data reading method, a data reading device, storage equipment and a storage medium. The method may include: receiving an input reading instruction, wherein the reading instruction carries a reading address; acquiring preset voltages of all word lines of a target memory cell to be read according to the read address; reading data of the target memory cell according to preset voltages of each word line of the target memory cell; obtaining an error unit of the read error in the target storage unit; and updating the preset voltage of each word line of the error unit according to the type of the error unit. The invention updates the preset voltage of each word line of the error unit through the error type of the error unit, thus, when reading next time, reading the data of the error unit according to the updated preset voltage, solving the problem of reading errors caused by the error preset voltage, and realizing the repair of two types of error bits which cannot be actually repaired in the memory in the prior art.
Description
Technical Field
Embodiments of the present invention relate to data processing technologies, and in particular, to a data reading method, apparatus, storage device, and storage medium.
Background
Nand flash memory is a nonvolatile memory, which stores data by performing read-write erasing operation on a memory unit, has the advantages of high writing speed, large storage capacity and the like, is widely used in electronic products, and along with the massive use of flash memory, the performance requirements of the flash memory are continuously improved.
In the process of Nand flash memory read operation, in order to correct various types of error bits, an error checking and correcting (Error Checking and Correction, ECC) algorithm is generally introduced, that is, the state of a memory cell is read first, then the read data is put into an internal latch, the error data in the latch is corrected by the ECC algorithm, and the read operation is ended. Therefore, the number of error data stored in the memory is not reduced.
Disclosure of Invention
The invention provides a data reading method, a data reading device, a storage device and a storage medium, so as to reduce the number of error data stored in a memory.
In a first aspect, an embodiment of the present invention provides a data reading method, including:
receiving an input reading instruction, wherein the reading instruction carries a reading address;
acquiring preset voltages of all word lines of a target memory cell to be read according to the read address;
reading data of the target memory cell according to preset voltages of each word line of the target memory cell;
obtaining an error unit of the read error in the target storage unit;
and updating the preset voltage of each word line of the error unit according to the type of the error unit so as to correct the error unit caused by the preset voltage of the word line.
Optionally, the updating the preset voltage of each word line of the error cell according to the type of the error cell includes:
when the type of the error unit is data retention error, reducing the preset voltage of the selected word line of the error unit by n times; said n is a positive number;
when the type of the error cell is a program disturb error, the preset voltage of the unselected word lines of the error cell is raised by m times, where m is a positive number.
Optionally, the obtaining the error unit of the read error in the target storage unit includes:
searching error data in the read data through an ECC algorithm;
in the target memory cell, an error bit storing the error data is acquired.
Optionally, the reading the data of the target storage unit includes:
reading the data from the target storage unit to a latch according to the read instruction;
the data is output from the latch.
Optionally, n is 0.1; and m is 0.1.
In a second aspect, an embodiment of the present invention provides a data reading apparatus, including:
the receiving module is used for receiving an input reading instruction, wherein the reading instruction carries a reading address;
the acquisition module is used for acquiring preset voltages of all word lines of the target storage unit to be read according to the read address;
the reading module is used for reading the data of the target storage unit according to the preset voltage of each word line of the target storage unit;
the acquisition module is used for acquiring an error unit of the read error in the target storage unit;
and the updating module is used for updating the preset voltage of each word line of the error unit according to the type of the error unit so as to correct the error unit caused by the preset voltage.
Optionally, the updating module includes:
a lowering unit for lowering a preset voltage n times of a selected word line of the error unit when the type of the error unit is a data retention error; said n is a positive number;
and a raising unit for raising a preset voltage m times of a non-selected word line of the error cell when the type of the error cell is a program disturb error, the m being a positive number.
Optionally, n is 0.1; and m is 0.1.
In a third aspect, an embodiment of the present invention provides a storage device, including:
one or more processors;
storage means for storing one or more programs,
when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the data reading method as described in any of the first aspects.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, which program, when executed by a processor, implements a data reading method according to any one of the first aspects.
The invention updates the preset voltage of each word line of the error unit through the error type of the error unit, thus, when reading next time, reading the data of the error unit according to the updated preset voltage, solving the problem of reading errors caused by the error preset voltage, and realizing the repair of two types of error bits which cannot be actually repaired in the memory in the prior art.
Drawings
FIG. 1 is a flow chart of a data reading method according to a first embodiment of the invention;
FIG. 2 is a flow chart of a data reading method according to a first embodiment of the invention;
FIG. 3 is a schematic diagram of a memory state change in a first embodiment of the invention;
FIG. 4 is a schematic diagram of a memory state change in a first embodiment of the invention;
FIG. 5 is a schematic diagram of the internal structure of a memory block (block) according to the first embodiment of the present invention;
FIG. 6 is a flow chart of a data reading method according to the first embodiment of the invention;
FIG. 7 is a flow chart of a data reading method according to a first embodiment of the invention;
FIG. 8 is a flow chart of a data reading method in a second embodiment of the invention;
fig. 9 is a schematic diagram of a data reading apparatus according to a third embodiment of the present invention;
fig. 10 is a schematic diagram of a data reading apparatus according to a third embodiment of the present invention;
FIG. 11 is a schematic diagram of a data reading apparatus according to a third embodiment of the present invention;
fig. 12 is a schematic diagram of a data reading apparatus according to a third embodiment of the present invention;
fig. 13 is a schematic structural diagram of a memory device according to a fourth embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a flowchart of a data reading method according to an embodiment of the present invention, where the embodiment is applicable to a memory reading situation, and the method may be performed by a data reading apparatus, and specifically includes the following steps:
step 101, receiving an input reading instruction.
The read instruction carries a read address.
Step 102, obtaining preset voltages of the word lines of the target memory cell to be read according to the read address.
The read address here includes the address of the block to be read, the address of the word line that reads which target memory cells in the block, and the like. Here, the preset voltage of the word line is preset and stored in the latch.
Taking Nand flash memory as an example, the Nand flash memory internal memory structure unit is based on a MOSFET (metal-oxide-semiconductor-field effect transistor), and is different from a general field effect transistor in that a floating gate exists between a gate (control gate) and a drain/source, and data is stored using the floating gate.
When the data is read, a read voltage is applied to the control gate, and for a cell with charges in the floating gate, the charges in the floating gate can offset the voltage supplied to the control gate, so that the threshold voltage is increased. If the control gate is not supplied with a high voltage, the drain-source is not in a conductive state, as compared with the case when there is no charge in the floating gate. Therefore, by determining whether or not the drain-source electrode is in the on state by applying the read voltage to the control gate, it is possible to determine whether or not the floating gate stores charge, and further whether or not the memory cell is in the erased state or the programmed state.
The writing (programming) of data is performed by such as and discharging of charges between the main board and the control gate. While NAND flash memory uses F-N tunneling to charge the floating gate through the silicon substrate, current flowing from the floating gate to the silicon substrate.
In Nand flash memory, data is stored in the form of charges, the amount of stored charges depends on the voltage applied by the control gate, the gate and the main board are insulated by an oxide film, and the charges accumulated at one time can be maintained for a long time, but if the oxide film is defective or the insulating film is damaged for some reason, the flash memory loses memory. Therefore, the purpose of the programming operation is to change the charge amount, thereby realizing correction of erroneous data.
Step 103, reading the data of the target memory cell according to the preset voltages of the word lines of the target memory cell.
In general, a memory cell stores errors due to a preset voltage, and thus reading of a few bits stored in the memory cell is problematic. Thus, a suitable preset voltage is used to ensure that the data can be read correctly.
Step 104, obtaining an error unit of the read error in the target storage unit.
The data of the target storage unit is read into the data latch, which data are error data are searched in the data latch, and the address of the error data stored in the memory, namely the address of the target storage unit, can be searched according to the storage address of the error data in the latch.
Step 105, updating the preset voltages of the word lines of the error cell according to the type of the error cell.
In this way, the erroneous unit caused by the preset voltage is corrected.
The error cells are classified by the type of error cause. The main reason for the error in this embodiment is that the memory state is not changed by human. The memory states include: a programmed state (write state) and an erased state. The reasons for such non-human alterations include the following two:
alternatively, the Data retention (Data retention) phenomenon causes that electrons on a floating gate of a Nand flash memory are lost if the Nand flash memory is stored for a long time, so that a preset voltage applied to a selected word line in the memory cell becomes small, and the Data retention phenomenon causes that the memory cell in an original programmed state gradually becomes an erased state, thereby causing the introduction of errors.
Alternatively, the program disturb phenomenon, i.e., the process of programming (writing) is caused by a higher preset voltage applied to the unselected word lines, which causes the memory cell threshold of the erased state of the unselected word lines to be raised to the programmed state, thereby causing the introduction of errors.
The invention updates the preset voltage of each word line of the error unit through the error type of the error unit, thus, when reading next time, reading the data of the error unit according to the updated preset voltage, solving the problem of reading errors caused by the error preset voltage, and realizing the repair of two types of error bits which cannot be actually repaired in the memory in the prior art.
On the basis of the above technical solution, as shown in fig. 2, step 105 may include:
step 1051, when the type of the error cell is a data retention error, decreasing the preset voltage of the selected word line of the error cell by n times.
Type of data retention error: upon not receiving an input erase command, the error cell changes from being in a programmed state (characterized by 0) to an erased state (characterized by 1), as shown in FIG. 3.
Step 1052, when the type of the error cell is a program disturb error, raise the preset voltage m times of the unselected word lines of the error cell.
Type of program disturb error: upon not receiving an input program (write) instruction, the error cell changes from being in the erased state (characterized by 1) to the programmed state (characterized by 0), as shown in FIG. 4.
Here, n is a positive number, and m is a positive number.
Each time data is read, the data is read according to the preset voltage of the word line updated last time, if the preset voltage of the word line of the error unit updated last time does not reach the voltage value of the state change, the data needs to be continuously increased or decreased on the basis of the preset voltage last time.
As shown in FIG. 5, the preset voltage of the selected word line is V cgrv A voltage; the preset voltage of the unselected word line is V read 。
Based on the above technical solution, as shown in fig. 6, step 104 may include:
step 1041, searching error data in the read data by using an ECC algorithm.
When writing these data, it is necessary to generate a check code by a check code generation algorithm, and each time a check code generation operation is performed on 256 bytes of data, the check code generation operation includes column check and row check. Solving exclusive OR of each bit of each memory cell to be verified, and if the result is 0, indicating that the memory cell contains even number 1; if the result is 1, it is indicated that an odd number of 1 s are contained. 256 bytes of data form a matrix of 256 rows and 8 columns, with each element of the matrix representing a bit. The matrix is the original ECC checksum, and the transmission layer protocol stored into the page uses Out-Of-Band (OOB) area. When reading data from the NAND flash memory into the register, we generate one ECC checksum every 256 bytes, referred to as a new ECC checksum. The original ECC checksum read from the OOB area and the new ECC checksum are exclusive-ored by bits, and if the result is 0, the error does not exist (or an error which cannot be detected by ECC exists); if 11 bits are 1 in the exclusive OR result of 3 bytes, the error of one bit exists and can be corrected; if only 1 bit is 1 in the exclusive OR result of 3 bytes, indicating that the OOB area is in error; other cases indicate uncorrectable errors. Since the reading of each bit is also erroneous for the memory cells with the read errors caused by the preset voltage, it is possible to determine which bits are erroneous, and it is possible to determine which memory cells are read errors.
Step 1042, in the target memory cell, an error cell of the read error is obtained.
And determining the address of the error data stored in the register according to the error data of the read error, and inquiring the storage unit, the bit and the address corresponding to the memory according to the address of the register. The bits herein refer to bits.
On the basis of the above technical solution, as shown in fig. 7, step 103 may include:
step 1031, reading data from the target memory cell to the latch according to the read instruction.
Step 1032, outputting data from the latch.
Optionally, n is 0.1; and m is 0.1.
Example two
Fig. 8 is a flowchart of a data reading method according to an embodiment of the present invention, where the embodiment is applicable to a memory reading situation, and the method may be performed by a memory device, and specifically includes the following steps:
step 201, receiving an input reading instruction.
Step 202, obtaining preset voltages of the word lines of the target memory cell to be read according to the read address.
Step 203, reading the data of the target memory cell according to the preset voltages of the word lines of the target memory cell.
Step 204, searching error data in the read data through an ECC algorithm.
Step 205, an error unit of the read error is obtained in the target memory unit.
Step 206, determining the type of the error unit.
Step 207, when the type of the error cell is a data retention error, the preset voltage of the selected word line of the error cell is reduced by 0.1 times.
Step 208, when the type of the error cell is a program disturb error, the preset voltage of the unselected word lines of the error cell is raised by 0.1 times.
In this way, the two types of error bits in the memory which cannot be actually repaired in the prior art are repaired, ECC resources used by error data are saved, the rest ECC resources can correct more other types of error bits, and the reliability of the memory cell is improved.
The data reading device provided by the embodiment of the invention can execute the data reading method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Example III
Fig. 9 is a schematic structural diagram of a data reading apparatus according to a third embodiment of the present invention, where the present embodiment is applicable to a memory reading situation, and the apparatus includes:
the receiving module 301 is configured to receive an input read instruction, where the read instruction carries a read address.
And an acquiring module 302, configured to acquire a preset voltage of each word line of the target memory cell to be read according to the read address.
And a reading module 303, configured to read data of the target memory cell according to a preset voltage of each word line of the target memory cell.
The obtaining module 304 is configured to obtain an error unit of the read error in the target storage unit.
An updating module 305, configured to update a preset voltage of each word line of the error cell according to the type of the error cell, so as to correct the error cell caused by the preset voltage.
The invention updates the preset voltage of each word line of the error unit through the error type of the error unit, thus, when reading next time, reading the data of the error unit according to the updated preset voltage, solving the problem of reading error caused by the error preset voltage and realizing the effect of reducing error data in the reading result.
On the basis of the above technical solution, as shown in fig. 10, the update module 305 includes:
a lowering unit 3051 for lowering a preset voltage of a selected word line of the error cell by n times when the type of the error cell is a data retention error; said n is a positive number;
and a raising unit 3052 for raising a preset voltage of the unselected word lines of the error cell by m times when the type of the error cell is a program disturb error, where m is a positive number.
On the basis of the above technical solution, as shown in fig. 11, the obtaining module 304 includes:
a searching unit 3041, configured to search for error data in the read data by using an ECC algorithm;
an acquisition unit 3042 for acquiring, in the target storage unit, an error bit storing the error data.
Optionally, as shown in fig. 12, the reading module 303 includes:
a readout unit 3031 for reading out the data from the target storage unit to a latch according to the read instruction;
an output unit 3032, for outputting the data from the latch.
Optionally, n is 0.1; and m is 0.1.
Example IV
Fig. 13 is a schematic structural diagram of a storage device according to a fourth embodiment of the present invention, and as shown in fig. 13, the storage device includes a processor 70, a memory 71, an input device 72, and an output device 73; the number of processors 70 in the memory device may be one or more, one processor 70 being illustrated in fig. 13; the processor 70, memory 71, input means 72 and output means 73 in the storage device may be connected by a bus or other means, in fig. 13 by way of example.
The memory 71 is a computer-readable storage medium, and may be used to store software programs, computer-executable programs, and modules, such as program instructions/modules (e.g., a receiving module 301, an acquiring module 302, a reading module 303, an acquiring module 304, and an updating module 305 in a data reading apparatus) corresponding to a data reading method in an embodiment of the present invention. The processor 70 executes various functional applications of the storage device and data processing, i.e., implements the data reading method described above, by running software programs, instructions, and modules stored in the memory 71.
The memory 71 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for functions; the storage data area may store data created according to the use of the storage device, etc. In addition, memory 71 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some examples, memory 71 may further include memory remotely located relative to processor 70, which may be connected to the storage device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input means 72 may be used to receive entered numeric or character information and to generate key signal inputs related to user settings and function control of the memory device. The output means 73 may comprise a display device such as a display screen.
Example five
A fifth embodiment of the present invention also provides a storage medium containing computer-executable instructions, which when executed by a computer processor, are for performing a data reading method, the method comprising:
receiving an input reading instruction, wherein the reading instruction carries a reading address;
acquiring preset voltages of all word lines of a target memory cell to be read according to the read address;
reading data of the target memory cell according to preset voltages of each word line of the target memory cell;
obtaining an error unit of the read error in the target storage unit;
and updating the preset voltage of each word line of the error unit according to the type of the error unit.
Of course, the storage medium containing the computer executable instructions provided in the embodiments of the present invention is not limited to the method operations described above, and may also perform the related operations in the data reading method provided in any embodiment of the present invention.
From the above description of embodiments, it will be clear to a person skilled in the art that the present invention may be implemented by means of software and necessary general purpose hardware, but of course also by means of hardware, although in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, etc., and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments of the present invention.
It should be noted that, in the above-mentioned embodiments of the search apparatus, each unit and module included are only divided according to the functional logic, but not limited to the above-mentioned division, as long as the corresponding functions can be implemented; in addition, the specific names of the functional units are also only for distinguishing from each other, and are not used to limit the protection scope of the present invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (8)
1. A data reading method, comprising:
receiving an input reading instruction, wherein the reading instruction carries a reading address;
acquiring preset voltages of all word lines of a target memory cell to be read according to the read address;
reading data of the target memory cell according to preset voltages of each word line of the target memory cell; the storage unit is in storage error caused by the preset voltage, so that the data in the storage unit is read out to have a problem;
obtaining an error unit of the read error in the target storage unit;
updating preset voltages of the word lines of the error cells according to the types of the error cells so as to correct the error cells caused by the preset voltages of the word lines;
wherein, according to the type of the error unit, updating the preset voltage of each word line of the error unit comprises:
when the type of the error unit is data retention error, reducing the preset voltage of the selected word line of the error unit by n times; said n is a positive number;
when the type of the error cell is a program disturb error, the preset voltage of the unselected word lines of the error cell is raised by m times, where m is a positive number.
2. The method of claim 1, wherein the retrieved error cells of the read error in the target memory cell comprise:
searching error data in the read data through an error checking and correcting ECC algorithm;
in the target memory cell, an error bit storing the error data is acquired.
3. The method of claim 1, wherein the reading the data of the target memory cell comprises:
reading the data from the target storage unit to a latch according to the read instruction;
the data is output from the latch.
4. The method of claim 1, wherein n is 0.1; and m is 0.1.
5. A data reading apparatus, comprising:
the receiving module is used for receiving an input reading instruction, wherein the reading instruction carries a reading address;
the acquisition module is used for acquiring preset voltages of all word lines of the target storage unit to be read according to the read address;
the reading module is used for reading the data of the target storage unit according to the preset voltage of each word line of the target storage unit; the storage unit is in storage error caused by the preset voltage, so that the data in the storage unit is read out to have a problem;
the acquisition module is used for acquiring an error unit of the read error in the target storage unit;
an updating module for updating the preset voltages of the word lines of the error unit according to the type of the error unit so as to correct the error unit caused by the preset voltages of the word lines;
wherein the update module comprises:
a lowering unit for lowering a preset voltage n times of a selected word line of the error unit when the type of the error unit is a data retention error; said n is a positive number;
and a raising unit for raising a preset voltage m times of a non-selected word line of the error cell when the type of the error cell is a program disturb error, the m being a positive number.
6. The apparatus of claim 5, wherein n is 0.1; and m is 0.1.
7. A storage device, the storage device comprising:
one or more processors;
storage means for storing one or more programs,
when executed by the one or more processors, causes the one or more processors to implement the data reading method of any of claims 1-4.
8. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements a data reading method according to any one of claims 1-4.
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| CN201811080692.XA CN110908825B (en) | 2018-09-17 | 2018-09-17 | Data reading method and device, storage equipment and storage medium |
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| CN201811080692.XA CN110908825B (en) | 2018-09-17 | 2018-09-17 | Data reading method and device, storage equipment and storage medium |
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| CN110908825A CN110908825A (en) | 2020-03-24 |
| CN110908825B true CN110908825B (en) | 2024-03-01 |
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