CN112259683B - Self-assembly bipolar organic field effect transistor memory and preparation method thereof - Google Patents
Self-assembly bipolar organic field effect transistor memory and preparation method thereof Download PDFInfo
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
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Abstract
The invention discloses a self-assembled bipolar organic field effect transistor memory and a preparation method thereof, wherein the memory sequentially comprises a source electrode, a drain electrode, an organic semiconductor layer, a gate insulating layer and a substrate from top to bottom, a charge trapping layer is arranged between the organic semiconductor layer and the gate insulating layer, and the charge trapping layer is a nano columnar film formed by self-assembling octadecyl trichlorosilane and a polymer with high dielectric constant; the preparation method constructs the structure of the nano-pillar by the self-assembly of the combination of two polymer solutions, thereby realizing the transmission of charge hole carriers to achieve the bipolar information storage. Meanwhile, the difficulty of preparing an ultra-smooth OTS layer is reduced by self-assembly of the two mixed polymers, compared with an ultra-smooth OTS thin film transistor memory, the transistor memory prepared by the mixed self-assembly has obvious charge stability, and on the premise of ensuring various transistor performance parameters, better storage performance and device maintenance performance are realized.
Description
Technical Field
The present invention relates to an organic field effect transistor memory, and more particularly, to an organic field effect transistor memory having a bipolar memory performance through a self-assembly process and a method for fabricating the same.
Background
The organic field effect transistor memory is used as a basic storage technology device, and has the advantages of light weight, low cost, low-temperature and large-area processing, easy compatibility with a flexible substrate, green preparation, convenient recovery and the like, so that the organic field effect transistor memory is very suitable for the requirement of future development of the memory. In Organic Field Effect Transistors (OFETs), charge transfer usually occurs mainly at the dielectric/semiconductor interface, so the properties of the dielectric/semiconductor interface determine the performance of the device, and modifying the dielectric surface with a self-assembled monomolecular film (SAM) can improve the quality of the dielectric/semiconductor interface, reduce charge trapping and scattering, and thus significantly improve the performance of various electronic devices. Octadecyltrichlorosilane (OTS) is widely applied to surface modification of organic semiconductor materials as a surfactant for modifying the surface of a medium, so that the performance of an organic semiconductor device is greatly improved, but in the existing prepared device, the surface quality (especially the surface roughness) of an OTS single-layer film prepared by the OTS single-layer film cannot be ensured due to the influence of three active Cl-Si groups in the octadecyltrichlorosilane, so that the reproducibility of the OFET device performance is poor, and therefore, the surface roughness of the OTS single-layer film is difficult to ensure to have higher reproducibility by a conventional solution or steam modification method.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide an organic field effect transistor memory which adopts mixed self-assembly to regulate and control surface morphology to realize high reproducibility and has bipolar storage performance; the second objective of the present invention is to provide a method for manufacturing the organic field effect transistor memory.
The technical scheme is as follows: the self-assembly bipolar organic field effect transistor memory comprises a source electrode, a drain electrode, an organic semiconductor layer, a gate insulating layer and a substrate from top to bottom in sequence, wherein a charge trapping layer is arranged between the organic semiconductor layer and the gate insulating layer, and the charge trapping layer is a nano columnar film formed by self-assembly of octadecyl trichlorosilane and polymers with high dielectric constants.
The charge trapping layer adopts widely-applied organic materials for modifying the surface of the substrate: the octadecyl trichlorosilane and the polystyrene which is a hydrophobic insulating material with high dielectric constant are combined with the modification and the insulating performance of the octadecyl trichlorosilane and the polystyrene to construct a charge trapping layer which completely covers the gate insulating layer. The prepared charge trapping layer adopts a self-assembly method to form a micro-morphology with the nano-pillars, when single solution self-assembly is adopted, the charge trapping layer can be controlled to form a monomolecular layer film, and when another organic solution is mixed, the morphology of the formed nano-pillars can be controlled. When the substrate surface is modified by using octadecyltrichlorosilane, the molecules of the octadecyltrichlorosilane are provided with three active Cl-Si groups, so that the treatment process must be carried out under strict experimental environments such as temperature and humidity, the device performance can be ensured only under such extremely harsh conditions, and the reproducibility of the device is very poor. When the self-assembly treatment mode is adopted, the difficulty of the preparation process can be effectively reduced, the experimental environment does not need to be strictly controlled, and the operation can be carried out at a ventilation position.
Further, the polymer with high dielectric constant is any one of polystyrene or polymethyl methacrylate.
Furthermore, the source and drain electrodes are made of copper or gold, and the thickness of the source and drain electrodes is 60-100 nm.
Furthermore, the organic semiconductor layer is made of any one of pentacene, tetracene, titanium cyanide copper, rubrene and triphenyl, and the thickness of the organic semiconductor layer is 60-80 nm.
Furthermore, the gate insulating layer is made of any one of silicon dioxide, aluminum oxide, zirconium oxide and polyvinylpyrrolidone, and the thickness of the gate insulating layer is 50-300 nm.
Further, the substrate is a heavily doped silicon substrate, a gate electrode is further arranged on the substrate, and the gate electrode is made of any one of highly doped silicon, aluminum, copper, silver, gold or a tip.
The invention further protects a preparation method of the self-assembly bipolar organic field effect transistor memory, which comprises the following steps:
the first step is as follows: dissolving octadecyl trichlorosilane and a polymer with a high dielectric constant in a low-boiling point solvent respectively to form a polymer solution, wherein the concentration of the solution is 2-4 mg/mL;
the second step is that: forming a gate electrode and a gate insulating layer on a substrate to prepare a substrate, ultrasonically cleaning the substrate by acetone, ethanol and deionized water respectively, and then drying the substrate;
the third step: carrying out ozone treatment on the dried substrate for 3-5 min;
the fourth step: placing the substrate treated in the third step into an octadecyl trichlorosilane solution to enable the substrate surface of the substrate to be upward, slowly dripping a polymer solution with a high dielectric constant along the vertical direction of the substrate by using a dropper after the substrate is completely immersed, sealing and standing the substrate for self-assembly for 10-15 hours after the dripping is finished, then taking out the substrate for washing by using a low-boiling-point solvent, and performing drying annealing at the temperature of 75-85 ℃ for 25-35 min after the washing is finished to form a charge trapping layer;
the fifth step: and vacuum evaporating an organic semiconductor layer and a source drain electrode on the charge trapping layer of the prepared sample in the fourth step.
Further, in the fourth step, the volume ratio of the octadecyl trichlorosilane solution to the polymer solution with high dielectric constant is 2-3: 1; the substrate is rinsed with the low boiling point solvent under conditions such that the low boiling point solvent does not coalesce as a drop or stream on the surface of the substrate.
Further, in the fifth step, the evaporation rate of vacuum evaporation of the organic semiconductor layer is
The vacuum degree is controlled at 5X 10 -4 The thickness of the organic semiconductor layer is controlled to be 60-80 nm through a crystal oscillator below Pa; plating copper or gold on the prepared organic semiconductor layer by using a mask plate through evaporation at the evaporation rate of
The vacuum degree is controlled at 5X 10 -4 And the thickness of the source and drain electrodes is controlled to be 60-100 nm by a crystal oscillator below Pa.
Has the beneficial effects that: compared with the prior art, the invention has the following remarkable advantages: 1. the invention selects the existing easily-obtained materials, reduces the preparation difficulty through a self-assembly processing mode, designs the charge trapping layer with the nano micro morphology, and compared with an ultra-smooth OTS thin film transistor memory, the transistor memory mixed with the self-assembly shows obvious charge stability, and realizes better storage performance and device maintenance performance on the premise of ensuring various transistor performance parameters; 2. the method combines the polystyrene and the octadecyl trichlorosilane, reduces the difficulty that the self-assembly environment needs to be strictly controlled when the octadecyl trichlorosilane is independently adopted to modify the silicon wafer substrate, and has high repetition rate; 3. the preparation method provided by the invention is simple in process and convenient to operate, and reduces the labor cost.
Drawings
FIG. 1 is a schematic structural diagram of an organic field effect transistor memory with bipolar memory performance prepared by the present invention;
FIG. 2 is an AFM of a charge trapping layer prepared in example 1 of the present invention;
FIG. 3 is a memory transfer curve of a memory prepared in example 1 of the present invention;
FIG. 4 is a graph showing the output curves of the memory prepared in example 1 of the present invention;
FIG. 5 is a memory characteristic transfer curve of a memory prepared in example 1 of the present invention with forward gate voltage applied;
FIG. 6 is a memory characteristic transfer curve of a memory fabricated in example 1 of the present invention with a negative gate voltage applied;
FIG. 7 is a characteristic curve of the retention time for applying the forward memory performance to the memory prepared in example 1 of the present invention;
FIG. 8 is a retention time characteristic curve of a memory prepared in example 1 of the present invention, which shows a negative memory performance;
FIG. 9 is a characteristic curve of the retention time of a memory prepared in example 1 of the present invention when a forward gate voltage is applied;
FIG. 10 is a characteristic curve of the retention time of a memory prepared in example 1 of the present invention with a negative gate voltage applied;
FIG. 11 is an AFM image of a charge trapping layer prepared in comparative example 1;
FIG. 12 is a memory characteristic transfer curve of a memory prepared in comparative example 1 with a forward gate voltage applied;
fig. 13 is a memory characteristic transfer curve of the memory prepared in comparative example 1 with a negative gate voltage applied.
Detailed Description
The invention is further illustrated by the following figures and examples.
The invention provides an organic field effect transistor memory with bipolar memory performance processed by a self-assembly means and a preparation method thereof, wherein the structure of the organic field effect transistor memory is shown as figure 1, and the organic field effect transistor memory comprises the following components: heavily doped silicon substrate; a gate electrode formed over the substrate 5; a gate insulating layer 4 covering the gate electrode; a charge trapping layer 3 formed on the gate insulating layer 4; an organic semiconductor layer 2 overlying the charge trapping layer 3; and source-drain electrodes 1 formed on both sides of a channel region on the surface of the organic semiconductor layer 2. In the actual preparation of the devices, the room temperature in the laboratory was kept constant at around 25 ℃ and the humidity was kept below 50%.
Example 1
(1) Preparing a Polystyrene (PS) solution with the concentration of 3mg/mL for at least 12 hours in advance to ensure that the polystyrene is fully dissolved; preparing octadecyl trichlorosilane (OTS solution) with the concentration of 3 mg/mL; the low boiling point solvents are toluene without additional treatment;
(2) selecting a heavily doped silicon wafer as a substrate, and sequentially forming a gate electrode and a gate insulating layer on the substrate, wherein the gate electrode is made of n-type doped silicon material, and the gate insulating layer is made of SiO 2 The thickness is 50nm, and a substrate is prepared; placing the substrate in a beaker, adding acetone to immerse the silicon wafer substrate, performing ultrasonic treatment for 15min, and pouring off the acetone; then, ethanol and deionized water were added, and the same operation as that for acetone treatment of the silicon wafer substrate was repeated. Then, drying the surface by nitrogen, placing the surface in an oven at 120 ℃ for 30min, and completely drying the substrate;
(3) placing the substrate dried in the step (2) in an ozone machine for treatment for 5 min;
(4) in a fume hood, the humidity is about 45 percent, a proper amount of octadecyl trichlorosilane solution is added into a screw-mouth strain bottle, and the cleaned substrate SiO is coated on the substrate 2 Placing the solution in a manner of facing upwards horizontally, and then slowly adding a fully dissolved polystyrene solution in the vertical direction by using a dropper, wherein the volume ratio of the octadecyl trichlorosilane solution to the polystyrene solution is 2.5: 1, then covering a cover and sealing the strain bottle by using a sealing film;
(5) standing for self-assembly for 12h, taking out the silicon wafer substrate, washing the upward surface with a toluene solution until the toluene is not aggregated into drops or flows down on the surface, and then putting the silicon wafer substrate into an oven at 80 ℃ immediately for annealing for 30 mins;
(6) vacuum evaporating organic semiconductor layer pentacene on the surface of the film prepared in the step (5), and controlling the vacuum degree in a vacuum chamber to be 4.0 multiplied by 10 -4 Pa, controlling the evaporation rate to
Controlling the thickness of the semiconductor layer to be 60nm through a crystal oscillator;
(7) evaporating and plating source and drain electrodes on the prepared organic semiconductor layer, preparing the electrodes by using a mask method to carry out electrode patterning treatment, adopting copper as an electrode material, controlling the width and the length of a channel of an electrode mask plate to be 1500 mu m and controlling the vacuum degree in a vacuum chamber to be 4.0 multiplied by 10 -4 Pa, evaporation rate of
The thickness of the electrode is controlled to be 60nm by a crystal oscillator.
Example 2
(1) Preparing a Polystyrene (PS) solution with the concentration of 2mg/mL for at least 12 hours in advance to ensure that the polystyrene is fully dissolved; preparing octadecyl trichlorosilane (OTS solution) with the concentration of 2 mg/mL; the low boiling point solvents are toluene without additional treatment;
(2) selecting a heavily doped silicon wafer as a substrate, and sequentially forming a gate electrode and a gate insulating layer on the substrate, wherein the gate electrode is made of an aluminum material, the gate insulating layer is made of aluminum oxide and has the thickness of 100nm, and the substrate is prepared; placing the substrate in a beaker, adding acetone to immerse the silicon wafer substrate, carrying out ultrasonic treatment for 15min, and pouring off the acetone; then, ethanol and deionized water were added, and the same operation as that for acetone treatment of the silicon wafer substrate was repeated. Then, drying the surface by nitrogen, placing the surface in an oven at 120 ℃ for 30min, and completely drying the substrate;
(3) placing the substrate dried in the step (2) in an ozone machine for treatment for 4 min;
(4) in a fume hood, the humidity is about 45 percent, a proper amount of octadecyl trichlorosilane solution is added into a screw-mouth strain bottle, and the cleaned substrate SiO is coated on the substrate 2 Placing the solution in a manner of facing upwards horizontally, and then slowly adding a fully dissolved polystyrene solution in the vertical direction by using a dropper, wherein the volume ratio of the octadecyl trichlorosilane solution to the polystyrene solution is 2: 1, then covering a cover and sealing the strain bottle by using a sealing film;
(5) standing for self-assembly for 10h, taking out the silicon wafer substrate, washing the upward surface with a toluene solution until the toluene is not aggregated into drops or flows down on the surface, and then immediately putting the silicon wafer substrate into a 75 ℃ oven for annealing for 25 mins;
(6) vacuum evaporating organic semiconductor layer tetracene on the surface of the film prepared in the step (5), and controlling the vacuum degree in the vacuum chamber to be 4.5 multiplied by 10- 4 Pa, controlling the evaporation rate to
Controlling the thickness of the semiconductor layer to be 70nm through a crystal oscillator;
(7) evaporating and plating source and drain electrodes on the prepared organic semiconductor layer, preparing the electrodes by using a mask method to carry out patterning treatment on the electrodes, adopting copper as an electrode material, controlling the width and the length of a channel of an electrode mask plate to be 1500 mu m and controlling the vacuum degree in a vacuum chamber to be 4.5 multiplied by 10- 4 Pa, evaporation rate of
The thickness of the electrode is controlled to be 80nm by a crystal oscillator.
Example 3
(1) Preparing a polymethyl methacrylate (PMMA) solution with the concentration of 4mg/mL for at least 12 hours in advance to ensure that the polystyrene is fully dissolved; preparing octadecyl trichlorosilane (OTS solution) with the concentration of 4 mg/mL; the low boiling point solvents are toluene without additional treatment;
(2) selecting a heavily doped silicon wafer as a substrate, and sequentially forming a gate electrode and a gate insulating layer on the substrate, wherein the gate electrode is made of a copper material, the gate insulating layer is made of polyvinylpyrrolidone, and the thickness of the gate insulating layer is 150nm, so that a substrate is prepared; placing the substrate in a beaker, adding acetone to immerse the silicon wafer substrate, carrying out ultrasonic treatment for 15min, and pouring off the acetone; then, ethanol and deionized water were added, and the same operation as that for acetone treatment of the silicon wafer substrate was repeated. Then, drying the surface by nitrogen, placing the surface in an oven at 120 ℃ for 30min, and completely drying the substrate;
(3) placing the substrate dried in the step (2) in an ozone machine for treatment for 3 min;
(4) in a fume hood, the humidity is about 45%, and a proper amount of the strain bottle with a screw mouth is addedOctadecyl trichlorosilane solution, substrate SiO of cleaned substrate 2 Placing the solution in a manner of facing upwards horizontally, and then slowly adding a fully dissolved polystyrene solution in the vertical direction by using a dropper, wherein the volume ratio of the octadecyl trichlorosilane solution to the polystyrene solution is 3: 1, then covering a cover and sealing the strain bottle by using a sealing film;
(5) standing for self-assembly for 15h, taking out the silicon wafer substrate, washing the upward surface with a toluene solution until the toluene is not aggregated into drops or flows down on the surface, and then putting the silicon wafer substrate into an oven at 85 ℃ immediately for annealing for 35 mins;
(6) vacuum evaporating organic semiconductor layer titanium-cyanogen copper on the surface of the film prepared in the step (5), and controlling the vacuum degree in a vacuum chamber to be 4.5 multiplied by 10 -4 Pa, controlling the evaporation rate to
Controlling the thickness of the semiconductor layer to be 80nm through a crystal oscillator;
(7) evaporating and plating source and drain electrodes on the prepared organic semiconductor layer, preparing the electrodes, patterning the electrodes by using a mask method, adopting gold as an electrode material, controlling the width and the length of a channel of an electrode mask plate to be 1500 mu m and controlling the vacuum degree in a vacuum chamber to be 4.5 multiplied by 10 -4 Pa, evaporation rate of
The thickness of the electrode is controlled to be 100nm by a crystal oscillator.
Comparative example 1
(1) Preparing octadecyl trichlorosilane (OTS solution) with the concentration of 3 mg/mL; the low boiling point solvents are toluene without additional treatment;
(2) selecting a heavily doped silicon wafer as a substrate, and sequentially forming a gate electrode and a gate insulating layer on the substrate, wherein the gate electrode is made of n-type doped silicon material, and the gate insulating layer is made of SiO 2 The thickness is 50nm, and a substrate is prepared; placing the substrate in a beaker, adding acetone to immerse the silicon wafer substrate, performing ultrasonic treatment for 15min, and pouring off the acetone; adding ethanol and deionized water, and repeating the same operation as that for treating silicon wafer substrate with acetoneDo this. Then, drying the surface by nitrogen, placing the surface in an oven at 120 ℃ for 30min, and completely drying the substrate;
(3) placing the substrate dried in the step (2) in an ozone machine for treatment for 5 min;
(4) in a glove box, the humidity is about 15 percent, the oxygen content is less than 5 percent, a proper amount of octadecyl trichlorosilane solution is added into a screw-mouth strain bottle, and the cleaned silicon chip substrate SiO is 2 Placing the bottle in a solution with an upward horizontal surface, covering the bottle with a cover and sealing the strain bottle with a sealing film, wherein the water and oxygen contents must be strictly controlled in the process, so that the water and oxygen are prevented from entering as much as possible, and all solvents for experiments need to be unopened and must be opened in a glove box;
(5) standing for self-assembly for 12h, taking out the silicon wafer substrate, washing the upward surface with a toluene solution until the toluene is not aggregated into drops or flows down on the surface, and then putting the silicon wafer substrate into an oven at 80 ℃ immediately for annealing for 30 mins;
(6) vacuum evaporating organic semiconductor layer pentacene on the surface of the film prepared in the step (5), and controlling the vacuum degree in a vacuum chamber to be 4.0 multiplied by 10 -4 Pa, controlling the evaporation rate to
Controlling the thickness of the semiconductor layer to be 60nm through a crystal oscillator;
(7) evaporating and plating source and drain electrodes on the prepared organic semiconductor layer, preparing the electrodes by using a mask method to carry out electrode patterning treatment, adopting copper as an electrode material, controlling the width and the length of a channel of an electrode mask plate to be 1500 mu m and controlling the vacuum degree in a vacuum chamber to be 4.0 multiplied by 10 -4 Pa, evaporation rate of
The thickness of the electrode is controlled to be 60nm by a crystal oscillator.
Performance testing
Referring to fig. 2, which is a photograph showing the morphology of the mixed self-assembled nano-pillars prepared in example 1, it is seen that the nano-pillars are well-aligned and have almost no difference in height, while having a small roughness, and have little influence on the growth of an upper thin film, and referring to fig. 11, which is a photograph showing the morphology of a monolayer thin film prepared in comparative example 1, it is seen in fig. 11 that the entire surface has no significant protrusion or depression, and the height of the pattern is very small and the roughness is very small according to the roughness analysis of the AFM image, compared to the morphology of fig. 2.
The devices prepared in example 1 and comparative example 1 were tested for electrical performance using a Keithley4200 semiconductor analyzer, and the transfer curves and output curves were stored as shown in fig. 3-4 and 12-13, with specific data as shown in table 1:
table 1 electrical performance data for the memories of example 1 and comparative example 1
| Threshold voltage V th avg (V) | Mobility mu avg (cm 2 V- 1 s -1 ) | Current on-off ratio I ON /I off | |
| Example 1 | -2.04 | 1.15 | 9.68×10 5 |
| Comparative example 1 | -2.99 | 1.12 | 5.99×10 5 |
As can be seen from the results of table 1, example 1 controls the density of the nanopillars by controlling the mixing of the two solutions, thereby regulating the device mobility. When the film formed by self-assembly is not a monomolecular layer but a regular nanorod film, the electron mobility is not greatly reduced, the on-off ratio of the device is increased, the leakage current is reduced, and the performance of the device is generally improved.
Referring to fig. 5 and 6, which are the positive and negative memory characteristic transfer curves of the memory, it can be seen that the memory device has a bipolar memory characteristic, can store both electrons and holes, and has a large memory window.
Referring to fig. 7 and 8, the data retention capability of the memory is positive and negative respectively, and after 10000s, the memory switching ratio of the device is still kept at 10 2 This demonstrates that the memory reliability of the device is high.
Referring to fig. 9 and 10, the positive and negative write-read-erase-read characteristic data of the memory also indicate that the memory has good repeated erasing capability, and the erasing window of the device is basically unchanged after a certain period of erasing cycles.
In summary, the organic field effect transistor memory with bipolar memory performance processed by the self-assembly method of the invention has better transistor performance. When seeking means for improving the mobility, a mixed self-assembly mode for regulating and controlling the surface topography can be adopted, and a mode for controlling the experimental environment to prepare the ultra-smooth film is not adopted.
Claims (10)
1. The utility model provides a self-assembling bipolar organic field effect transistor memory, includes source drain electrode (1), organic semiconductor layer (2), grid insulation layer (4) and substrate (5) from top to bottom in proper order, its characterized in that: a charge trapping layer (3) is arranged between the organic semiconductor layer (2) and the grid insulating layer (4), and the charge trapping layer (3) is a nano columnar film formed by self-assembly of octadecyl trichlorosilane and polymers with high dielectric constants.
2. The self-assembled bipolar organic field effect transistor memory of claim 1, wherein: the polymer with high dielectric constant is any one of polystyrene or polymethyl methacrylate.
3. The self-assembled ambipolar organic field effect transistor memory of claim 1, wherein: the source and drain electrodes (1) are made of copper or gold, and the thickness of the source and drain electrodes is 60-100 nm.
4. The self-assembled ambipolar organic field effect transistor memory of claim 1, wherein: the organic semiconductor layer (2) is made of any one of pentacene, tetracene, titanium cyanide copper, rubrene and triphenyl, and the thickness of the organic semiconductor layer is 60-80 nm.
5. The self-assembled ambipolar organic field effect transistor memory of claim 1, wherein: the gate insulating layer (4) is made of any one of silicon dioxide, aluminum oxide, zirconium oxide and polyvinylpyrrolidone, and the thickness of the gate insulating layer is 50-300 nm.
6. The self-assembled ambipolar organic field effect transistor memory of claim 1, wherein: the substrate (5) adopts a heavily doped silicon substrate, a gate electrode is further arranged on the substrate (5), and the gate electrode is made of any one of highly doped silicon, aluminum, copper, silver, gold and tip.
7. The method for fabricating a self-assembled ambipolar organic field effect transistor memory device according to any of claims 1 to 6, comprising the steps of:
the first step is as follows: dissolving octadecyl trichlorosilane and a polymer with a high dielectric constant in a low-boiling point solvent respectively to form a polymer solution, wherein the concentration of the solution is 2-4 mg/mL;
the second step is that: forming a gate electrode and a gate insulating layer on a substrate to prepare a substrate, ultrasonically cleaning the substrate by acetone, ethanol and deionized water respectively, and then drying the substrate;
the third step: carrying out ozone treatment on the dried substrate for 3-5 min;
the fourth step: placing the substrate treated in the third step into an octadecyl trichlorosilane solution to enable the substrate surface of the substrate to be upward, slowly dripping a polymer solution with a high dielectric constant along the vertical direction of the substrate by using a dropper after the substrate is completely immersed, sealing and standing the substrate for self-assembly for 10-15 hours after the dripping is finished, then taking out the substrate for washing by using a low-boiling-point solvent, and performing drying annealing at the temperature of 75-85 ℃ for 25-35 min after the washing is finished to form a charge trapping layer;
the fifth step: and (3) carrying out vacuum evaporation on the organic semiconductor layer and the source drain electrode on the charge trapping layer of the prepared sample in the fourth step.
8. The method according to claim 7, wherein the method further comprises: in the fourth step, the volume ratio of the octadecyl trichlorosilane solution to the polymer solution with high dielectric constant is 2-3: 1.
9. the method according to claim 7, wherein the method further comprises: in the fourth step, the step of washing the substrate by using a low-boiling-point solvent is specifically as follows: the low boiling point solvent does not coalesce into drops or run down as a stream on the substrate surface.
10. The method according to claim 7, wherein the method further comprises: in the fifth step, the evaporation rate of vacuum evaporation of the organic semiconductor layer is
The vacuum degree is controlled at 5X 10 - 4 The thickness of the organic semiconductor layer is controlled to be 60-80 nm through a crystal oscillator below Pa; in the prepared organic semiconductor layerThe mask plate is utilized to evaporate copper or gold, the evaporation rate is
The vacuum degree is controlled at 5X 10 -4 And the thickness of the source and drain electrodes is controlled to be 60-100 nm by a crystal oscillator below Pa.
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| CN108258116A (en) * | 2017-12-28 | 2018-07-06 | 南京邮电大学 | A kind of semiconductor nano array organic field effect tube multi-bit memory and preparation method thereof |
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| CN108258116A (en) * | 2017-12-28 | 2018-07-06 | 南京邮电大学 | A kind of semiconductor nano array organic field effect tube multi-bit memory and preparation method thereof |
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