CN112259550A - Etching method and etching device for semiconductor device - Google Patents
Etching method and etching device for semiconductor device Download PDFInfo
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- CN112259550A CN112259550A CN202011133166.2A CN202011133166A CN112259550A CN 112259550 A CN112259550 A CN 112259550A CN 202011133166 A CN202011133166 A CN 202011133166A CN 112259550 A CN112259550 A CN 112259550A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The invention provides an etching method and an etching device for a semiconductor device. An etching method of a semiconductor device, comprising: providing a reaction chamber, wherein an upper electrode and a lower electrode arranged opposite to the upper electrode are arranged in the reaction chamber, and the upper electrode comprises a first part; conveying the semiconductor device into the reaction chamber, wherein the semiconductor device is positioned on the lower electrode, and the projection of the first part of the upper electrode on the lower electrode covers the projection of the semiconductor device on the lower electrode; and controlling a voltage difference generated between the upper electrode and the lower electrode to generate plasma in the reaction chamber, wherein the plasma is used for etching the semiconductor device, and the first part comprises a plurality of working areas, and the temperature of each working area is independently controlled. The invention solves the technical problems that partial channel holes in the channel hole area on a semiconductor device are small and are not etched enough, the connectivity and roundness of the channel holes are influenced, the uniformity of the whole channel holes is influenced, and the electrical performance of a three-dimensional memory is further influenced.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an etching method and an etching device of a semiconductor device.
Background
A NAND memory (NAND) is a better storage device than a hard disk drive, and has advantages of low power consumption, light weight, and the like, wherein the NAND memory of a three-dimensional (3D) structure has a high integration density and a large storage capacity due to three-dimensionally arranging memory cells on a substrate, and thus has been widely used in electronic products.
In the etching process of the semiconductor device, because the energy of different regions of a machine table is different, the amount of polymers on different regions is different, and the amount of the polymers brought onto the semiconductor device by different regions of the machine table is different, the phenomena that partial channel holes of the channel hole region on the semiconductor device are small and insufficient in etching are caused, the connectivity and roundness of the channel holes are influenced, the uniformity of the whole channel hole is influenced, and the electrical property of the three-dimensional memory is further influenced.
Disclosure of Invention
The invention aims to provide a three-dimensional memory and a preparation method thereof, and aims to solve the technical problems that partial channel holes in a channel hole region on a conductor device are small and are not etched enough, the connectivity and roundness of the channel holes are influenced, the uniformity of the whole channel holes is influenced, and the electrical performance of the three-dimensional memory is further influenced.
The invention provides an etching method of a semiconductor device, which comprises the following steps: providing a reaction chamber, wherein an upper electrode and a lower electrode arranged opposite to the upper electrode are arranged in the reaction chamber, and the upper electrode comprises a first part; conveying a semiconductor device into the reaction chamber, wherein the semiconductor device is positioned on the lower electrode, and the projection of the first part of the upper electrode on the lower electrode covers the projection of the semiconductor device on the lower electrode; and controlling a voltage difference generated between the upper electrode and the lower electrode to generate plasma in the reaction chamber, wherein the plasma is used for etching the semiconductor device, the first part comprises a plurality of working areas, and the temperature of each working area is independently controlled.
The plurality of working areas comprise a central working area and an annular working area, the annular working area is sleeved outside the central working area, the temperature of the central working area is independently controlled, and the temperature of the annular working area is independently controlled.
The annular working areas are multiple, the central working area is located in the annular working area, the annular working areas are sequentially sleeved in the direction of the central working area, and the temperature of each annular working area is independently controlled.
Wherein the semiconductor device includes a central portion and an edge portion surrounding the central portion; the central working region corresponds to a central portion of the semiconductor device, the annular working region corresponds to an edge portion of the semiconductor device, and the temperature of the central working region is lower than that of the annular working region.
The central working area comprises a plurality of first sub-modules which are distributed in a grid shape, and the temperature of each first sub-module is independently controlled.
The annular working area comprises a plurality of second sub-modules, the second sub-modules are distributed in a grid shape, and the temperature of each second sub-module is independently controlled.
The upper electrode also comprises a second part, the second part is sleeved outside the first part, and the temperature of the second part is independently controlled.
The invention provides an etching device of a semiconductor device, comprising: the semiconductor device is arranged in the reaction chamber and is arranged on the lower electrode, and the projection of the first part of the upper electrode on the lower electrode covers the projection of the semiconductor device on the lower electrode; the first part comprises a plurality of working areas, and the temperature of each working area is independently controlled.
The plurality of working areas comprise a central working area and an annular working area, the annular working area is sleeved outside the central working area, the temperature of the central working area is independently controlled, and the temperature of the annular working area is independently controlled.
The central working area comprises a plurality of first sub-modules which are distributed in a grid shape, and the temperature of each first sub-module is independently controlled; the annular working area comprises a plurality of second sub-modules which are distributed in a grid shape, and the temperature of each second sub-module is independently controlled.
To sum up, this application is through setting up the temperature independent control of every work area, can adjust the temperature difference of the different work areas of upper electrode, can adjust the ability that the different work areas of upper electrode brought the polymer to semiconductor device, can adjust the energy of the different areas of board and tend to unanimous or basically unanimous, it is the same or basically the same to adjust the amount of polymer on the different areas of board, the different areas of board is the same or basically the same with the amount that the polymer was brought to semiconductor device, the equal sculpture of the channel hole district on the semiconductor device is abundant, the connectivity and the circularity of channel hole are all better, whole channel hole distributes evenly, the electrical property of three-dimensional memory is better.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of the structure of an etching apparatus.
Fig. 2 is a schematic structural view of the upper electrode in fig. 1.
FIG. 3 is a graph of the energy distribution of the tool of FIG. 1.
Fig. 4 is a schematic cross-sectional view of a conventional channel hole.
Fig. 5 is a schematic top view of a conventional channel hole.
Fig. 6 is a schematic flow chart of an etching method of a semiconductor device according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a first structure of an upper electrode according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a second structure of the upper electrode according to the embodiment of the present invention.
Fig. 9 is a schematic diagram of a third structure of the upper electrode according to the embodiment of the present invention.
Fig. 10 is a schematic diagram of a fourth structure of the upper electrode according to the embodiment of the present invention.
Fig. 11 is a schematic diagram of a fifth structure of the upper electrode according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Before describing embodiments of the present invention, a conventional etching method of the semiconductor device 10 is first described. The process generally comprises the following steps:
referring to fig. 1-2, a reaction chamber 20 is provided, wherein an upper electrode 30 and a lower electrode 40 opposite to the upper electrode 30 are disposed in the reaction chamber 20, and the upper electrode 30 includes a first portion 50; conveying the semiconductor device 10 into the reaction chamber 20, wherein the semiconductor device 10 is located on the lower electrode 40, and the projection of the first part 50 of the upper electrode 30 on the lower electrode 40 covers the projection of the semiconductor device 10 on the lower electrode 40; a voltage difference is generated between the upper electrode 30 and the lower electrode 40 to generate a plasma within the reaction chamber 20, and the plasma is used to etch the semiconductor device 10.
Referring to fig. 3-5, the first portion 50 of the conventional upper electrode 30 is integral and at the same temperature. However, due to the inherent properties of the upper electrode 30 on the machine, the energy of the central region of the first portion 50 of the upper electrode 30 is higher than that of the other regions (fig. 3), which results in more polymer being generated in the central region, and the accumulation of more polymer results in more irregular surface topography of the mask 90 corresponding to the central portion of the semiconductor, such that the amount of polymer falling into the outer row holes 801 in the channel hole region is larger than that falling into the inner row holes 802, and the phenomena of smaller outer row holes 801 and insufficient etching (fig. 4-5) occur, which affects the connectivity and roundness of the outer row holes 801, affects the uniformity of the entire channel holes 80, forms a loading effect between the inner row holes 802 and the outer row holes 801, and further affects the electrical performance of the three-dimensional memory.
In view of the above problems, the present invention provides an etching method of the semiconductor device 10. Referring to fig. 6, fig. 6 is a flowchart illustrating an etching method for the semiconductor device 10 according to the present invention. This application is through setting up the temperature independent control of every work area, can adjust the temperature difference of the different work areas of upper electrode 30, can adjust the ability that the different work areas of upper electrode 30 brought the polymer to semiconductor device 10, can adjust the energy of the different areas of board and tend to unanimous or basically unanimous, it is the same or basically the same to adjust the amount of polymer on the different areas of board, the different areas of board is the same or basically the same with the amount that the polymer was brought to semiconductor device 10, the equal sculpture of channel hole 80 in channel hole region on semiconductor device 10 is abundant, the connectivity and the circularity of channel hole 80 are all better, whole channel hole 80 distributes evenly, the electrical property of three-dimensional memory is better. The etching method of the semiconductor device 10 includes S1, S2, S3. S1, S2 and S3 are described in detail as follows.
S1, providing a reaction chamber 20, wherein the reaction chamber 20 is provided with an upper electrode 30 and a lower electrode 40 disposed opposite to the upper electrode 30, and the upper electrode 30 includes a first portion 50.
S2, with continued reference to fig. 1, the semiconductor device 10 is transported into the reaction chamber 20, wherein the semiconductor device 10 is located on the lower electrode 40, and the projection of the first portion 50 of the upper electrode 30 on the lower electrode 40 covers the projection of the semiconductor device 10 on the lower electrode 40.
And S3, controlling a voltage difference generated between the upper electrode 30 and the lower electrode 40 to generate a plasma within the reaction chamber 20, the plasma being used to etch the semiconductor device 10, wherein the first portion 50 includes a plurality of working regions, and a temperature of each working region is independently controlled. It is understood that the reaction chamber 20 is filled with gas, and the gas is ionized to generate plasma by the voltage difference between the upper electrode 30 and the lower electrode 40.
Therefore, the temperature of each working area is independently controlled, the temperature difference of different working areas of the upper electrode 30 can be adjusted, the capacity of the polymer brought onto the semiconductor device 10 by the different working areas of the upper electrode 30 can be adjusted, the energy of different areas of the machine table can be adjusted to be consistent or basically consistent, the amount of the polymer in different areas of the machine table is adjusted to be the same or basically the same, the amount of the polymer brought onto the semiconductor device 10 by the different areas of the machine table is the same or basically the same, the channel holes 80 in the channel hole area on the semiconductor device 10 are fully etched, the penetration performance and the roundness of the channel holes 80 are better, the whole channel holes 80 are uniformly distributed, and the electrical performance of the three-dimensional memory is better.
Referring to FIG. 7, in one embodiment, the upper electrode 30 further includes a second portion 60, the second portion 60 is disposed outside the first portion 50, and the temperature of the second portion 60 is independently controlled. It will be appreciated that since the projection of the first portion 50 of the upper electrode 30 onto the lower electrode 40 overlaps the projection of the semiconductor device 10 onto the lower electrode 40, the space between the second portion 60 of the upper electrode 30 and the lower electrode 40 is free of the semiconductor device 10.
In the present application, the temperature of the second portion 60 of the upper electrode 30 is independently controlled, and the moving speed and the moving direction of the plasma in the reaction chamber 20 can be controlled, so that the plasma moves between the first portion 50 of the upper electrode 30 and the semiconductor device 10 as much as possible, thereby improving the utilization rate of the plasma and the etching efficiency of the semiconductor device 10.
It is understood that the semiconductor device 10 includes a substrate and a stacked structure disposed on the substrate, the stacked structure is a stack of alternately stacked insulating layers and gate sacrificial layers, and the channel holes 80 etched in the semiconductor device 10 penetrate through the stacked structure and expose the substrate. The stacked structure is a stack of alternately stacked insulating layers and gate sacrificial layers.
The material of the substrate is, for example, Silicon, but it may also be other Silicon-containing substrates, such as Silicon On Insulator (SOI), SiGe, Si: C, etc., and p-type/n-type or deep or shallow various potential wells required for the device may be formed in the substrate through ion implantation, etc. The stacked structure is a stack in which insulating layers and gate sacrificial layers are alternately stacked. Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable Deposition methods may be used to alternately deposit on the substrate in sequence. The insulating layer is made of, for example, silicon oxide, and the gate sacrificial layer is made of, for example, silicon nitride, which is replaced with a metal in a subsequent process to serve as a gate layer. In the present embodiment, the stacked structure is a 3-layer stacked structure of O/N/O (silicon oxide as an insulating layer and silicon nitride as a gate sacrificial layer). Of course, the stacked structure of the present invention is not limited to the above 3-layer structure, and may be other multi-layer structures different from 3 layers, particularly according to actual requirements. The insulating layer can also be silicon oxynitride, and the grid sacrificial layer can also be amorphous silicon, polysilicon, aluminum oxide, and the like. Channel holes 80 extend through the stack to the substrate.
With continued reference to fig. 7, in one embodiment, the plurality of working regions includes a central working region 501 and an annular working region 502, the annular working region 502 is disposed outside the central working region 501, the temperature of the central working region 501 is independently controlled, and the temperature of the annular working region 502 is independently controlled.
Therefore, the temperature of the central working area 501 and the annular working area 502 is independently controlled, the polymer amount on the semiconductor device 10 opposite to the central working area 501 of the upper electrode 30 can be independently controlled, the polymer amount on the semiconductor device 10 opposite to the annular working area 502 of the upper electrode 30 can be independently controlled, and further the etching condition of the channel holes 80 in the channel hole area on the semiconductor device 10 can be controlled, so that all the channel holes 80 on the semiconductor device 10 can be fully etched, the connectivity and the roundness of all the channel holes 80 are good, the whole channel holes 80 are uniformly distributed, and the electrical property of the three-dimensional memory is good.
In a particular embodiment, semiconductor device 10 includes a central portion and an edge portion surrounding the central portion; the central operating region 501 corresponds to a central portion of the semiconductor device 10, the annular operating region 502 corresponds to an edge portion of the semiconductor device 10, and the temperature of the central operating region 501 is lower than that of the annular operating region 502.
In the present application, the temperature of the central working area 501 is set to be lower than the temperature of the annular working area 502, the amount of the polymer on the central working area 501 of the upper electrode 30 can be reduced, so that the surface morphology of the mask 90 corresponding to the central part of the semiconductor is regular, the polymer is not accumulated in the central part of the semiconductor device 10, the amount of the polymer falling into the outer row holes 801 of the trench area is equal to or approximately equal to the amount of the polymer falling into the inner row holes 802, the etching of the outer row holes 801 of the trench area is sufficient, the size of the outer row holes 801 meets the requirements, the connectivity and the roundness of the outer row holes 801 are both good, the whole trench holes 80 are uniformly distributed, the load effect between the inner row holes 802 and the outer row holes 801 is not formed, and the electrical performance of.
Referring to fig. 8, in one embodiment, a plurality of annular working areas 502 are provided, the plurality of annular working areas 502 are sequentially sleeved in a direction from the central working area 501 to the annular working area 502, and the temperatures of the plurality of annular working areas 502 are independently controlled.
In the present application, the temperature of each annular working region 502 is independently controlled, the temperature of each annular working region 502 can be independently controlled according to the etching requirements of different parts of the semiconductor device 10 and according to the inherent properties of the machine, and if the temperature of each annular working region 502 can be set to be consistent or inconsistent, so that fewer polymers fall into each channel hole 80 of the semiconductor device 10 corresponding to the annular working region 502, the etching of each channel hole 80 of each part is sufficient, the connectivity and the roundness of each channel hole 80 are good, the distribution of the whole channel holes 80 is uniform, and the electrical performance of the three-dimensional memory is good.
Referring to fig. 9, in a specific embodiment, the central working area 501 includes a plurality of first sub-modules 501a, the plurality of first sub-modules 501a are distributed in a grid shape, and the temperature of each first sub-module 501a is independently controlled. That is, the central working area 501 may be divided into a plurality of first sub-modules 501a, and the temperatures of the plurality of first sub-modules 501a are not interfered with each other and can be independently controlled, so that further fine control of the temperature of the central working area 501 of the upper electrode 30 is realized, and the amount of the polymer falling into each channel hole 80 can be controlled in a targeted manner.
Therefore, the temperature of each first sub-module 501a of the upper electrode 30 can be further finely controlled according to the etching requirement of the channel holes 80 on the semiconductor device 10, so that less polymer falls into each channel hole 80 corresponding to the first sub-module 501a, less polymer falls into the outer row of holes 801, or no polymer falls into the outer row of holes 801, the outer row of holes 801 are fully etched, the size of the outer row of holes 801 meets the requirement, the connectivity and the roundness of the outer row of holes 801 are better, the whole channel holes 80 are uniformly distributed, the load effect between the inner row of holes 802 and the outer row of holes 801 cannot be formed, and the electrical performance of the three-dimensional memory is better.
Referring to fig. 10, in one embodiment, the annular working area 502 includes a plurality of second sub-modules 502a, the plurality of second sub-modules 502a are distributed in a grid, and the temperature of each second sub-module 502a is independently controlled. That is, the annular working area 502 may be divided into a plurality of second sub-modules 502a, and the temperatures of the plurality of second sub-modules 502a are not interfered with each other and can be independently controlled, so as to further finely control the temperature of the annular working area 502 of the upper electrode 30, and to purposefully control the amount of the polymer falling into each of the channel holes 80.
Therefore, the temperature of each second sub-module 502a of the upper electrode 30 can be further finely controlled according to the etching requirements of the channel holes 80 on the semiconductor device 10, so that less polymer falls into each channel hole 80 corresponding to the second sub-module 502a, the connectivity and the roundness of each channel hole 80 are better, the distribution of the whole channel holes 80 is uniform, and the electrical performance of the three-dimensional memory is better.
Referring to fig. 11, it is understood that the central working area 501 may have a plurality of first sub-modules 501a, and the annular working area 502 may have a plurality of second sub-modules 502a, so that the amount of polymer falling into each channel hole 80 may be controlled, the connectivity and roundness of each channel hole 80 are good, the distribution of the whole channel holes 80 is uniform, and the electrical performance of the three-dimensional memory is good.
Except for the etching method of the semiconductor device 10 described above. The invention also provides an etching device of the semiconductor device 10.
The etching device comprises: the semiconductor device comprises a reaction chamber 20, an upper electrode 30 and a lower electrode 40, wherein the upper electrode 30 and the lower electrode 40 are arranged in the reaction chamber 20, the upper electrode 30 and the lower electrode 40 are arranged oppositely, the semiconductor device 10 is arranged in the reaction chamber 20 and is arranged on the lower electrode 40, and the projection of a first part 50 of the upper electrode 30 on the lower electrode 40 covers the projection of the semiconductor device 10 on the lower electrode 40; the first portion 50 includes a plurality of working regions, each of which is independently temperature controlled, for generating a voltage difference between the upper electrode 30 and the lower electrode 40 to generate a plasma for etching the semiconductor device 10 in the reaction chamber 20.
The utility model provides an etching device is through setting up the temperature independent control of every work area, can adjust the temperature difference of the different work areas of upper electrode 30, can adjust the ability of the different work areas of upper electrode 30 with the polymer on taking semiconductor device 10, can adjust the energy of the different areas of board and tend to unanimous or basically unanimous, the quantity of adjusting the polymer on the different areas of board is the same or basically the same, the different areas of board is the same or basically the same with the quantity that the polymer was taken on semiconductor device 10, the equal sculpture of channel hole 80 in the channel hole region on semiconductor device 10 is abundant, the connectivity and the circularity of channel hole 80 are all better, whole channel hole 80 distributes evenly, the electrical property of three-dimensional memory is better.
In a specific embodiment, the plurality of working regions includes a central working region 501 and an annular working region 502, the annular working region 502 is sleeved outside the central working region 501, the temperature of the central working region 501 is independently controlled, and the temperature of the annular working region 502 is independently controlled.
The temperature of the central working area 501 and the temperature of the annular working area 502 of the upper electrode 30 of the etching device are independently controlled, the polymer amount on the semiconductor device 10 opposite to the central working area 501 of the upper electrode 30 can be independently controlled, the polymer amount on the semiconductor device 10 opposite to the annular working area 502 of the upper electrode 30 can be independently controlled, and further the etching condition of the channel holes 80 in the channel hole area on the semiconductor device 10 can be controlled, so that all the channel holes 80 on the semiconductor device 10 are fully etched, the connectivity and the roundness of all the channel holes 80 are good, the whole channel holes 80 are uniformly distributed, and the electrical property of the three-dimensional memory is good.
In a specific embodiment, the central working area 501 includes a plurality of first sub-modules 501a, the plurality of first sub-modules 501a are distributed in a grid shape, and the temperature of each first sub-module 501a is independently controlled; the annular working area 502 includes a plurality of second sub-modules 502a, the plurality of second sub-modules 502a are distributed in a grid shape, and the temperature of each second sub-module 502a is independently controlled.
The etching device can further finely control the temperature of each first sub-module 501a of the upper electrode 30 according to the etching requirements of the channel holes 80 on the semiconductor device 10, so that less polymer falls into each channel hole 80 corresponding to the first sub-module 501a, less polymer falls into the outer row of holes 801, or no polymer falls into the outer row of holes 801, the outer row of holes 801 are fully etched, the size of the outer row of holes 801 meets the requirements, the connectivity and the roundness of the outer row of holes 801 are better, the whole channel holes 80 are uniformly distributed, the load effect between the inner row of holes 802 and the outer row of holes 801 cannot be formed, and the electrical property of the three-dimensional memory is better.
The etching device can further finely control the temperature of each second sub-module 502a of the upper electrode 30 according to the etching requirements of the channel holes 80 on the semiconductor device 10, so that less polymer falls into each channel hole 80 corresponding to the second sub-module 502a, the connectivity and the roundness of each channel hole 80 are better, the whole channel holes 80 are uniformly distributed, and the electrical property of the three-dimensional memory is better.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A method for etching a semiconductor device, comprising:
providing a reaction chamber, wherein an upper electrode and a lower electrode arranged opposite to the upper electrode are arranged in the reaction chamber, and the upper electrode comprises a first part;
conveying a semiconductor device into the reaction chamber, wherein the semiconductor device is positioned on the lower electrode, and the projection of the first part of the upper electrode on the lower electrode covers the projection of the semiconductor device on the lower electrode;
and controlling a voltage difference generated between the upper electrode and the lower electrode to generate plasma in the reaction chamber, wherein the plasma is used for etching the semiconductor device, the first part comprises a plurality of working areas, and the temperature of each working area is independently controlled.
2. The etching method according to claim 1, wherein the plurality of working regions comprise a central working region and an annular working region, the annular working region is sleeved outside the central working region, the temperature of the central working region is independently controlled, and the temperature of the annular working region is independently controlled.
3. The etching method according to claim 2, wherein the number of the annular working areas is plural, the plural annular working areas are sequentially sleeved in a direction from the central working area to the annular working area, and the temperature of each annular working area is independently controlled.
4. The etching method according to claim 2, wherein the semiconductor device includes a center portion and an edge portion surrounding the center portion; the central working region corresponds to a central portion of the semiconductor device, the annular working region corresponds to an edge portion of the semiconductor device, and the temperature of the central working region is lower than that of the annular working region.
5. The etching method according to claim 2, wherein the central working area comprises a plurality of first sub-modules, the plurality of first sub-modules are distributed in a grid shape, and the temperature of each first sub-module is independently controlled.
6. The etching method according to claim 2, wherein the annular working area comprises a plurality of second sub-modules, the plurality of second sub-modules are distributed in a grid shape, and the temperature of each second sub-module is independently controlled.
7. The etching method according to claim 1, wherein the upper electrode further comprises a second portion, the second portion is sleeved outside the first portion, and the temperature of the second portion is independently controlled.
8. An etching apparatus for a semiconductor device, comprising: the semiconductor device is arranged in the reaction chamber and is arranged on the lower electrode, and the projection of the first part of the upper electrode on the lower electrode covers the projection of the semiconductor device on the lower electrode; the first part comprises a plurality of working areas, and the temperature of each working area is independently controlled.
9. The etching apparatus according to claim 8, wherein the plurality of working regions includes a central working region and an annular working region, the annular working region is sleeved outside the central working region, the temperature of the central working region is independently controlled, and the temperature of the annular working region is independently controlled.
10. The etching apparatus according to claim 8, wherein the central working area comprises a plurality of first sub-modules, the plurality of first sub-modules are distributed in a grid shape, and the temperature of each first sub-module is independently controlled; the annular working area comprises a plurality of second sub-modules which are distributed in a grid shape, and the temperature of each second sub-module is independently controlled.
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