CN112233981A - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

Info

Publication number
CN112233981A
CN112233981A CN202011089159.7A CN202011089159A CN112233981A CN 112233981 A CN112233981 A CN 112233981A CN 202011089159 A CN202011089159 A CN 202011089159A CN 112233981 A CN112233981 A CN 112233981A
Authority
CN
China
Prior art keywords
region
regions
doped
barrier
type transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011089159.7A
Other languages
English (en)
Inventor
田武
孙超
王欣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN202011089159.7A priority Critical patent/CN112233981A/zh
Publication of CN112233981A publication Critical patent/CN112233981A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种半导体器件及其制备方法，其包括如下步骤：提供基底层，基底层上设置有栅极，基底层内设置有源极区域、漏极区域及沟道区，栅极与沟道区对应，源极区域及漏极区域设置在栅极两侧；在基底层上，在源极区域与栅极之间的待掺杂区上及漏极区域与栅极之间的待掺杂区上形成图形化的阻挡层，阻挡层间隔遮挡部分待掺杂区；对待掺杂区进行掺杂，形成轻掺杂区。本发明在需要降低轻掺杂区的掺杂剂量的区域(宽管子区域)形成阻挡层，通过阻挡层遮挡作用降低该区域掺杂剂量，从而避免不需要降低轻掺杂区的掺杂剂量的区域(窄管子区域)掺杂剂量也被降低，既能够避免宽管子漏电流产生，又能够避免窄管子击穿电压受影响，方法简单可行。

Description

半导体器件及其制备方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体器件及其制备方法。
背景技术
在当前3D-NAND电路设计中，大量的超高电压N型金属氧化物半导体(UHV NMOS)器件被用来产生和传递电压给核心阵列，并对其进行编程和擦除操作。为了获得大的电流驱动能力，经常会使用一些宽的超高电压N型金属氧化物半导体器件。但是由于需要兼顾好的衬偏特性，这些超高电压N型金属氧化物半导体器件的阈值电压(VT)和阱的离子注入(IMP)一般都比较小。因此，在高压off状态的时候很容易因贯穿而出现大的漏电流。
如何避免半导体器件漏电流的产生，成为目前亟需解决的技术问题。
发明内容
本发明所要解决的技术问题是，如何避免半导体器件漏电流的产生。
为了解决上述问题，本发明提供了一种半导体器件的制备方法，其包括如下步骤：提供一基底层，所述基底层上设置有栅极，所述基底层内设置有源极区域、漏极区域及沟道区，所述栅极与所述沟道区对应，所述源极区域及漏极区域设置在所述栅极两侧；在所述基底层上，在所述源极区域与所述栅极之间的待掺杂区上及所述漏极区域与所述栅极之间的待掺杂区上形成图形化的阻挡层，所述阻挡层间隔遮挡部分所述待掺杂区；对所述待掺杂区进行掺杂，形成轻掺杂区。
可选地，所述阻挡层包括阻挡区及镂空区，所述阻挡区与所述镂空区交替排列，所述镂空区暴露出所述基底层。
可选地，所述阻挡层包括多个间隔设置的阻挡条，所述阻挡条作为所述阻挡区，相邻所述阻挡条之间的间隙作为所述镂空区。
可选地，所述阻挡层包括多个间隔设置的同心阻挡环，所述阻挡环作为所述阻挡区，相邻所述阻挡环之间的间隙作为所述镂空区。
可选地，所述阻挡层包括多个矩阵排列的阻挡块，所述阻挡块作为所述阻挡区，相邻所述阻挡块之间的间隙作为所述镂空区。
可选地，所述阻挡条或所述阻挡环或所述阻挡块的宽度为60nm～0.5μm。
可选地，在形成所述阻挡层之前对所述源极区域及漏极区域进行掺杂，形成源区及漏区。
可选地，在形成所述轻掺杂区之后或者之前对所述源极区域及漏极区域进行掺杂，形成源区及漏区。
可选地，所述半导体器件包括第一类型晶体管及第二类型晶体管，所述第一类型晶体管的沟道区宽度大于所述第二类型晶体管的沟道区宽度，所述阻挡层仅形成在第一类型晶体管的待掺杂区上。
本发明还提供一种采用上述的制备方法制备的半导体器件，其包括：基底层；栅极，设置在所述基底层上；源极及漏极，设置在所述基底层内，且位于所述栅极两侧，沟道区，设置在所述基底层内，与所述栅极对应；轻掺杂区，设置在所述基底层内，且位于所述源极与所述栅极之间及所述漏极与所述栅极之间；图形化的阻挡层，设置在所述基底层上，且间隔遮挡部分所述轻掺杂区。
可选地，所述半导体器件包括第一类型晶体管及第二类型晶体管，所述第一类型晶体管的沟道区宽度大于所述第二类型晶体管的沟道区宽度，所述阻挡层仅形成在第一类型晶体管的待掺杂区上，所述第一类型晶体管的轻掺杂区的掺杂浓度小于所述第二类型晶体管的轻掺杂区的掺杂浓度。
本发明的优点在于，在需要降低轻掺杂区的掺杂剂量的区域(宽管子区域)形成阻挡层，通过阻挡层的遮挡作用降低该区域的掺杂剂量，而不是通过调整离子注入设备的离子注入剂量来降低该区域的掺杂剂量，从而避免不需要降低轻掺杂区的掺杂剂量的区域(窄管子区域)的掺杂剂量也被降低，本发明既能够避免宽管子漏电流产生，又能够避免窄管子的击穿电压受到影响，且不会额外增大半导体器件的尺寸及工艺，方法简单可行。
附图说明
图1是本发明第一实施例的半导体器件的制备方法的步骤示意图；
图2A～图2D是本发明第一实施例的半导体器件的制备方法的各个步骤中半导体结构的截面示意图；
图3是图2C所示结构的俯视示意图；
图4是本发明制备方法第二实施例的半导体结构的俯视示意图；
图5是本发明制备方法第三实施例的半导体结构的俯视示意图；
图6是本发明制备方法第四实施例的半导体结构的俯视示意图；
图7是本发明制备方法第五实施例的半导体结构的俯视示意图；
图8是本发明制备方法第六实施例的半导体结构的俯视示意图；
图9是本发明制备方法第七实施例的半导体结构的俯视示意图。
具体实施方式
下面结合附图对本发明提供的半导体器件及其制备方法的实施例做详细说明。
如背景技术所述，为了获得大的电流驱动能力，经常会使用一些宽的超高电压N型金属氧化物半导体器件来产生和传递电压给核心阵列，并对其进行编程和擦除操作。但是由于需要兼顾好的衬偏特性，这些超高电压N型金属氧化物半导体器件的阈值电压(VT)和阱的离子注入(IMP)一般都比较小，因此，在高压off状态的时候很容易因贯穿而出现大的漏电流。
现有技术中，改善漏电流的方法有：一、增加沟道区的长度(channel length)，但是，会导致芯片尺寸增加，单位成本上升；二、增加阱的离子注入浓度，但是，会导致体效应发生变化，使得电压传输效率降低；3)降低轻掺杂区(LDD)的掺杂剂量或者离子注入的深度，但是，会导致其他窄管子的击穿电压(BVDS)受到影响。可见，现有技术中改善漏电流的方法均存在缺陷。
因此，本发明提供一种半导体器件及其制备方法，其能够改善漏电流，且能够避免上述缺陷。
图1是本发明第一实施例的半导体器件的制备方法的步骤示意图，图2A～图2D是本发明第一实施例的半导体器件的制备方法的各个步骤中半导体结构的截面示意图。
请参阅步骤S10及图2A，提供一基底层100，所述基底层100上设置有栅极110，所述基底层100内设置有源极区域101、漏极区域102及沟道区120，所述栅极110与所述沟道区120对应，所述源极区域101及漏极区域102设置在所述栅极110两侧。
所述基底层100的构成材料可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，所述基底层100的构成材料选用单晶硅。
在所述基底层100中，所述栅极110下方区域为所述沟道区120，即所述基底层100被所述栅极110遮挡的区域为所述沟道区120。所述源极区域101及漏极区域102虽然设置在所述栅极110两侧，但是，所述源极区域101及漏极区域102与所述栅极100之间具有一定间距，而并非是接触设置。所述源极区域101与所述栅极110之间为待掺杂区103，所述漏极区域102与所述栅极110之间也为待掺杂区104。所述待掺杂区103及104在后续步骤中被掺杂而形成轻掺杂区。
其中，可对所述源极区域101及漏极区域102进行掺杂，而形成源极及漏极。在本实施例中，在该步骤之后，在形成阻挡层150(参见图2C)的步骤之前，对所述源极区域101及漏极区域102进行掺杂。
具体地说，请参阅步骤S11及图2B，对所述源极区域101及漏极区域102进行掺杂，形成源极130及漏极140。其中，掺杂的方法可为离子注入(IMP)，注入的离子可根据后续形成的晶体管的类型选择。例如，后续若要形成NMOS，则在该步骤中，可对所述源极区域101及漏极区域102进行As、P或Sb离子注入，形成源极130及漏极140；后续若要形成PMOS，可对所述源极区域101及漏极区域102进行B离子注入，形成源极130及漏极140。
而在本发明其它实施例中，也可在形成阻挡层之后，形成轻掺杂层的步骤之前或者形成轻掺杂层的步骤之后，对所述源极区域101及漏极区域102进行掺杂，形成源极及漏极。
请参阅步骤S12及图2C，在所述基底层100上，在所述源极区域101与所述栅极110之间的待掺杂区103上及所述漏极区域102与所述栅极110之间的待掺杂区104上形成图形化的阻挡层150，所述阻挡层150间隔遮挡部分所述待掺杂区103及104。
所述阻挡层150间隔遮挡部分所述待掺杂区103及104是指所述阻挡层150具有图案，其能够遮挡部分所述待掺杂区103及104，也暴露出部分所述待掺杂区103及104。具体地说，请参阅图3，其为图2C所示结构的俯视示意图，所述阻挡层150包括阻挡区151及镂空区152，所述阻挡区151与所述镂空区152交替排列，所述阻挡区151遮挡所述基底层100的待掺杂区103及104，所述镂空区152暴露出所述基底层100的所述待掺杂区103及104，使得所述待掺杂区103及104的部分区域被遮挡，部分区域未被遮挡。
进一步，在该步骤中，可首先在所述基底层100上形成阻挡材料层，再采用光刻及刻蚀工艺图形化所述阻挡材料层，以形成所述图形化的阻挡层150。在本实施例中，所述阻挡层150的材料为多晶硅，在本发明其它实施例中，所述阻挡层150也可为其他材料，只要能够对后续的离子注入实现遮挡作用即可。
请参阅步骤S13及图2D，对所述待掺杂区103及104进行掺杂，形成轻掺杂区160及170。其中，可采用离子注入工艺对所述待掺杂区103及104进行掺杂，注入的离子类型与形成源极及漏极的离子类型相同，只是两者浓度不同，所述轻掺杂区160及170的掺杂浓度小于所述源极及漏极的掺杂浓度。
在该步骤中，在未被所述阻挡层150遮挡的区域(即所述镂空区152)，离子能够注入待掺杂区103及104，并在所述待掺杂区103及104内扩散，形成轻掺杂区163及170，而在被所述阻挡层150遮挡的区域(即阻挡区151)，离子注入被阻挡，并未注入所述待掺杂区103及104，使得在注入设备提供的相同的离子注入剂量下，注入所述待掺杂区103及104的离子剂量减少，使得轻掺杂区160及170的掺杂浓度降低，则在相同电压下，漏区耗尽速度变慢，源区与漏区的耗尽层不容易连接，从而不易出现贯穿的现象，改善了漏电流，提高了半导体器件的电学性能。
进一步，如图3所示，在第一实施例中，所述阻挡层150包括多个间隔设置的阻挡条，所述阻挡条作为所述阻挡区151，相邻所述阻挡条之间的间隙作为所述镂空区152。其中，所述阻挡条之间的间隔(即所述镂空区150的宽度)可根据所述待掺杂区域103及104需要的掺杂浓度决定。若所述待掺杂区域103及104需要的掺杂浓度高，则增大所述阻挡条之间的间隔，若所述待掺杂区域103及104需要的掺杂浓度低，则减小所述阻挡条之间的间隔。所述阻挡条(即所述阻挡区151)的宽度也可根据所述待掺杂区域103及104需要的掺杂浓度决定。进一步，所述阻挡条的宽度为60nm～0.5μm。
进一步，在第一实施例中，所述阻挡条沿所述沟道区120宽度方向设置，而在本发明其他实施例中，例如，请参阅图4，在第二实施例中，所述阻挡条沿所述沟道区120的长度方向设置，请参阅图5，在第三实施例中，所述阻挡条倾斜设置；请参阅图6，在第四实施例中，所述阻挡条沿不同的方向设置。上述仅用于示例所述阻挡条的排布方式，可以理解的是，所述阻挡条还可采用其他的排布方式。
在上述实施例中，所述阻挡区151由阻挡条构成，在本发明第五实施例中，所述阻挡区由多个间隔设置的同心阻挡环构成。具体地说，请参阅图7，多个阻挡环153同心设置，所述阻挡环153作为所述阻挡区，用于遮挡所述待掺杂区103及104，相邻所述阻挡区153之间的间隙154作为所述镂空区，暴露出所述待掺杂区103及104。
在本发明第六实施例中，所述阻挡区也可有多个矩阵排列的阻挡块构成。具体地说，请参阅图8，多个阻挡块155阵列排列，所述阻挡块155作为所述阻挡区，用于遮挡所述待掺杂区103及104，相邻的所述阻挡块155之间的间隙156作为所述镂空区，暴露出所述待掺杂区103及104。
相较于现有技术中直接通过调整离子注入设备的离子注入剂量来降低轻掺杂区(LDD)的掺杂剂量而言，本发明的制备方法在需要降低轻掺杂区的掺杂剂量的区域(宽管子区域)形成阻挡层，通过阻挡层的遮挡作用降低该区域的掺杂剂量，而不是通过调整离子注入设备的离子注入剂量来降低该区域的掺杂剂量，从而避免不需要降低轻掺杂区的掺杂剂量的区域(窄管子区域)的掺杂剂量也被降低，本发明既能够避免宽管子漏电流产生，又能够避免窄管子的击穿电压受到影响，且不会额外增大半导体器件的尺寸及工艺，方法简单可行。
进一步，本发明还提供一第七实施例。请参阅图9，其为本发明第七实施例的半导体结构的俯视示意图，所述半导体器件包括第一类型晶体管100A及第二类型晶体管100B。所述第一类型晶体管100A包括第一栅极110A、第一源极130A、第一漏极140A及第一沟道区120A，所述第二类型晶体管100B包括第二栅极110B、第二源极130B、第二140B及第二沟道区120B。其中，所述第一类型晶体管100A的第一沟道区120A的宽度W1大于所述第二类型晶体管100B的第二沟道区120B的宽度W2。所述阻挡层150仅形成在所述第一类型晶体管100A的轻掺杂区160A及170A对应区域，并未形成在所述第二类型晶体管100B的轻掺杂区160B及170B对应区域，使得所述第一类型晶体管100A的轻掺杂区160A及170A掺杂浓度小于所述第二类型晶体管100B的轻掺杂区160B及170B的掺杂浓度，本发明既能够避免第一类型晶体管100A(宽管子)漏电流的产生，又能够避免第二类型晶体管100B(窄管子)的击穿电压受到影响，且不会额外增大半导体器件的尺寸及工艺，方法简单可行。
本发明还提供一种采用上述制备方法制备的半导体器件。请参阅图2D，所述半导体器件包括基底层100、栅极110、源极130、漏极140、沟道区120、轻掺杂区160及170、图形化的阻挡层150。
所述栅极110设置在所述基底层100上；所述源极130及漏极140设置在所述基底层100内，且位于所述栅极110两侧；所述沟道区120设置在所述基底层110内，与所述栅极110对应；所述轻掺杂区160及170设置在所述基底层100内，且位于所述源极130与所述栅极110之间及所述漏极140与所述栅极110之间；图形化的阻挡层150设置在所述基底层100上，且间隔遮挡部分所述轻掺杂区160及170。其中，所述阻挡层150的排布如图3～图8所示，不再赘述。
进一步，所述半导体器件包括第一类型晶体管及第二类型晶体管。具体地说，请参阅图9，所述半导体器件包括第一类型晶体管100A及第二类型晶体管100B。所述第一类型晶体管100A包括第一栅极110A、第一源极130A、第一漏极140A及第一沟道区120A，所述第二类型晶体管100B包括第二栅极110B、第二源极130B、第二140B及第二沟道区120B。
其中，所述第一类型晶体管100A的第一沟道区120A的宽度W1大于所述第二类型晶体管100B的第二沟道区120B的宽度W2。所述阻挡层150仅形成在所述第一类型晶体管100A的轻掺杂区160A及170A对应区域，并未形成在所述第二类型晶体管100B的轻掺杂区160B及170B对应区域，使得所述第一类型晶体管100A的轻掺杂区160A及170A掺杂浓度小于所述第二类型晶体管100B的轻掺杂区160B及170B的掺杂浓度。
本发明半导体器件既能够避免第一类型晶体管100A(宽管子)漏电流的产生，又能够避免第二类型晶体管100B(窄管子)的击穿电压受到影响，且不会额外增大半导体器件的尺寸及工艺，方法简单可行。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (11)

1.一种半导体器件的制备方法，其特征在于，包括如下步骤：
提供一基底层，所述基底层上设置有栅极，所述基底层内设置有源极区域、漏极区域及沟道区，所述栅极与所述沟道区对应，所述源极区域及漏极区域设置在所述栅极两侧；
在所述基底层上，在所述源极区域与所述栅极之间的待掺杂区上及所述漏极区域与所述栅极之间的待掺杂区上形成图形化的阻挡层，所述阻挡层间隔遮挡部分所述待掺杂区；
对所述待掺杂区进行掺杂，形成轻掺杂区。
2.根据权利要求1所述的半导体器件的制备方法，其特征在于，所述阻挡层包括阻挡区及镂空区，所述阻挡区与所述镂空区交替排列，所述镂空区暴露出所述基底层。
3.根据权利要求2所述的半导体器件的制备方法，其特征在于，所述阻挡层包括多个间隔设置的阻挡条，所述阻挡条作为所述阻挡区，相邻所述阻挡条之间的间隙作为所述镂空区。
4.根据权利要求2所述的半导体器件的制备方法，其特征在于，所述阻挡层包括多个间隔设置的同心阻挡环，所述阻挡环作为所述阻挡区，相邻所述阻挡环之间的间隙作为所述镂空区。
5.根据权利要求2所述的半导体器件的制备方法，其特征在于，所述阻挡层包括多个矩阵排列的阻挡块，所述阻挡块作为所述阻挡区，相邻所述阻挡块之间的间隙作为所述镂空区。
6.根据权利要求2～5任意一项所述的半导体器件的制备方法，其特征在于，所述阻挡区的宽度为60nm～0.5μm。
7.根据权利要求1所述的半导体器件的制备方法，其特征在于，在形成所述阻挡层之前对所述源极区域及漏极区域进行掺杂，形成源区及漏区。
8.根据权利要求1所述的半导体器件的制备方法，其特征在于，在形成所述轻掺杂区之后或者之前对所述源极区域及漏极区域进行掺杂，形成源区及漏区。
9.根据权利要求1所述的半导体器件的制备方法，其特征在于，所述半导体器件包括第一类型晶体管及第二类型晶体管，所述第一类型晶体管的沟道区宽度大于所述第二类型晶体管的沟道区宽度，所述阻挡层仅形成在第一类型晶体管的待掺杂区上。
10.一种采用权利要求1～8任意一项所述的制备方法制备的半导体器件，其特征在于，包括：
基底层；
栅极，设置在所述基底层上；
源极及漏极，设置在所述基底层内，且位于所述栅极两侧，
沟道区，设置在所述基底层内，与所述栅极对应；
轻掺杂区，设置在所述基底层内，且位于所述源极与所述栅极之间及所述漏极与所述栅极之间；
图形化的阻挡层，设置在所述基底层上，且间隔遮挡部分所述轻掺杂区。
11.根据权利要求10所述的半导体器件，其特征在于，所述半导体器件包括第一类型晶体管及第二类型晶体管，所述第一类型晶体管的沟道区宽度大于所述第二类型晶体管的沟道区宽度，所述阻挡层仅形成在第一类型晶体管的待掺杂区上，所述第一类型晶体管的轻掺杂区的掺杂浓度小于所述第二类型晶体管的轻掺杂区的掺杂浓度。
CN202011089159.7A 2020-10-13 2020-10-13 半导体器件及其制备方法 Pending CN112233981A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011089159.7A CN112233981A (zh) 2020-10-13 2020-10-13 半导体器件及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011089159.7A CN112233981A (zh) 2020-10-13 2020-10-13 半导体器件及其制备方法

Publications (1)

Publication Number Publication Date
CN112233981A true CN112233981A (zh) 2021-01-15

Family

ID=74112351

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011089159.7A Pending CN112233981A (zh) 2020-10-13 2020-10-13 半导体器件及其制备方法

Country Status (1)

Country Link
CN (1) CN112233981A (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6320236B1 (en) * 1999-10-06 2001-11-20 Advanced Micro Devices, Inc. Optimization of logic gates with criss-cross implants to form asymmetric channel regions
CN101226962A (zh) * 2008-02-22 2008-07-23 谭健 Hvmos及集成hvmos与cmos的半导体器件
CN203826346U (zh) * 2014-04-25 2014-09-10 鄂尔多斯市源盛光电有限责任公司 一种掩膜板及离子注入设备
CN104183635A (zh) * 2013-05-28 2014-12-03 北京天元广建科技研发有限责任公司 一种场效应晶体管
US20160308072A1 (en) * 2015-04-15 2016-10-20 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device having edge termination structure including high-concentration region and low-concentration region
CN110649101A (zh) * 2019-10-18 2020-01-03 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN112786450A (zh) * 2019-11-06 2021-05-11 京东方科技集团股份有限公司 晶体管及其制备方法、阵列基板及其制备方法、显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6320236B1 (en) * 1999-10-06 2001-11-20 Advanced Micro Devices, Inc. Optimization of logic gates with criss-cross implants to form asymmetric channel regions
CN101226962A (zh) * 2008-02-22 2008-07-23 谭健 Hvmos及集成hvmos与cmos的半导体器件
CN104183635A (zh) * 2013-05-28 2014-12-03 北京天元广建科技研发有限责任公司 一种场效应晶体管
CN203826346U (zh) * 2014-04-25 2014-09-10 鄂尔多斯市源盛光电有限责任公司 一种掩膜板及离子注入设备
US20160308072A1 (en) * 2015-04-15 2016-10-20 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device having edge termination structure including high-concentration region and low-concentration region
CN110649101A (zh) * 2019-10-18 2020-01-03 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN112786450A (zh) * 2019-11-06 2021-05-11 京东方科技集团股份有限公司 晶体管及其制备方法、阵列基板及其制备方法、显示面板

Similar Documents

Publication Publication Date Title
US8174071B2 (en) High voltage LDMOS transistor
US5510279A (en) Method of fabricating an asymmetric lightly doped drain transistor device
US8450156B2 (en) Method for producing a thyristor
US9704756B2 (en) Methods of manufacturing semiconductor devices
KR100460553B1 (ko) 절연 게이트형 반도체 장치 제조 방법
US5362982A (en) Insulated gate FET with a particular LDD structure
US20140008733A1 (en) Drain extended mos device for bulk finfet technology
US7521741B2 (en) Shielding structures for preventing leakages in high voltage MOS devices
US20080217693A1 (en) Structure to improve MOS transistor on-breakdown voltage and method of making the same
US7550804B2 (en) Semiconductor device and method for forming the same
US8889518B2 (en) LDMOS transistor with asymmetric spacer as gate
JP2009290211A (ja) 半導体素子及びその製造方法
CN111029408A (zh) 一种集成esd的vdmos器件及制备方法
US11652167B2 (en) Semiconductor device having junction termination structure and method of formation
US5623154A (en) Semiconductor device having triple diffusion
US20120161235A1 (en) Electrostatic discharge protection device and manufacturing method thereof
CN112233981A (zh) 半导体器件及其制备方法
US6130133A (en) Fabricating method of high-voltage device
KR100587605B1 (ko) 고전압 트랜지스터 및 그 제조방법
US20130285147A1 (en) Compact tid hardening nmos device and fabrication process
TWI798825B (zh) 半導體元件的製造方法
CN111243956B (zh) 半导体制作工艺
KR100211762B1 (ko) 반도체 메모리 장치 및 그 제조방법
KR100859482B1 (ko) 반도체 소자 및 그 제조방법
CN109712890B (zh) 一种半导体器件的制造方法及半导体器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210115

RJ01 Rejection of invention patent application after publication