CN112201618A - Method for optimizing quality of cushion layer - Google Patents
Method for optimizing quality of cushion layer Download PDFInfo
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- CN112201618A CN112201618A CN202011061130.8A CN202011061130A CN112201618A CN 112201618 A CN112201618 A CN 112201618A CN 202011061130 A CN202011061130 A CN 202011061130A CN 112201618 A CN112201618 A CN 112201618A
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- layer
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- groove structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
Abstract
The invention provides a method for optimizing the quality of a liner layer, which comprises the steps of providing a dielectric layer with a groove structure, and sequentially depositing a diffusion barrier layer and a thin liner layer in the groove structure; carrying out physical vapor deposition on the thin liner layer by using a metal material, removing impurities in the thin liner layer to densify the thin liner layer, and simultaneously forming a metal thin layer on the thin liner layer; depositing a copper seed crystal layer in the groove structure; filling copper in the groove structure; the upper surface of the groove structure is chemically and mechanically polished to remove the exposed copper and polished until the dielectric layer is exposed. The invention improves the copper interconnection process, and the thin layer liner layer in the groove of the dielectric layer is subjected to physical vapor deposition by using a metal material and bombards the thin layer liner layer by using a high-bias condition to remove impurities in the thin layer liner layer, so that the thin layer liner layer is more densified, the film forming quality of the thin layer liner layer is effectively improved, and the contact resistance of the contact hole is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for optimizing the quality of a liner layer.
Background
As metal copper line dimensions shrink, Electromigration (EM) becomes more challenging. The Electromigration (EM) is enhanced by using a Cu alloy seed (Cu alloy seed) at 28nm, which has no impact on the process flow, but the copper wire resistance is increased. Below the 20nm technology node, in order to reduce the resistance and change back to pure copper seed, a cobalt (Co) cap layer is selectively grown after Cu chemical mechanical polishing (Cu CMP) to improve EM.
The thin-layer cobalt liner layer (Co liner) is deposited by adopting a Chemical Vapor Deposition (CVD) mode, compared with a Physical Vapor Deposition (PVD) mode, the cobalt coverage of the chemical vapor deposition is better, overhang is avoided, film-forming impurities are more, the quality is looser, and the contact resistance of a contact hole is increased.
Therefore, it is necessary to provide a new method for improving the film formation quality of the thin liner layer to reduce the contact resistance of the contact hole.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a method for optimizing the quality of a liner layer, which is used to solve the problem of the prior art that the contact resistance of a contact hole is increased due to the low film quality of a thin liner layer in a synchronous interconnection process.
To achieve the above and other related objects, the present invention provides a method for optimizing the quality of a cushion layer, the method comprising at least the steps of:
providing a dielectric layer with a groove structure, and sequentially depositing a diffusion barrier layer and a thin liner layer in the groove structure;
step two, carrying out a physical vapor deposition process on the thin liner layer by using a metal material, removing impurities in the thin liner layer to densify the thin liner layer, and simultaneously forming a metal thin layer on the thin liner layer;
depositing a copper seed crystal layer in the groove structure;
filling copper in the groove structure;
and step five, chemically and mechanically grinding the upper surface of the groove structure to remove the exposed copper, and grinding until the dielectric layer is exposed.
Preferably, the forming method of the groove structure in the dielectric layer in the first step includes: and forming the groove structure on the dielectric layer by photoetching and etching.
Preferably, the diffusion barrier layer in the first step is a TaN layer or a TiN layer.
Preferably, the diffusion barrier layer in the first step is a double-layer structure composed of a TaN layer and a Ta layer.
Preferably, the thickness of the diffusion barrier layer deposited in step one is
Preferably, the method for depositing the thin liner layer in the step one is a chemical vapor deposition method.
Preferably, the thin liner layer in step one is cobalt.
Preferably, the thin liner layer in step one is ruthenium.
Preferably, the thin liner layer deposited in step one has a thickness of
Preferably, the metal material used for the physical vapor deposition process in the second step is copper.
Preferably, the metal material used for the physical vapor deposition process in step two is an alloy containing copper.
Preferably, the metal material used for the physical vapor deposition process in the second step is a CuMn alloy or a CuAL alloy.
Preferably, the copper-containing alloy used in the physical vapor deposition process in step two has a copper content of greater than 99%.
Preferably, the bias voltage used for performing the physical vapor deposition process in the second step is 2000W.
Preferably, the direct current energy used for carrying out the physical vapor deposition process in the step two is 100-2000W; the RF power is 50-2000W.
Preferably, the thickness of the metal thin layer formed on the thin liner layer in the second step is
Preferably, the method for filling copper in the groove structure in the fourth step is as follows: and electroplating copper in the groove structure to fill the groove structure.
Preferably, the method further comprises a sixth step of forming a cap layer on the copper of the groove structure.
Preferably, the material of the cap layer formed in the sixth step is cobalt.
As described above, the method for optimizing the quality of the cushion layer of the present invention has the following beneficial effects: the invention improves the copper interconnection process, and the thin layer liner layer in the groove of the dielectric layer is subjected to physical vapor deposition by using a metal material and bombards the thin layer liner layer by using a high-bias condition to remove impurities in the thin layer liner layer, so that the thin layer liner layer is more densified, the film forming quality of the thin layer liner layer is effectively improved, and the contact resistance of the contact hole is reduced.
Drawings
FIG. 1 is a schematic diagram of a dielectric layer structure with a recessed structure according to the present invention;
FIG. 2 is a schematic structural diagram of a metal layer formed after physical vapor deposition of a thin liner layer according to the present invention;
FIG. 3 is a schematic diagram illustrating a copper seed layer formed in the trench structure according to the present invention;
FIG. 4 is a schematic view of a trench structure filled with Cu according to the present invention;
FIG. 5 is a schematic view of the structure of the present invention after removing the exposed copper on the upper surface of the trench structure;
FIG. 6 is a schematic diagram showing a structure of the present invention after a cap layer is formed on the copper in the trench structure;
FIG. 7 is a flowchart illustrating a method for optimizing the quality of a pad layer according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a method for optimizing the quality of a pad layer, as shown in fig. 7, fig. 7 is a flowchart of the method for optimizing the quality of a pad layer according to the present invention, and the method at least includes the following steps:
providing a dielectric layer with a groove structure, and sequentially depositing a diffusion barrier layer and a thin liner layer in the groove structure; as shown in fig. 1, fig. 1 is a schematic view illustrating a dielectric layer structure having a trench structure according to the present invention. The dielectric layer 01 has the groove structure E, and a diffusion barrier layer 02 is deposited in the groove structure E, and then a thin liner layer 03 is deposited, that is, the thin liner layer 03 is deposited on the diffusion barrier layer 02 in the groove structure E.
Further, in the first step of this embodiment, the method for forming the recess structure E in the dielectric layer includes: and forming the groove structure E on the dielectric layer 01 by photoetching and etching. Further, the diffusion barrier layer 02 in the first step of this embodiment is a TaN layer or a TiN layer. In other embodiments, the diffusion barrier layer 02 in the first step may also be a two-layer structure composed of a TaN layer and a Ta layer. Further, the thickness of the diffusion barrier layer 02 deposited in the first step of this embodiment is
Still further, the method for depositing the thin liner layer 03 in the first step of this embodiment is a Chemical Vapor Deposition (CVD) method. Further, the thin liner layer 03 in the first step of the present embodiment is cobalt (Co) (i.e. the material of the thin liner layer 03 is cobalt). In other embodiments, the thin liner layer in the first step may also be ruthenium (Ru). The thin liner layer 03 deposited in the first step of this embodiment has a thickness of
Step two, carrying out a physical vapor deposition process on the thin liner layer by using a metal material, removing impurities in the thin liner layer to densify the thin liner layer, and simultaneously forming a metal thin layer on the thin liner layer; as shown in fig. 2, fig. 2 is a schematic structural diagram illustrating a metal thin layer formed after a thin liner layer is subjected to physical vapor deposition in the present invention. In the second step of this embodiment, a metal material is used to perform Physical Vapor Deposition (PVD) on the thin liner layer 03, that is, the thin liner layer 03 is bombarded (deposited) with a metal material under a high bias voltage, so as to bombard and remove impurities in the thin liner layer (cobalt material), so that the cobalt thin liner layer becomes more dense, and the film quality thereof is improved.
Further, in the present invention, the metal material used for performing the Physical Vapor Deposition (PVD) process in the second step of this embodiment is copper. Thus, the thin metal layer 04 formed on the thin liner layer 03 is a thin layer of copper.
Further, in other embodiments, the metal material used in the physical vapor deposition process in step two may also be an alloy containing copper. For example, in other embodiments, the metal material used in the pvd process performed in step two may be a CuMn alloy or a CuAL alloy. Still further, in other embodiments, the copper-containing alloy used in the physical vapor deposition process in step two has a copper content of greater than 99%.
Further, the bias voltage used for the pvd process in step two of this embodiment is 2000W. Furthermore, in the second step of the present embodiment, the dc energy used for performing the pvd process is 100 to 2000W; the RF power is 50-2000W. In this embodiment, under the conditions of a high bias voltage of 2000W, a DC energy of 100-2000W and a RF power of 50-2000W, impurities in the thin liner layer of cobalt can be bombarded out, so as to obtain a more densified film.
Further, the thickness of the metal thin layer 04 formed on the thin liner layer in the second step of this embodiment is as follows
Depositing a copper seed crystal layer in the groove structure; referring to fig. 3, fig. 3 is a schematic structural view illustrating a copper seed layer formed in the trench structure according to the present invention. That is, a copper seed layer (Cu seed layer)05 is deposited on the thin liner layer 04 in the groove structure E in step three.
Filling copper in the groove structure; referring to fig. 4, fig. 4 is a schematic view illustrating a structure of the groove structure of the present invention filled with copper. Further, in the fourth step of this embodiment, the method for filling copper in the groove structure includes: and electroplating copper in the groove structure to fill the groove structure to form a copper layer 06. The diffusion barrier layer 02, the thin liner layer 03, the metal thin layer 04 and the copper seed layer 05 are respectively formed inside the groove structure and on the dielectric layer 01 outside the groove structure, that is, the diffusion barrier layer 02 is formed on the upper surface of the dielectric layer 01 outside the groove structure during deposition besides the sidewall and the bottom inside the groove structure; and the thin liner layer 03 is formed on the diffusion barrier layer 02 outside the groove structure in addition to the diffusion barrier layer 02 inside the groove structure; and the metal thin layer 04 is formed on the thin liner layer 03 outside the groove structure in addition to the thin liner layer 03 inside the groove structure; the copper seed layer 05 is formed on the metal thin layer 04 outside the groove structure in addition to the metal thin layer 04 inside the groove structure. Therefore, one part of the copper layer 06 fills the groove structure, and the other part is located on the upper surface of the groove structure and covers the copper seed layer 05.
And step five, chemically and mechanically grinding the upper surface of the groove structure to remove the exposed copper, and grinding until the dielectric layer is exposed. As shown in fig. 5, fig. 5 is a schematic structural view of the present invention after removing the copper exposed on the upper surface of the groove structure.
In the method for optimizing the quality of the liner layer according to the present invention, the liner layer refers to the thin liner layer 03 in fig. 1 to 6, and the thin liner layer 03 of the present embodiment is a liner layer of a cobalt material.
Further, the present embodiment further includes a sixth step of forming a cap layer on the copper of the groove structure. And the material of the cap layer formed in the sixth step is cobalt. As shown in fig. 6, fig. 6 is a schematic structural diagram illustrating the formation of a cap layer on the copper in the groove structure according to the present invention. The material of the cap layer 07 in this embodiment is cobalt (Co).
In summary, the invention improves the copper interconnection process, and removes the internal impurities by performing physical vapor deposition on the thin layer liner layer in the groove of the dielectric layer by using a metal material and bombarding the thin layer liner layer under a high bias condition, so that the thin layer liner layer is more densified, the film forming quality of the thin layer liner layer is effectively improved, and the contact resistance of the contact hole is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (19)
1. A method of optimizing the quality of a cushion layer, the method comprising at least the steps of:
providing a dielectric layer with a groove structure, and sequentially depositing a diffusion barrier layer and a thin liner layer in the groove structure;
step two, carrying out a physical vapor deposition process on the thin liner layer by using a metal material, removing impurities in the thin liner layer to densify the thin liner layer, and simultaneously forming a metal thin layer on the thin liner layer;
depositing a copper seed crystal layer in the groove structure;
filling copper in the groove structure;
and step five, chemically and mechanically grinding the upper surface of the groove structure to remove the exposed copper, and grinding until the dielectric layer is exposed.
2. The method of optimizing the quality of a underlayment layer of claim 1, wherein: in the first step, the forming method of the groove structure in the dielectric layer comprises the following steps: and forming the groove structure on the dielectric layer by photoetching and etching.
3. The method of optimizing the quality of a underlayment layer of claim 1, wherein: and the diffusion barrier layer in the first step is a TaN layer or a TiN layer.
4. The method of optimizing the quality of a underlayment layer of claim 1, wherein: and the diffusion barrier layer in the first step is a double-layer structure consisting of a TaN layer and a Ta layer.
5. Method for optimizing the quality of a spacer layer according to claim 3 or 4, characterized in that: the thickness of the diffusion barrier layer deposited in the step one is
6. The method of optimizing the quality of a underlayment layer of claim 1, wherein: the method for depositing the thin liner layer in the first step is a chemical vapor deposition method.
7. The method of optimizing the quality of a underlayment layer of claim 1, wherein: the thin liner layer in step one is cobalt.
8. The method of optimizing the quality of a underlayment layer of claim 1, wherein: the thin liner layer in step one is ruthenium.
9. The method of optimizing spacer layer quality of claim 7 wherein: the thickness of the thin liner layer deposited in the first step is
10. The method of optimizing the quality of a underlayment layer of claim 1, wherein: and in the second step, the metal material used for the physical vapor deposition process is copper.
11. The method of optimizing the quality of a underlayment layer of claim 1, wherein: and in the second step, the metal material used for the physical vapor deposition process is copper-containing alloy.
12. The method of optimizing the quality of a underlayment layer of claim 11, wherein: and in the second step, the metal material used for the physical vapor deposition process is CuMn alloy or CuAL alloy.
13. A method of optimising the quality of a spacer layer according to claim 11 or 12 wherein: and the copper content of the copper-containing alloy used in the physical vapor deposition process in the second step is more than 99%.
14. A method of optimising the quality of a spacer layer according to claim 11 or 12 wherein: the bias voltage used for performing the physical vapor deposition process in the second step is 2000W.
15. The method of optimizing the quality of a underlayment layer of claim 14, wherein: in the second step, the direct current energy used for carrying out the physical vapor deposition process is 100-2000W; the RF power is 50-2000W.
16. The method of optimizing the quality of a underlayment layer of claim 1, wherein: the thickness of the metal thin layer formed on the thin liner layer in the second step is
17. The method of optimizing the quality of a underlayment layer of claim 1, wherein: the method for filling copper in the groove structure in the fourth step comprises the following steps: and electroplating copper in the groove structure to fill the groove structure.
18. The method of optimizing the quality of a underlayment layer of claim 1, wherein: the method further comprises a sixth step of forming a cap layer on the copper of the groove structure.
19. The method of optimizing spacer layer quality of claim 18 wherein: and the material of the cap layer formed in the sixth step is cobalt.
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| CN202011061130.8A CN112201618A (en) | 2020-09-30 | 2020-09-30 | Method for optimizing quality of cushion layer |
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| CN202011061130.8A CN112201618A (en) | 2020-09-30 | 2020-09-30 | Method for optimizing quality of cushion layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809001A (en) * | 2021-09-03 | 2021-12-17 | 长江存储科技有限责任公司 | Semiconductor device and method of forming the same |
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| US20180294162A1 (en) * | 2017-04-07 | 2018-10-11 | Applied Materials, Inc. | Barrier film deposition and treatment |
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| US20110104890A1 (en) * | 2008-07-18 | 2011-05-05 | Ulvac, Inc | Method for forming cu electrical interconnection film |
| CN102132383A (en) * | 2008-08-29 | 2011-07-20 | 应用材料股份有限公司 | Cobalt deposition on barrier surfaces |
| CN103081066A (en) * | 2010-08-20 | 2013-05-01 | 美光科技公司 | Semiconductor constructions, and method for providing electricity conductive material within openings |
| CN110214200A (en) * | 2017-01-24 | 2019-09-06 | 应用材料公司 | Pass through the cobalt anti-agglomeration and gap filling performance of doping ruthenium enhancing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113809001A (en) * | 2021-09-03 | 2021-12-17 | 长江存储科技有限责任公司 | Semiconductor device and method of forming the same |
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