CN102437103B - Method for manufacturing integrated circuit with partially-redundant through holes and integrated circuit - Google Patents
Method for manufacturing integrated circuit with partially-redundant through holes and integrated circuit Download PDFInfo
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- CN102437103B CN102437103B CN201110386112.1A CN201110386112A CN102437103B CN 102437103 B CN102437103 B CN 102437103B CN 201110386112 A CN201110386112 A CN 201110386112A CN 102437103 B CN102437103 B CN 102437103B
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Abstract
The invention discloses a process for filling copper interconnection redundant through holes and manufacturing dual damascene. According to the process, a dual damascene structure containing partially-etched redundant through holes is manufactured by adopting a buried layer redundant through hole dielectric etching barrier layer process; and redundant through holes are added in part of areas in which the redundant through holes cannot be filled by the conventional manufacturing process, and particularly redundant through holes can be added around isolated through holes around which the redundant through holes cannot be filled in the past; and thus, the density and the density uniformity of photoetching and etching through holes are improved, then the photoetching and etching uniformity of through holes can be improved, and photoetching and etching process windows of the through holes are increased.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly copper-connection redundant via is filled and dual damascene manufacturing process.
Background technology
Along with semiconductor integrated circuit characteristic size continue reduce, back segment interconnection resistance electric capacity (Resistor Capacitor, be called for short RC) postpone to present the trend of remarkable increase, and postpone in order to reduce back segment interconnection RC, copper-connection replaces aluminium interconnection becomes main flow technique.Because the manufacture method of copper interconnecting line can not form by etching sheet metal as aluminum interconnecting, copper Damascus mosaic technology becomes the standard method of the making of copper interconnecting line.Cu dual Damascene technology: deposit one dielectric layer in planar substrates; By photoetching and etching technics, in dielectric layer, form through hole and the groove of inlaying; Depositing metal barrier layer and copper seed layer; Plated metal copper fills up through hole and groove in dielectric layer; Excess metal on dielectric layer is removed in cmp planarization, forms planar copper interconnect.
And along with reducing of clear size of opening, through hole photoetching and etching technics are more and more higher to via densities uniformity requirement, require to fill redundant via and improve via densities uniformity to improve the uniformity of photoetching and etching through hole, improve product yield, electric property and reliability.Yet, because traditional double Damascus etching technics is filled restriction much to redundant via, tradition redundant via filling mode require the redundant via D that fills must in layer redundancy metal DM region and its lower floor be also redundancy metal DM, in layer interconnection line metal 11 and lower interconnection line metal 11 on cannot fill redundant via D.The raising that this has limited redundant via D packed density, is unfavorable for the improvement of photoetching and etching through hole density uniformity, and the integrated circuit structure of prior art is referring to Fig. 1.
In order further to improve the uniformity of photoetching and etching through hole density, increase through hole photoetching and etching technics window, adopt the redundant via manufacturing process of buried regions etching barrier layer partial etching, in parts of traditional manufacturing process, cannot fill the region of redundant via and add redundant via, the isolated through hole that particularly can formerly much cannot fill redundant via adds redundant via around; Thereby, improve product yield, electric property and reliability.
Summary of the invention
The present invention proposes a kind of copper-connection redundant via and fills and dual damascene manufacturing process, adopt buried regions redundant via dielectric etching barrier layer technique to make the double damask structure that contains partial etching redundant via, in parts of traditional manufacturing process, cannot fill the region of redundant via and add redundant via, the isolated through hole that particularly can formerly much cannot fill redundant via adds redundant via around, density and the density uniformity of photoetching and etching through hole have been improved, and then can improve the uniformity of through hole photoetching and etching, increase through hole photoetching and etching technics window.
The present invention has specifically proposed a kind of integrated circuit manufacture method with partial redundance through hole, be to form the integrated circuit with dual damascene process, the method has following steps, the first step: deposit successively the first dielectric etching barrier layer on the first metal layer on semiconductor substrate, using as through-hole interconnection etching barrier layer, deposit the first dielectric layer, deposit the second dielectric etching barrier layer.Second step: photoetching or etching the second dielectric etching barrier layer, to form redundant via etching barrier layer in the precalculated position that evenly forms redundant via.The 3rd step: deposit the second dielectric layer and dielectric protection layer, make redundant via etching barrier layer between the first dielectric layer and the second dielectric layer.The 4th step: photoetching and etching are made interconnection all-pass hole and redundant via D, redundant via D is uniformly distributed and is corresponding with equally distributed described redundant via etching barrier layer 6 positions on integrated circuit.Then photoetching and etching are made the groove of interconnection line metal and redundancy metal DM, and open the first described dielectric etching barrier layer of the described full via bottoms of interconnection, form double damask structure; Or photoetching and etching are made the groove of interconnection line metal and redundancy metal DM, and open the first dielectric etching barrier layer of the full via bottoms of interconnection.Then photoetching and etching are made interconnection all-pass hole and redundant via D, described redundant via D is uniformly distributed and is corresponding with equally distributed redundant via etching barrier layer position on integrated circuit, described interconnection all-pass hole terminates in the first dielectric etching barrier layer in through-hole interconnection, redundant via terminates in redundant via etching barrier layer, open the first dielectric etching barrier layer of the full via bottoms of interconnection, form double damask structure.The 5th step: metallic copper is filled in plated metal barrier layer, copper seed layer, plating successively, and chemical/mechanical grinding-flatening is removed excess metal to the second dielectric layer, final second metal level with interconnection line metal and redundancy metal DM that forms.
Accompanying drawing explanation
Fig. 1 is the redundant via interstitital texture of prior art;
Fig. 2 to Fig. 6 is the concrete formation technique of partial redundance filling through hole structure of the present invention.
Wherein, description of reference numerals is as follows:
1 substrate 8 dielectric protection layer
2 the first metal layer 9 interconnection all-pass holes
3 first dielectric etching barrier layer 10 second metal levels
4 first dielectric layer 11 interconnection line metals
5 second dielectric etching barrier layer D redundant via
6 redundant via etching barrier layer DM redundancy metals
7 second dielectric layers
Embodiment
In conjunction with Fig. 6, integrated circuit structure of the present invention is described, in the embodiment of the present invention, functional part same as the prior art adopts identical Reference numeral.
Integrated circuit of the present invention has substrate 1, and the first metal layer 2, the first dielectric etching barrier layer 3, the first dielectric layer 4, redundant via etching barrier layer 6, the second dielectric layer 7 and the second metal level 10 that on substrate, stack gradually on 1, the first metal layer 2 is connected by interconnection all-pass hole 9 with the second metal level 10, redundant via D as far as possible evenly forms by photoetching and etching on integrated circuit, and redundant via D terminates in redundant via etching barrier layer 6.
Wherein the first metal layer 2 forms interconnection line metal 11 and redundancy metal DM by Cu dual Damascene technology.On on the first dielectric etching barrier layer 3, the first dielectric layer 4 and part the second dielectric layer 7, have the interconnection all-pass hole 9 that connects upper and lower circuit, redundant via etching barrier layer 6 is the buried regions between the first dielectric layer 4 and the second dielectric layer 7 that formed by photoetching and etching by the second dielectric etching barrier layer.On part the second dielectric layer 7, form the second metal level 10 and redundant via D, redundant via terminates in redundant via etching barrier layer 6.
Below in conjunction with Fig. 2 to Fig. 6, integrated circuit fabrication process of the present invention is described, in the present embodiment, functional part same as the prior art adopts identical Reference numeral.
Integrated circuit fabrication process of the present invention relates to redundant via and fills and dual damascene manufacturing process, this technological process first first step is on the first metal layer 2 on semiconductor substrate 1, to deposit successively the first dielectric etching barrier layer 3, usings as interconnection all-pass hole 9 etching barrier layers; Deposit the first dielectric layer 4; Deposit the second dielectric etching barrier layer 5.In this step, the technique that deposits the first dielectric etching barrier layer 3, the second dielectric etching barrier layer 5 and the first dielectric layer 4 can be selected CVD sedimentation, the material of the first dielectric barrier layer 3, the second dielectric barrier layer 5 can be selected from one or more in SiCN, SiN, SiC, SiCO, the first dielectric barrier layer 3 and the second dielectric barrier layer 5 are preferably chosen not identical dielectric material, make it have certain etching selection ratio, the first dielectric layer 4, material be chosen as SiOCH Low-K dielectric material, referring to Fig. 2.
Second step is chemical etching the second dielectric etching barrier layer 5, to form redundant via etching barrier layer 6 in the precalculated position that forms redundant via D, the size of the redundant via etching barrier layer 6 forming in this step is greater than redundant via D, and parcel redundant via D, but can not have overlapping with interconnected all-pass hole 9.
The 3rd step is deposition the second dielectric layer 7 and dielectric protection layer 8; make redundant via etching barrier layer 6 between the first dielectric layer 4 and the second dielectric layer 7; this second dielectric layer 7 selects the technique of CVD sedimentation deposition SiOCH Low-K dielectric material to form, and dielectric protection layer 8 is selected CVD sedimentation deposition SiO
2technique form, referring to Fig. 3.
The 4th step is that photoetching and etching are made interconnection all-pass hole 9 and redundant via D, described redundant via D is uniformly distributed as far as possible and is corresponding with described redundant via etching barrier layer 6 positions on integrated circuit, described interconnection all-pass hole 9 terminates in the first dielectric etching barrier layer 3, redundant via D terminates in redundant via etching barrier layer 6, referring to Fig. 4.Then photoetching and etching are made the groove of interconnection line metal 11 and redundancy metal DM, and open the first described dielectric etching barrier layer 3 of described 9 bottoms, interconnection all-pass hole, form double damask structure, referring to Fig. 5;
Or first photoetching and etching are made the groove of interconnection line metal 11 and redundancy metal DM, then photoetching and etching are made interconnection all-pass hole 9 and redundant via D, described redundant via D is uniformly distributed as far as possible and is corresponding with equally distributed redundant via etching barrier layer 6 positions on integrated circuit, described interconnection all-pass hole 9 terminates in the first dielectric etching barrier layer 3 in through-hole interconnection, redundant via 10 terminates in redundant via etching barrier layer 6, then remove residue photoresistance, etching is opened the first dielectric etching barrier layer 3 of interconnection 9 bottoms, all-pass hole, form double damask structure.
The 5th step is plated metal barrier layer, copper seed layer, plating filling metallic copper, and chemical/mechanical grinding (CMP) planarization removal excess metal to the second dielectric layer 7, finally forms the step of the second metal level 10.Metal barrier in this step can deposit one or more formation in TaN, Ta, TiN, Ti by PVD or ALD method, and copper seed layer can adopt PVD sedimentation to form, referring to Fig. 6.
Being uniformly distributed and the filling of the redundant via in the interconnection line metal 11 of the first metal layer 2 and the interconnection line metal 11 of the second metal level 10 of redundant via on surface-mounted integrated circuit thus.
The present invention proposes a kind of copper-connection redundant via and fills and dual damascene manufacturing process, adopt redundant via dielectric etching barrier layer 6 techniques to make the double damask structure that contains partial etching redundant via D, realize redundant via and fill, and do not affect circuit function.
Redundant via filling mode: not only can Dang Cenghe lower floor simultaneously with redundancy metal area filling redundant via D, and allow in layer metal interconnecting wires 11 and on lower metal interconnection line, suitably adding redundant via D, the redundant via and the through-hole interconnection that add are placed on same mask, to improve photoetching and etching through hole density uniformity, increase through hole photoetching and etching technics window.
Redundant via etching barrier layer technique is made the double damask structure that contains partial etching redundant via: deposition of dielectric layer on lower metal layer matrix (embedding redundant via dielectric etching barrier layer in dielectric layer); Dual damascene etching technics is made through hole and groove, and through-hole interconnection is opened through-hole interconnection etching barrier layer, contact lower metal interconnection line; Depositing metal barrier layer and copper seed layer; Electroplate and fill metallic copper, cmp planarization, is ground to dielectric layer and removes excess metal, forms the second metal level double damask structure.
The present invention can repeat above-mentioned steps and make more multi-layered metal level.
The present invention improves density and the density uniformity of photoetching and etching through hole, and then can improve the uniformity of through hole photoetching and etching, increases through hole photoetching and etching technics window, thereby reaches the beneficial effect that improves product yield, electric property and reliability.
Technology contents of the present invention and technical characterstic are open as above, any change or the adjustment of those skilled in the art on this basis, the scope of neither disengaging appended claim of the present invention institute wish protection.
Claims (10)
1. an integrated circuit manufacture method with partial redundance through hole, is to form the integrated circuit with dual damascene process, and the method has following steps:
The first step: deposit successively the first dielectric etching barrier layer (3), the first dielectric layer (4), the second dielectric etching barrier layer (5) on the first metal layer (2) on semiconductor substrate (1), wherein, using the first dielectric etching barrier layer (3) as through-hole interconnection etching barrier layer;
Second step: the second dielectric etching barrier layer (5) described in chemical etching, to form redundant via etching barrier layer (6) in the precalculated position that evenly forms redundant via D;
The 3rd step: deposit the second dielectric layer (7) and dielectric protection layer (8), make described redundant via etching barrier layer (6) between described the first dielectric layer (4) and described the second dielectric layer (7);
The 4th step: photoetching and etching are made interconnection all-pass hole (9) and redundant via (D), described redundant via (D) is uniformly distributed and is corresponding with described redundant via etching barrier layer (6) position on integrated circuit, described redundant via (D) terminates in described redundant via etching barrier layer (6), then photoetching and etching are made the groove of interconnection line metal (11) and redundancy metal (DM), and open the first described dielectric etching barrier layer (3) of described bottom, interconnection all-pass hole (9), form double damask structure;
Or photoetching and etching are made the groove of interconnection line metal (11) and redundancy metal (DM), then, photoetching and etching are made interconnection all-pass hole (9) and redundant via (D), described redundant via (D) terminates in described redundant via etching barrier layer (6), and the described redundant via (D) of the first described dielectric etching barrier layer (3) of opening described bottom, interconnection all-pass hole (9) is uniformly distributed and corresponding with described redundant via etching barrier layer (6) position on integrated circuit, form double damask structure;
The 5th step: plated metal barrier layer, copper seed layer successively, and electroplate and fill metallic copper, and chemical/mechanical grinding-flatening removes excess metal to the second dielectric layer (7), final second metal level (10) with interconnection line metal (11) and described redundancy metal (DM) that forms.
2. manufacture method as claimed in claim 1, wherein, described deposition the first dielectric etching barrier layer (3), the second dielectric etching barrier layer (5) and described the first dielectric layer (4) and the technique of the second dielectric layer (7) are CVD sedimentation.
3. manufacture method as claimed in claim 1, wherein, the first described dielectric etching barrier layer (3), the material of the second dielectric etching barrier layer (5) are to be selected from one or more in SiCN, SiN, SiC, SiCO.
4. manufacture method as claimed in claim 3, wherein, the first described dielectric etching barrier layer (3), the material of the second dielectric etching barrier layer (5) are selected different dielectric materials, so that it has certain etching selection ratio.
5. manufacture method as claimed in claim 1, wherein, described the first dielectric layer (4), the second dielectric layer (7) material are SiOCH Low-K dielectric material.
6. manufacture method as claimed in claim 1, wherein, the cross-sectional area of the described redundant via etching barrier layer (6) of formation is greater than the cross-sectional area of redundant via (D), but can not have overlapping with described interconnection all-pass hole (9).
7. manufacture method as claimed in claim 1, wherein, adopts CVD sedimentation deposition SiO
2form described dielectric protection layer (8).
8. manufacture method as claimed in claim 1, wherein, the described metal barrier in the 5th step can be by one or more formation in PVD or ALD method deposition TaN, Ta, TiN, Ti.
9. manufacture method as claimed in claim 1, wherein, described copper seed layer can adopt PVD sedimentation to form.
10. an integrated circuit with the dual damascene manufacturing process that redundant via is partially filled, is characterized in that right to use requires the manufacture method described in any one in 1-9 to make.
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| CN1499626A (en) * | 2002-10-30 | 2004-05-26 | ��ʿͨ��ʽ���� | Semiconductor device and its mfg. method |
| CN101276815A (en) * | 2007-03-29 | 2008-10-01 | 株式会社瑞萨科技 | Semiconductor device |
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| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1499626A (en) * | 2002-10-30 | 2004-05-26 | ��ʿͨ��ʽ���� | Semiconductor device and its mfg. method |
| CN101276815A (en) * | 2007-03-29 | 2008-10-01 | 株式会社瑞萨科技 | Semiconductor device |
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