CN112198729B - Array substrate, display panel and electronic equipment - Google Patents

Array substrate, display panel and electronic equipment Download PDF

Info

Publication number
CN112198729B
CN112198729B CN202011175784.3A CN202011175784A CN112198729B CN 112198729 B CN112198729 B CN 112198729B CN 202011175784 A CN202011175784 A CN 202011175784A CN 112198729 B CN112198729 B CN 112198729B
Authority
CN
China
Prior art keywords
layer
electrode
array substrate
substrate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011175784.3A
Other languages
Chinese (zh)
Other versions
CN112198729A (en
Inventor
艾飞
宋继越
宋德伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to CN202011175784.3A priority Critical patent/CN112198729B/en
Priority to PCT/CN2020/131049 priority patent/WO2022088326A1/en
Priority to US17/260,982 priority patent/US20220399383A1/en
Publication of CN112198729A publication Critical patent/CN112198729A/en
Application granted granted Critical
Publication of CN112198729B publication Critical patent/CN112198729B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F1/13318—Circuits comprising a photodetector
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Human Computer Interaction (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention discloses an array substrate, a display panel and electronic equipment, wherein the array substrate comprises a substrate, a first insulating layer and a second insulating layer, wherein the substrate comprises a first conducting layer arranged on the first conducting layer; the first conductive layer includes a first connection portion; the first connecting part is connected with the first metal part; the fourth insulation layer is arranged on the first conducting layer; a second through hole is formed in the fourth insulation; a second conductive layer disposed on the fourth insulation layer and in the second via, the second conductive layer including a second electrode, the second electrode covering the PIN diode; the second electrode is connected with the first connecting portion through the second via hole. The array substrate, the display panel and the electronic device can improve the stability of the optical sensor.

Description

Array substrate, display panel and electronic equipment
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and electronic equipment.
Background
The combination of optical fingerprint technology and display panel is one of the main directions at present, and its principle is to utilize the difference of intensity of light reflected to the sensing area of display panel by the valleys and ridges of the fingerprint, thereby converting different light signals into electric signals, extracting through the chip, forming the key fingerprint pattern, and achieving the purpose of fingerprint identification.
At present, optical fingerprint technologies applied to organic light emitting diodes are relatively wide, but the optical fingerprint technologies applied to liquid crystal display panels are few, and due to the limitation of factors such as backlight and aperture opening ratio, an optical sensor needs to be manufactured on an array substrate, but the depth of a via hole between an upper conductive layer and a lower metal part is deep, so that process risks in the exposure and etching processes are increased, and the stability of the optical sensor is reduced.
Disclosure of Invention
The invention provides an array substrate, a display panel and an electronic device, which can reduce process risks in the exposure and etching processes and improve the stability of an optical sensor.
The invention provides an array substrate, which comprises:
a substrate including a control element;
the third metal layer is arranged on the substrate; the third metal layer comprises a first electrode and a first metal part, and the first electrode is connected with the control element through a first through hole;
the PIN diode is arranged on the first electrode and comprises a first semiconductor layer and an intrinsic semiconductor layer;
the third insulating layer is arranged on the PIN diode;
the first conducting layer is arranged on the third insulating layer; the first conductive layer includes a first connection portion; the first connecting part is connected with the first metal part;
the fourth insulating layer is arranged on the first conducting layer; a second through hole is formed in the fourth insulation;
a second conductive layer disposed on the fourth insulation layer and in the second via, the second conductive layer including a second electrode, the second electrode covering the PIN diode; the second electrode is connected with the first connecting portion through the second via hole.
The invention also provides a display panel which comprises the array substrate.
The invention also provides electronic equipment which comprises the display panel.
The array substrate, the display panel and the electronic equipment comprise a substrate, a display panel and a display panel, wherein the substrate comprises a control element; the third metal layer is arranged on the substrate; the third metal layer comprises a first electrode and a first metal part, and the first electrode is connected with the control element; the PIN diode is arranged on the first electrode and comprises a first semiconductor layer and an intrinsic semiconductor layer; the first conducting layer is arranged on the PIN diode; the first conductive layer includes a first connection portion; the first connecting part is connected with the first metal part; the fourth insulating layer is arranged on the first conducting layer; a second through hole is formed in the fourth insulation; a second conductive layer disposed on the fourth insulation layer and in the second via, the second conductive layer including a second electrode, the second electrode covering the PIN diode; the second electrode is connected with the first connecting part through the second via hole; therefore, the depth of the connecting hole between the second electrode and the first metal part can be reduced, the process risk caused by the difference of the depth hole in the exposure and etching processes is reduced, the stability and the process feasibility of the manufacturing process are improved, and the stability of the optical sensor is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention.
Fig. 2 is a flow chart of a manufacturing process of the array substrate shown in fig. 1.
Fig. 3 is a schematic cross-sectional view of an array substrate according to another embodiment of the invention.
Fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. In the present invention, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc. refer to directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The terms "first," "second," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions.
Referring to fig. 1 to 3, fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention.
As shown in fig. 1, the array substrate 100 of the present embodiment includes a substrate 10, a third metal layer 21, a PIN diode 30, a first conductive layer 40, a fourth insulating layer 24, and a second conductive layer 50.
The substrate 10 includes control elements T1; the control element T1 is also a thin film transistor. In one embodiment, the substrate 10 may include: a base substrate 11, a first semiconductor layer 14, a first insulating layer 15, a first metal layer 16, and a second metal layer 18. In addition, the substrate 10 may further include at least one of a light-shielding layer 12, a buffer layer 13, a gate insulating layer 17, a planarization layer 19, and a passivation layer 19'.
The substrate 11 may be a glass substrate or a flexible substrate. The material of the substrate 11 includes one or more of glass, silica, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide, and polyurethane.
The light shielding layer 12 is disposed on the substrate 11, and the material of the light shielding layer 12 may be a metal material.
The buffer layer 13 is disposed on the light-shielding layer 12, and the material of the buffer layer 13 includes, but is not limited to, silicon nitride or silicon oxide.
The active layer 14 is arranged on the buffer layer 13; in a preferred embodiment, the material of the active layer 14 is polysilicon. Referring to fig. 2, the active layer 14 may include a first semiconductor portion 141.
A first insulating layer 15 is provided on the active layer 14; the material of the first insulating layer 15 may include at least one of silicon nitride, silicon oxide, and organic photoresist.
A first metal layer 16 is provided on the first insulating layer 15; the first metal layer 16 includes a first gate electrode 161. The material of the first metal layer 16 may include at least one of copper, aluminum, and titanium.
The gate insulating layer 17 is disposed on the first metal layer 16, and a material of the gate insulating layer 17 may include at least one of silicon nitride and silicon oxide.
A second metal layer 18 is disposed on the gate insulating layer 17, wherein the second metal layer 18 includes a first source 181 and a first drain 182; the material of the second metal layer 18 may be the same as the material of the first metal layer 16.
The planarization layer 19 is disposed on the second metal layer 18, and the material of the planarization layer 19 may include at least one of silicon nitride, silicon oxide, and organic photoresist. In a preferred embodiment, the material of the planarization layer 19 is an organic photoresist.
A passivation layer 19 'is disposed on the planarization layer 19, and the material of the passivation layer 19' may include at least one of silicon nitride, silicon oxide, and organic photoresist.
A third metal layer 21 is provided on the passivation layer 19'; the third metal layer 21 includes a first electrode 211 and a first metal part 212. The first electrode 211 is connected to the control element T1 through a first via 191, and specifically the first electrode 211 is connected to the first drain 182.
The material of the third metal layer 21 may be at least one of Ti/Al/Ti, Mo/Cu, Mo/Al/Mo. The material of the third metal layer 21 is not limited thereto. In one embodiment, in order to improve the sensitivity of the photosensor, the area of the orthographic projection of the first electrode 211 on the substrate 10 is larger than the area of the orthographic projection of the PIN diode 30 on the substrate 10, that is, the PIN diode 30 partially covers the first electrode 211. The PIN diode 30 covers at least a part of the first semiconductor portion 141, and in a preferred embodiment, in order to further increase the aperture ratio, the PIN diode 30 covers the first semiconductor portion 141 entirely. That is, the PIN diode 30 covers at least a part of the first semiconductor portion 141 and a part of the first electrode 211.
The PIN diode 30 is disposed on the first electrode 211, and the PIN diode 30 includes a first semiconductor layer 31, an intrinsic semiconductor layer 32, and a second semiconductor layer 33; the intrinsic semiconductor layer 32 and the second semiconductor layer 33 are sequentially provided on the first semiconductor layer 31. In one embodiment, the material of the first semiconductor layer 31 is N-type amorphous silicon (N + a-Si), the material of the intrinsic semiconductor layer 32 is amorphous silicon (a-Si), and the material of the second semiconductor layer 33 is P-type amorphous silicon (P + a-Si). In a preferred embodiment, the material of the semiconductor layer of the control element T1 is polysilicon, and the material of the intrinsic semiconductor layer 32 is amorphous silicon, which can be made thicker, so that the amorphous silicon is beneficial to light absorption, and is convenient for forming a high-performance photosensor, thereby improving the accuracy of fingerprint identification. In other embodiments, the PIN diode 30 may not include the second semiconductor layer 33, that is, the PIN diode 30 includes the first semiconductor layer 31 and the intrinsic semiconductor layer 32.
The third insulating layer 23 is arranged on the PIN diode; the material of the third insulating layer 23 may also include at least one of silicon nitride, silicon oxide, and organic photoresist.
A first conductive layer 40 is disposed on the third insulating layer, wherein the first conductive layer 40 includes a first connection portion 44, and the first connection portion 44 is connected to the first metal portion 212; in an embodiment, in order to reduce the impedance of the first electrode, the first conductive layer 40 may further include a first plate 41, and the first plate 41 is connected to the first electrode 211. It is understood, of course, that in other embodiments, first conductive layer 40 may not include a first plate. In one embodiment, the material of the first conductive layer 40 includes, but is not limited to, indium tin oxide. In another embodiment, the first conductive layer 40 further includes a second connection portion 45, and the second connection portion 45 is connected to the drain electrode 183 of the switching element T2. In one embodiment, in order to reduce the impedance of the first electrode, the first conductive layer 40 further includes a first electrode plate 41, and the first electrode plate 41 is connected to the first electrode 211. It is understood, of course, that in other embodiments, first conductive layer 40 may not include a first plate. In one embodiment, the material of the first conductive layer 40 includes, but is not limited to, indium tin oxide. In one embodiment, the position of the orthographic projection of the first conductive layer 40 on the substrate 10 does not overlap the position of the orthographic projection of the PIN diode 30 on the substrate 10.
A fourth insulating layer 24 is disposed on the first conductive layer 40; referring to fig. 2, a second via 241 is disposed on the fourth insulating layer 24. In another embodiment, a third via 242 is further disposed on the fourth insulating layer 24. The material of the fourth insulating layer 24 may also include at least one of silicon nitride, silicon oxide, and organic photoresist. A first opening (not shown) is disposed on the fourth insulating layer 24, and the first opening is used for connecting the second electrode 51 and the PIN diode 30, that is, the first opening is used for exposing a part of the PIN diode 30.
A second conductive layer 50 is provided on the PIN diode 30, the second conductive layer 50 comprising a second electrode 51. The second electrode 51 covers the PIN diode 30. Referring to fig. 2, the second electrode 51 is connected to the first connection portion 44 through the second via 241. That is, the second electrode 51 is connected to the first metal part 212 through the first connection part 44. In one embodiment, the material of the second conductive layer 50 includes, but is not limited to, indium tin oxide. In addition, the first metal part 212 can be used as a voltage access point of the second electrode 51, so that the driving chip inputs a voltage to the second electrode 51 through the first metal part 212, and further the length of a connection line between the second electrode 51 and the driving chip is shortened, the loss of the voltage is reduced, and the sensitivity of the photosensor is further improved. In an embodiment, the second electrode 51 may also cover a part or all of the first metal portion 212. Wherein in an embodiment, a portion of the second electrode 51 is located within the first opening.
In another embodiment, the substrate 10 further includes a switching element T2, and the switching element T2 includes a third drain 183. The second conductive layer 50 further includes a pixel electrode 53; the pixel electrode 53 is connected to the second connection portion 45 through the third via hole 242, so that the depth of the via hole between the pixel electrode and the third drain electrode is further reduced, the process risk caused by the difference of the deep and shallow holes in the exposure and etching processes is reduced, the stability and the process feasibility of the manufacturing process are improved, and the stability of the optical sensor is further improved.
In a preferred embodiment, the pixel electrode 53 covers the second connection portion 45 in order to further reduce the impedance of the connection line. That is, the forward projection area of the pixel electrode 53 on the substrate is greater than or equal to the forward projection area of the second connection portion 45 on the substrate.
In one embodiment, in order to further improve the sensitivity of the photosensor, the second electrode 51 covers the first electrode 211 and the first plate 41, that is, the area of the orthographic projection of the second electrode 51 on the substrate is larger than the sum of the area of the orthographic projection of the first electrode 211 on the substrate and the area of the orthographic projection of the first plate 41 on the substrate. The array substrate 100 may further include a second plate, which is a portion (not shown) of the second electrode 51 corresponding to the first plate 41; the second plate forms a storage capacitor C1 with the first plate 41.
In another embodiment, in order to further improve the integration of the array substrate and reduce the overall thickness, the third metal layer 21 further includes a common electrode 213; the first conductive layer 40 further includes a touch electrode line 42; the position of the common electrode 213 corresponds to the position of the touch electrode line 42, and the common electrode 213 is connected to the touch electrode line 42. In one embodiment, the material of the first conductive layer 30 includes, but is not limited to, indium tin oxide. The touch electrode line 42 here is also used for an access point as a common voltage.
In one embodiment, to simplify the manufacturing process and reduce the production cost, the first conductive layer 40 further includes a third plate 43, and the second conductive layer 50 further includes a fourth plate 52, wherein the fourth plate 52 corresponds to the third plate 43 to form a pixel capacitor.
In a preferred embodiment, the third drain 183 is located on the second metal layer 18. That is, the drain and the source of the switching element T2 are fabricated at the same level as the source and the drain of the control element T1, respectively, the gate of the switching element T2 may be fabricated at the same level as the gate of the control element T1, and the active layer of the switching element T2 may be fabricated at the same level as the active layer of the control element T1.
In an embodiment, the array substrate 100 may further include a second insulating layer 22.
The second insulating layer 22 is disposed between the third metal layer 21 and the first semiconductor layer 31; the material of the second insulating layer 22 may include at least one of silicon nitride, silicon oxide, and organic photoresist. Wherein a second opening (not labeled) is disposed on the second insulating layer 22, and the position of the second opening corresponds to the position of the first opening, wherein the second opening is used for connecting the PIN diode 30 and the first electrode 211. Wherein the PIN diode 30 may be located within the second opening and overlying a portion of the second insulating layer 22. In one embodiment, the area of the second opening is larger than the area of the first opening, or the width of the second opening is larger than the width of the first opening. Wherein the position of the second opening corresponds to the position of the first electrode 211 in order to facilitate the connection of the PIN diode 30 with the first electrode 211.
The third insulating layer 23 is provided between the PIN diode 30 and the first conductive layer 40; the material of the third insulating layer 23 may also include at least one of silicon nitride, silicon oxide, and organic photoresist.
The photosensitive sensor comprises a PIN diode 30, a first electrode and a second electrode, the photosensitive sensor is manufactured on the control element T1, and the PIN diode 30 at least covers part of the active layer of the control element, so that the photosensitive sensor at least covers part of the active layer of the control element, the aperture opening ratio is improved, and the accuracy of fingerprint identification is improved; in addition, the light absorption coefficient of the photosensitive layer of the amorphous silicon is greatly superior to that of the polycrystalline silicon, so that the sensitivity of the photosensitive sensor is improved.
The second electrode is connected with the first connecting part through the second through hole, so that the depth of the connecting hole between the second electrode and the first metal part can be reduced, the process risk caused by the difference of deep holes and shallow holes in the exposure and etching processes is reduced, the stability and the process feasibility of the manufacturing process are improved, and the stability of the optical sensor is improved.
As shown in fig. 2, in an embodiment, a method for manufacturing an array substrate of this embodiment includes:
s101, preparing a light shielding layer 12 on a substrate 11;
for example, the light-shielding layer 12 is patterned by exposure etching or the like so that the light-shielding layer 12 shields the first semiconductor portion 141.
S102, sequentially preparing the buffer layer 13 and the active layer 14 on the light-shielding layer 12.
For example, amorphous silicon is deposited on the buffer layer 13, and after excimer laser annealing, the active layer 14 of polycrystalline silicon is obtained, the active layer 14 is exposed and etched to form the first semiconductor portion 141 and the second semiconductor portion 142, respectively, and P ions are doped into the first semiconductor portion 141 and the second semiconductor portion 142 to form N +, so that the first semiconductor portion 141 and the second semiconductor portion 142 can be easily in ohmic contact.
S103, depositing a first insulating layer 15 and a first metal layer 16 on the first semiconductor portion and the second semiconductor portion in this order.
For example, the first metal layer 16 is patterned to form a first gate electrode 161 and a third gate electrode 162. Then, N-ion implantation is performed on the first and second semiconductor portions 141 and 142, respectively, using a self-aligned process.
And S104, depositing a gate insulating layer 17 on the first metal layer 16.
For example, in one embodiment, the gate insulating layer 17 may have a SiNx/SiOx stack structure, and in one embodiment, the gate insulating layer 17 may be hydrogenated and activated by rapid thermal annealing, and then exposed and etched to form source and drain connection holes, which are connected to the first semiconductor portion 141 or the second semiconductor portion 142.
And S105, depositing a second metal layer in the connecting hole and the gate insulating layer 17.
For example, patterning the second metal layer 18 forms the first source and drain electrodes 181 and 182, and the third drain and source electrodes 183 and 184.
And S106, preparing the flat layer 19 and the passivation layer 19' on the second metal layer 18 in sequence.
For example, a first via 191 is disposed on the passivation layer 19 ', the first via 191 penetrates the passivation layer 19' and the planarization layer 19, and the first electrode 211 is connected to the first drain electrode 182 through the first via 191.
S107, depositing a third metal layer 21 on the passivation layer 19'.
For example, the third metal layer 21 is patterned to form a first electrode 211, a first metal portion 212, and a common electrode 213.
And S108, depositing a second insulating layer 22 on the third metal layer 21.
S109, depositing the first semiconductor layer 31, the intrinsic semiconductor layer 32, and the second semiconductor layer 33 on the second insulating layer 22 in sequence, and patterning them. In one embodiment, the material of the first semiconductor layer 31 is N-type amorphous silicon (N + a-Si), the material of the intrinsic semiconductor layer 32 is amorphous silicon (a-Si), and the material of the second semiconductor layer 33 is P-type amorphous silicon (P + a-Si).
S110, sequentially forming the third insulating layer 23 and the first conductive layer 40 on the second semiconductor layer 33, and patterning the first conductive layer 40 to form the first electrode plate 41, the touch electrode line 42, the third electrode plate 43, the first connection portion 44, and the second connection portion 45.
A first connection hole, a second connection hole, and a third connection hole (not shown) are formed in the third insulating layer 23, wherein the touch electrode line 42 is connected to the common electrode 213 through the first connection hole, the first electrode plate 41 is connected to the first electrode 211 through the second connection hole, and the first connection portion 44 is connected to the first metal portion 212 through the third connection hole. The first connection hole, the second connection hole, and the third connection hole all penetrate through the third insulating layer 23 and the second insulating layer 22.
S111, depositing the fourth insulating layer 24 and the second conductive layer 50 on the first conductive layer 40 in sequence.
For example, a second via 241 and a third via 242 are disposed on the fourth insulating layer 24, and the second via 241 is used to connect the second electrode 51 and the first connection portion 44.
The third via hole 242 is used to connect the pixel electrode 53 and the second connection portion 45. The second connection portion 45 is connected to the third drain 183.
A second conductive layer 50 is formed in the second via hole, the third via hole and the fourth insulating layer 24, and the second conductive layer 50 is patterned to form a second electrode 51, a pixel electrode 53 and a fourth electrode plate 52.
The manufacturing method of the array substrate of the present embodiment includes all technical solutions of the array substrate, so that all the technical effects can be achieved, and details are not described herein.
In other embodiments, as shown in fig. 3, the third metal layer 21 may further include an auxiliary portion 214, and the second connection portion 45 is connected to the drain of the switching element T2 through the auxiliary portion 214. Therefore, the depth of the through hole between the pixel electrode and the third drain electrode is further reduced, the process risk caused by the difference of the depth hole in the exposure and etching processes is reduced, the stability and the process feasibility of the manufacturing process are improved, and the display effect is further improved.
The passivation layer 19' of the present embodiment is further provided with a fourth via hole, wherein the auxiliary portion 214 is connected to the third drain electrode 183 through the fourth via hole.
The manufacturing method of the array substrate of the present embodiment is different from the previous embodiment in that:
the manufacturing method of the embodiment further comprises the following steps: a fourth via is provided on the passivation layer 19', wherein the auxiliary portion 214 is connected with the third drain electrode 183 through the fourth via.
As shown in fig. 4, the present embodiment further provides a display panel 200, which includes any one of the array substrates 100, and the display panel 200 may further include a second substrate 201, where the second substrate 201 is disposed opposite to the array substrate 100. The display panel 200 may be a liquid crystal display panel. A liquid crystal layer (not shown) is further disposed between the array substrate 100 and the second substrate 201. In addition, a sealant may be disposed between the array substrate 100 and the second substrate 201 for bonding the array substrate 100 and the second substrate 201. In one embodiment, the second substrate 201 may include a second substrate 71 and a second electrode 72, and the second electrode 72 is disposed on a side of the second substrate 71 close to the array substrate. In another embodiment, the second substrate 201 may be a color film substrate, that is, the second substrate 201 may further include a color film layer. It is understood that the structure of the second substrate 201 is not limited thereto.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an electronic device provided in the present invention.
The electronic device 300 may include a display panel 200, a control circuit 80, and a housing 90. It should be noted that the electronic device 300 shown in fig. 5 is not limited to the above, and may further include other devices, such as a camera, an antenna structure, a fingerprint unlocking module, and the like.
The display panel 200 is disposed on the housing 90.
In some embodiments, the display panel 200 may be fixed to the housing 90, and the display panel 200 and the housing 90 form a closed space to accommodate the control circuit 80 and the like.
In some embodiments, the housing 90 may be made of a flexible material, such as a plastic housing or a silicone housing.
The control circuit 80 is installed in the casing 90, the control circuit 80 may be a motherboard of the electronic device 300, and one, two or more functional components of a battery, an antenna structure, a microphone, a speaker, an earphone interface, a universal serial bus interface, a camera, a distance sensor, an ambient light sensor, a receiver, a processor, and the like may be integrated on the control circuit 80.
The display panel 200 is mounted in the housing 90, and the display panel 200 is electrically connected to the control circuit 80 to form a display surface of the electronic device 300. The display panel 200 may include a display area and a non-display area. The display area may be used to display a screen of the electronic device 300 or provide a user with touch control. The non-display area may be used to set various functional components.
The electronic device includes, but is not limited to, a mobile phone, a tablet computer, a computer monitor, a game machine, a television, a display screen, a wearable device, and other life appliances or household appliances with display functions.
The array substrate, the display panel and the electronic equipment comprise a substrate, a display panel and a display panel, wherein the substrate comprises a control element; the third metal layer is arranged on the substrate; the third metal layer comprises a first electrode and a first metal part, and the first electrode is connected with the control element; the PIN diode is arranged on the first electrode and comprises a first semiconductor layer and an intrinsic semiconductor layer; the first conducting layer is arranged on the PIN diode; the first conductive layer includes a first connection portion; the first connecting part is connected with the first metal part; the fourth insulating layer is arranged on the first conducting layer; a second through hole is formed in the fourth insulation; a second conductive layer disposed on the fourth insulation layer and in the second via, the second conductive layer including a second electrode, the second electrode covering the PIN diode; the second electrode is connected with the first connecting part through the second via hole; therefore, the depth of the connecting hole between the second electrode and the first metal part can be reduced, the process risk caused by the difference of the depth hole in the exposure and etching processes is reduced, the stability and the process feasibility of the manufacturing process are improved, and the stability of the optical sensor is improved.
The array substrate, the display panel and the electronic device provided by the invention are described in detail, and the principle and the embodiment of the invention are explained by applying specific examples, and the description of the embodiments is only used to help understanding the invention. Meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (14)

1. An array substrate, comprising:
a substrate including a control element;
the third metal layer is arranged on the substrate; the third metal layer comprises a first electrode and a first metal part, and the first electrode is connected with the control element through a first through hole;
the PIN diode is arranged on the first electrode and comprises a first semiconductor layer and an intrinsic semiconductor layer;
the third insulating layer is arranged on the PIN diode;
the first conducting layer is arranged on the third insulating layer; the first conductive layer includes a first connection portion; the first connecting part is connected with the first metal part;
the fourth insulating layer is arranged on the first conducting layer; a second through hole is formed in the fourth insulating layer;
the second conducting layer is arranged on the fourth insulating layer and in the second through hole, and comprises a second electrode which covers the PIN diode; the second electrode is connected with the first connecting part through the second via hole;
the substrate further comprises a switching element;
a third via hole is further formed in the fourth insulating layer;
the first conductive layer further comprises a second connection portion; the second connection portion is connected to a drain of the switching element;
the second conductive layer further includes a pixel electrode; the pixel electrode is connected with the second connecting part through the third via hole;
the pixel electrode covers the second connecting part;
the third metal layer further includes an auxiliary portion through which the second connection portion is connected to the drain of the switching element.
2. The array substrate of claim 1, wherein the base further comprises:
and the passivation layer is arranged between the third metal layer and the switch element, a fourth through hole is formed in the passivation layer, and the auxiliary part is connected with the drain electrode of the switch element through the fourth through hole.
3. The array substrate of claim 1,
the position of the orthographic projection of the first conducting layer on the substrate is not overlapped with the position of the orthographic projection of the PIN diode on the substrate.
4. The array substrate of claim 1,
and a first opening is arranged on the fourth insulating layer and used for connecting the second electrode and the PIN diode.
5. The array substrate of claim 4, further comprising a second insulating layer, wherein a second opening is disposed on the second insulating layer, and the position of the second opening corresponds to the position of the first opening, wherein the second opening is used for connecting the PIN diode and the first electrode.
6. The array substrate of claim 5,
the area of the second opening is larger than the area of the first opening.
7. The array substrate of claim 1,
and a third connecting hole is formed in the third insulating layer, and the first connecting part is connected with the first metal part through the third connecting hole.
8. The array substrate of claim 1,
the third metal layer further comprises a common electrode; the first conducting layer further comprises a touch electrode line; the position of the public electrode corresponds to the position of the touch electrode wire, and the public electrode is connected with the touch electrode wire.
9. The array substrate of claim 1,
the first conductive layer further comprises a third polar plate;
the second conducting layer further comprises a fourth polar plate, and the position of the third polar plate corresponds to the position of the fourth polar plate.
10. The array substrate of claim 1,
the PIN diode covers at least a portion of the active layer of the control element and a portion of the first electrode.
11. The array substrate of claim 1,
the active layer of the control element is made of polycrystalline silicon, and the intrinsic semiconductor layer is made of amorphous silicon.
12. The array substrate of claim 1,
the PIN diode further comprises a second semiconductor layer disposed on the intrinsic semiconductor layer.
13. A display panel comprising the array substrate according to any one of claims 1 to 12.
14. An electronic device characterized by comprising the display panel according to claim 13.
CN202011175784.3A 2020-10-28 2020-10-28 Array substrate, display panel and electronic equipment Active CN112198729B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202011175784.3A CN112198729B (en) 2020-10-28 2020-10-28 Array substrate, display panel and electronic equipment
PCT/CN2020/131049 WO2022088326A1 (en) 2020-10-28 2020-11-24 Array substrate, display panel and electronic device
US17/260,982 US20220399383A1 (en) 2020-10-28 2020-11-24 Array substrate, display panel, and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011175784.3A CN112198729B (en) 2020-10-28 2020-10-28 Array substrate, display panel and electronic equipment

Publications (2)

Publication Number Publication Date
CN112198729A CN112198729A (en) 2021-01-08
CN112198729B true CN112198729B (en) 2022-04-26

Family

ID=74011777

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011175784.3A Active CN112198729B (en) 2020-10-28 2020-10-28 Array substrate, display panel and electronic equipment

Country Status (3)

Country Link
US (1) US20220399383A1 (en)
CN (1) CN112198729B (en)
WO (1) WO2022088326A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112909066B (en) * 2021-02-05 2024-02-02 武汉华星光电半导体显示技术有限公司 Display panel, preparation method of display panel and display device
CN113066798B (en) * 2021-03-08 2022-11-08 武汉华星光电技术有限公司 Driving substrate, display panel and manufacturing method of driving substrate
CN113345917B (en) * 2021-05-21 2024-03-08 武汉华星光电技术有限公司 Array substrate, manufacturing method thereof and display panel

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107480639A (en) * 2017-08-16 2017-12-15 上海天马微电子有限公司 A kind of touch-control display panel and display device
US9871061B2 (en) * 2014-08-27 2018-01-16 Samsung Display Co., Ltd. Display substrate and method of fabricating the same
CN108365050A (en) * 2018-02-24 2018-08-03 京东方科技集团股份有限公司 A kind of sensor and preparation method thereof, display panel and display device
CN109188811A (en) * 2018-10-09 2019-01-11 刘弛 Array substrate and display panel
CN111708203A (en) * 2020-07-20 2020-09-25 京东方科技集团股份有限公司 Display substrate, display panel and display device
CN111781777A (en) * 2020-07-23 2020-10-16 武汉华星光电技术有限公司 Array substrate, display panel and electronic equipment

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5293197B2 (en) * 2009-01-07 2013-09-18 セイコーエプソン株式会社 Photoelectric conversion device, electro-optical device, electronic equipment
US9494697B2 (en) * 2012-02-28 2016-11-15 Carestream Health, Inc. Digital radiographic imaging arrays including patterned anti-static protective coating with systems and methods for using the same
CN112349232A (en) * 2019-08-06 2021-02-09 群创光电股份有限公司 Display device and electronic device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9871061B2 (en) * 2014-08-27 2018-01-16 Samsung Display Co., Ltd. Display substrate and method of fabricating the same
CN107480639A (en) * 2017-08-16 2017-12-15 上海天马微电子有限公司 A kind of touch-control display panel and display device
CN108365050A (en) * 2018-02-24 2018-08-03 京东方科技集团股份有限公司 A kind of sensor and preparation method thereof, display panel and display device
CN109188811A (en) * 2018-10-09 2019-01-11 刘弛 Array substrate and display panel
CN111708203A (en) * 2020-07-20 2020-09-25 京东方科技集团股份有限公司 Display substrate, display panel and display device
CN111781777A (en) * 2020-07-23 2020-10-16 武汉华星光电技术有限公司 Array substrate, display panel and electronic equipment

Also Published As

Publication number Publication date
WO2022088326A1 (en) 2022-05-05
CN112198729A (en) 2021-01-08
US20220399383A1 (en) 2022-12-15

Similar Documents

Publication Publication Date Title
CN112198729B (en) Array substrate, display panel and electronic equipment
CN111781777B (en) Array substrate, display panel and electronic equipment
CN110634890B (en) Array substrate, electronic device and manufacturing method of array substrate
JP4737956B2 (en) Display device and photoelectric conversion element
TW200947089A (en) System for displaying images and fabrication method thereof
KR20050022358A (en) Display device and photoelectric conversion device
CN110137084B (en) Thin film transistor, preparation method thereof, electronic device substrate and electronic device
CN108807421B (en) Manufacturing method of TFT array substrate and TFT array substrate
KR102640599B1 (en) Photosensitive sensors, array substrates, and electronic devices
CN113192985A (en) TFT substrate and preparation method thereof, display panel and display device
CN112242407B (en) Array substrate and preparation method thereof
CN113345917B (en) Array substrate, manufacturing method thereof and display panel
CN111129033B (en) Array substrate and preparation method thereof
CN112241223B (en) Display screen and electronic equipment
WO2023102974A1 (en) Display panel and method for manufacturing display panel
US20200091204A1 (en) Array substrate, manufacturing method thereof, display panel and manufacturing method thereof
CN112002739A (en) Display panel, display screen and electronic equipment
US20240071125A1 (en) Display panel and method of menufacturing display panel
US11307468B2 (en) Array substrate and manufacturing method thereof
CN115236907B (en) Array substrate, display panel, display device and manufacturing method
EA045125B1 (en) LIGHT SENSOR, MATRIX SUBSTANCE AND ELECTRONIC EQUIPMENT
CN115915846A (en) Display panel and display device
CN114597244A (en) Display panel and mobile terminal
CN115132762A (en) Array substrate, manufacturing method thereof, display panel and display device
CN114792715A (en) Display panel

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant