CN112180230A - Chip test parameter abnormity detection method, storage medium and terminal - Google Patents
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Abstract
A method, a storage medium and a terminal for detecting chip test parameter abnormity are provided, the method comprises the following steps: acquiring a first test parameter of a current batch of chips; calculating the proportion of the edge chips of the current batch of chips according to the first test parameter, wherein the proportion of the edge chips is the proportion of the edge chips in the current batch of chips, and the edge chips are the chips of which the numerical value of the first test parameter falls into a qualified range but exceeds an edge range; and when the difference between the edge chip proportion and the reference edge chip proportion is larger than a first preset prompt value, determining that the chip test parameter abnormity is detected, wherein the reference edge chip proportion corresponds to the preset test item. By the scheme of the invention, the automatic detection and pushing of the chip test parameter abnormity can be realized, so that the chip reliability problem and the problems possibly existing in the production process and the test link can be early warned before the Bin failure actually occurs.
Description
Technical Field
The invention relates to the technical field of chip manufacturing and testing, in particular to a method for detecting chip testing parameter abnormity, a storage medium and a terminal.
Background
When testing the chip, the testing machine will sequentially perform hundreds or even thousands of tests on the chip according to the test program, and the result obtained by the test is called as the test parameter. Comparing the value (i.e. test result) of each test parameter measured by the test program with the chip test specification (spec) of the corresponding test item specified in the chip specification to determine whether the value is good or bad, and if the value of the test parameter measured by a certain test item of the chip does not meet the requirement of the chip test specification, determining that the chip fails to work according to the corresponding relation between the test parameter and the Bin. Wherein, Bin can be used to characterize the classification of a chip, and is used to distinguish whether the chip is a chip with normal function. Further, when the chip cannot work normally, Bin can be used to distinguish which part of the chip cannot be realized normally.
For chip test parameters, the test data compression file per wafer (wafer) is up to several hundred megabytes (Bytes) due to the enormous amount of test data. At present, many companies are basically in the stage of engineering analysis, and when a certain Bin fails abnormally, the testing parameter value of the Bin is analyzed, so that a direction is provided for failure reason analysis.
Current chip test parameters are also commonly used for lot (lot) or wafer (wafer) handling (placement). Specifically, whether the goods can be put, whether the customer needs to be informed of the handling, whether some good chips need to be marked as bad chips and not to be shipped, and the like are determined according to manual experience and failure reasons obtained based on analysis of chip testing parameters.
In summary, the utilization of chip test parameters in the prior art is limited to failure analysis related scenes, on one hand, the abnormal value screening and failure analysis are performed with human intervention, and on the other hand, the existing chip test parameters only play a role after Bin failure occurs and cannot play an early warning role before Bin failure.
Disclosure of Invention
The invention solves the technical problem of how to realize the automatic detection of the abnormal chip test parameters.
To solve the above technical problems, an embodiment of the present invention provides a method for detecting chip test parameter abnormality, including: acquiring a first test parameter of a current batch of chips, wherein the first test parameter is a test result of the current batch of chips in a preset test item; calculating the proportion of the edge chips of the current batch of chips according to the first test parameter, wherein the proportion of the edge chips is the proportion of the edge chips in the current batch of chips, and the edge chips are the chips of which the numerical value of the first test parameter falls into a qualified range but exceeds an edge range; and when the difference between the edge chip proportion and the reference edge chip proportion is larger than a first preset prompt value, determining that the chip test parameter abnormity is detected, wherein the reference edge chip proportion corresponds to the preset test item.
Optionally, the step of calculating the reference edge chip ratio includes: acquiring a second test parameter of the historical batch of chips, wherein the second test parameter is a test result of the historical batch of chips in the preset test item; acquiring the number of qualified chips in the historical batch of chips and yield test buffer data according to the second test parameter, wherein the yield test buffer data is used for representing the numerical distribution of the second test parameter; narrowing the qualified range based on the yield test buffer data to obtain the edge range; screening a first number of chips from the historical batch of chips according to the edge range and the qualified range, wherein the first number of chips are chips with the numerical value of a second test parameter falling into the qualified range but exceeding the edge range; determining a ratio of the first number to the number of qualified chips as the reference edge chip ratio.
Optionally, the obtaining yield test buffer data of the historical batch of chips according to the second test parameter includes: calculating the four-bit distance of the second test parameter to obtain the yield test buffer data; or calculating the standard deviation of the second test parameter to obtain the yield test buffer data.
Optionally, the calculating the edge chip proportion of the current batch of chips according to the first test parameter includes: acquiring the number of qualified chips in the current batch of chips; screening the chips in the current batch to obtain the edge chips according to the qualified range and the edge range; and determining the ratio of the number of the edge chips obtained by screening to the number of the qualified chips in the current batch of chips as the edge chip proportion of the current batch of chips.
Optionally, the detection method further includes: counting the average edge chip proportion of all batches of chips detected in a preset detection period; and when the difference value between the average edge chip proportion and the reference edge chip proportion is larger than a second preset prompt value, determining that the chip test parameter abnormity is detected.
Optionally, the first preset prompt value and the second preset prompt value are both determined according to the goods return rate of the chip, and the second preset prompt value is smaller than the first preset prompt value.
Optionally, the detection method further includes: acquiring the variation trend of the numerical values of third test parameters of a plurality of batches of chips along with time within a preset time period, wherein the third test parameters are the test results of the plurality of batches of chips in the preset test items; and when the variation trend is continuously beyond the control range, determining that the chip test parameter abnormality is detected.
Optionally, the process of determining the control range includes the following steps: obtaining a fourth test parameter of historical multi-batch chips, wherein the fourth test parameter is a test result of the historical multi-batch chips in the preset test item; calculating key statistical values of the fourth test parameters; and determining a control range according to the key statistical value and the standard deviation of the key statistical value.
Optionally, the obtaining a trend of the values of the third test parameters of the multiple batches of chips along with time within the preset time period includes: calculating key statistical values of the third test parameters; and drawing the variation trend of the key statistical values along with time.
Optionally, the key statistics are selected from: median, 95 quantile, 5 quantile, 99 quantile and 1 quantile.
In order to solve the above technical problem, an embodiment of the present invention further provides a device for detecting chip test parameter abnormality, including: the device comprises an acquisition module, a test module and a control module, wherein the acquisition module is used for acquiring a first test parameter of a current batch of chips, and the first test parameter is a test result of the current batch of chips in a preset test item; the calculation module is used for calculating the edge chip proportion of the current batch of chips according to the first test parameter, wherein the edge chip proportion is the proportion of edge chips in the current batch of chips, and the edge chips are chips of which the numerical value of the first test parameter falls into a qualified range but exceeds the edge range; and the detection module determines to detect that the chip test parameter is abnormal when the difference between the edge chip proportion and the reference edge chip proportion is greater than a first preset prompt value, wherein the reference edge chip proportion corresponds to the preset test item.
To solve the above technical problem, an embodiment of the present invention further provides a storage medium, on which a computer program is stored, and the computer program executes the steps of the above method when being executed by a processor.
In order to solve the above technical problem, an embodiment of the present invention further provides a terminal, including a memory and a processor, where the memory stores a computer program capable of running on the processor, and the processor executes the steps of the method when running the computer program.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a method for detecting chip test parameter abnormity, which comprises the following steps: acquiring a first test parameter of a current batch of chips, wherein the first test parameter is a test result of the current batch of chips in a preset test item; calculating the proportion of the edge chips of the current batch of chips according to the first test parameter, wherein the proportion of the edge chips is the proportion of the edge chips in the current batch of chips, and the edge chips are the chips of which the numerical value of the first test parameter falls into a qualified range but exceeds an edge range; and when the difference between the edge chip proportion and the reference edge chip proportion is larger than a first preset prompt value, determining that the chip test parameter abnormity is detected, wherein the reference edge chip proportion corresponds to the preset test item.
By adopting the embodiment, the abnormal chip test parameters can be automatically detected and pushed, so that the chip reliability problem and the possible problems in the production process and the test link can be early warned before the Bin failure actually occurs. Specifically, by analyzing the edge chip proportion in the current batch of chips, the test result distribution condition of the current batch of chips in the preset test items can be accurately obtained. Further, if the ratio of the edge chips of the current batch is increased to a value that is greater than a first preset prompt value, it indicates that the value distribution of the first test parameter deviates from the reference distribution, that is, the chip test parameter is abnormal. Therefore, the embodiment can realize automatic detection of the test parameter abnormity. When the numerical distribution of the first test parameter deviates from the reference distribution, even if the numerical change of the first test parameter does not cause Bin failure, the abnormal deviation condition can be accurately and automatically detected and early warning can be timely sent out by adopting the embodiment, so that the problem of chip reliability is favorably solved.
Further, the detection method further comprises: acquiring the variation trend of the numerical values of third test parameters of a plurality of batches of chips along with time within a preset time period, wherein the third test parameters are the test results of the plurality of batches of chips in the preset test items; and when the variation trend is continuously beyond the control range, determining that the chip test parameter abnormality is detected.
Therefore, potential production process and test problems can be detected as early as possible, and the result process and test defects are possible before Bin fails. Specifically, when the values of the third testing parameters of a plurality of batches of chips in the same preset testing item are continuously increased or continuously decreased for a period of time, even if the testing result still falls within the qualified range specified by the chip testing specification, the deviation of a certain process parameter of the production line is very likely to mean in essence, and if the deviation is not solved in advance, the problem of low yield of a large batch may occur later. Therefore, the present embodiment sets the control range and matches with the time variation trend of the test result to realize automatic detection. When the variation trend continuously exceeds the control range, the numerical value of the third test parameter is shown to approach the upper limit or the lower limit of the qualified range, and early warning needs to be sent out.
Drawings
FIG. 1 is a graph of a distribution of values of a chip test parameter;
FIG. 2 is a graph of the trend of values of chip test parameters over time;
FIG. 3 is a flowchart illustrating a method for detecting abnormal chip test parameters according to an embodiment of the present invention;
FIG. 4 is a graph of the time-dependent variation of the difference between the edge chip ratio of the test item IDDQ _ GPU and the reference edge chip ratio for a plurality of batches of chips monitored over time;
FIG. 5 is a graph of the distribution of values of the test parameters of the test item IDDQ _ GPU for the lot A chips of FIG. 4;
FIG. 6 is a time-dependent trend of the difference between the edge chip ratio of the test item Vmin _ CPU and the reference edge chip ratio of a plurality of batches of chips monitored over time;
FIG. 7 is a graph showing the distribution of the values of the test parameters of all lots of chips in Vmin _ CPU under test item from week 20 in FIG. 6;
fig. 8 is a schematic structural diagram of a device for detecting abnormal chip test parameters according to an embodiment of the present invention.
Detailed Description
As background art, the utilization of chip test parameters in the prior art is limited to failure analysis related scenes, on one hand, human intervention is needed to perform exception value screening and failure analysis, and on the other hand, the existing chip test parameters only play a role after Bin failure occurs and cannot play an early warning role before Bin failure.
The inventor of the present application has found through analysis that, for the same test item of the same product, the value distribution range of the test result (i.e. the test parameter) of the test item for all chips has a reference distribution. This baseline profile may be wafer level, Fab manufacturing lot level, or packaging lot level. Even if the value variation of the test parameter does not cause Bin failure, it is desirable to detect such a wafer or lot having abnormal test parameters and to have as few false alarms (false alarms) as possible if the value distribution deviates from the reference distribution.
From the inventor's classification, the abnormal chip testing parameters generally include four situations as shown in fig. 1 and fig. 2, where each curve in fig. 1 represents the value distribution of a certain testing parameter of a wafer or a lot of chips, and the curve in fig. 2 represents the time variation trend of the value of a certain testing parameter of a plurality of wafers or lots of chips over a period of time. Fig. 1 and 2 are specific illustrations of the distribution and trend of values of test parameters in a particular test item.
The four chip test parameter anomalies are listed below:
1. shift in the value distribution of the test parameter (shift), as shown by curve 11 in FIG. 1;
2. the numerical distribution of the test parameter broadens, as shown by curve 12 in FIG. 1; 3. the trailing (long tail) of the numerical distribution of the test results of the test parameters, as shown by curve 13 in fig. 1;
4. the values of the test parameters are continuously higher or lower, and fig. 2 shows an example of continuously higher values and continuously lower values.
For the above four abnormal conditions of chip test parameters, the chip is still determined as a "good" chip in the prior art when the test parameters are obtained, because the values of the test parameters still fall within the qualified range specified by the specification (spec). Taking fig. 1 as an example, the qualified line 14 shown in fig. 1 defines the upper limit of the chip passing the test item, a chip whose test parameter is greater than the value represented by the qualified line 14 is determined as a "bad" chip, and a chip whose test parameter is less than the value represented by the qualified line 14 is determined as a "good" chip. Taking fig. 2 as an example, the upper specification line 21 and the lower specification line 22 shown in fig. 2 together define the qualified range, chips with test results larger than the value represented by the upper specification line 21 and chips with test results smaller than the value represented by the lower specification line 22 are determined as "bad" chips, and chips with test results falling between the upper specification line 21 and the lower specification line 22 are determined as "good" chips.
Taking curve 13 as an example, since the values of the test parameters always fall to the left of the qualified line 14, the chips of the wafer or lot represented by curve 13 are "good" chips in the usual sense. However, it can be seen that the specific values of the test parameters for this batch of chips are actually very close to the qualified line 14, especially the circled portion of the figure, and these chips may have reliability problems after long-term use. The prior art can not detect and identify the situations either manually or by computer.
Taking the trend of the value of the test parameter over time as shown in fig. 2 as an example, although the value of the test parameter is always located between the upper specification line 21 and the lower specification line 22 in the plotting period shown in fig. 2, the value of the test parameter is actually continuously higher as time advances. This means that a deviation in a certain process parameter of the production line may occur, which if not solved in advance, may then lead to a large number of low yield problems. Similarly, the prior art is not able to detect and identify such situations, either manually or by computer.
The embodiment of the invention provides a method for detecting chip test parameter abnormity, which comprises the following steps: acquiring a first test parameter of a current batch of chips, wherein the first test parameter is a test result of the current batch of chips in a preset test item; calculating the proportion of the edge chips of the current batch of chips according to the first test parameter, wherein the proportion of the edge chips is the proportion of the edge chips in the current batch of chips, and the edge chips are the chips of which the numerical value of the first test parameter falls into a qualified range but exceeds an edge range; and when the difference between the edge chip proportion and the reference edge chip proportion is larger than a first preset prompt value, determining that the chip test parameter abnormity is detected, wherein the reference edge chip proportion corresponds to the preset test item.
By adopting the embodiment, the abnormal chip test parameters can be automatically detected and pushed, so that the chip reliability problem and the possible problems in the production process and the test link can be early warned before the Bin failure actually occurs. Specifically, by analyzing the edge chip proportion in the current batch of chips, the test result distribution condition of the current batch of chips in the preset test items can be accurately obtained. Further, if the ratio of the edge chips of the current batch is increased to a value that is greater than a first preset prompt value, it indicates that the value distribution of the first test parameter deviates from the reference distribution, that is, the chip test parameter is abnormal. Therefore, the embodiment can realize automatic detection of the test parameter abnormity. When the numerical distribution of the first test parameter deviates from the reference distribution, even if the numerical change of the first test parameter does not cause Bin failure, the abnormal deviation condition can be accurately and automatically detected and early warning can be timely sent out by adopting the embodiment, so that the problem of chip reliability is favorably solved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 is a flowchart of a method for detecting abnormal chip test parameters according to an embodiment of the present invention.
The embodiment can be applied to a chip manufacturing scene, and chip manufacturing enterprises can more accurately carry out batch or wafer disposal and shipment early warning by timely and automatically detecting abnormal conditions of chip testing parameters. The detection method may be performed by a device that performs or assists chip testing, for example, an Automatic Test Equipment (ATE) or a computing device coupled to the ATE locally or remotely.
Specifically, referring to fig. 3, the method for detecting abnormal chip test parameters in this embodiment may include the following steps:
step S101, obtaining a first test parameter of a current batch of chips, wherein the first test parameter is a test result of the current batch of chips in a preset test item;
step S102, calculating the proportion of the edge chips of the current batch of chips according to the first test parameter, wherein the proportion of the edge chips is the proportion of the edge chips in the current batch of chips, and the edge chips are the chips of which the numerical value of the first test parameter falls into a qualified range but exceeds the edge range;
step S103, when the difference between the edge chip proportion and the reference edge chip proportion is larger than a first preset prompt value, determining that the detected chip testing parameter is abnormal, wherein the reference edge chip proportion corresponds to the preset testing item.
More specifically, the preset test item may be any test item that the test machine performs on the chip according to a test program. The embodiment can be repeatedly executed, and the test results of different preset test items are obtained during each execution so as to judge whether the first test parameter of the current batch of chips in the preset test item is abnormal or not.
Further, the first test parameter may include a test result of each chip in the current batch of chips in the preset test item. For convenience of description, the test results of the preset test items for the single chips in the current batch are also collectively referred to as the first test parameters.
Further, the present embodiment can be implemented in batch units to detect whether the testing parameters of the chips in a specific batch are abnormal in the predetermined testing items. It should be noted that, in practical applications, the embodiment may also be implemented in units of wafers (wafers).
In one embodiment, the current batch of chips refers to a batch of chips that need to detect whether the test data is abnormal or not during the execution of the embodiment.
In the step S101, the test result may be obtained by the test machine in real time during the process of testing the current chip according to the test program.
Or the test result may be obtained from a preset database, where the preset database is used to store the test result obtained after the test machine has historically tested one or more batches of chips according to a test program.
In one implementation, the edge range and the qualified range are in one-to-one correspondence with preset test items. That is, each preset test item is provided with a corresponding edge range and a pass range.
The pass range is a preset chip test specification, that is, the pass range refers to the upper limit and/or the lower limit of the specification that the chip specified in the chip specification should meet in the preset test item, such as the qualified line 14 shown in fig. 1, the upper line 21 of the specification shown in fig. 2, and the lower line 22 of the specification.
The edge range is an updated chip test specification narrowed on the basis of a preset chip test specification, that is, the edge range is an upper limit and/or a lower limit narrowed on the basis of a qualified range. For chips with values of the test parameters falling within the acceptable range but exceeding the marginal range, it is indicated that the test results of such chips in the predetermined test items are substantially very close to the critical line defined by the acceptable range (as circled in fig. 1). Experiments show that the reliability problem is easy to occur in the long-term use process of the chip, so that the scheme of the embodiment automatically detects the chip with the hidden reliability danger by additionally arranging the edge range, and the automatic detection of the distribution movement, the widening and the tailing conditions of the test parameters shown in the figure 1 becomes possible.
Further, the degree of shrinkage of the margin compared to the qualified range may be determined by statistical analysis of historical data, wherein the historical data includes historical test parameters of the plurality of batches of chips in the predetermined test item. By reasonably setting the edge range, false alarm can be avoided while the value distribution of the test parameters is effectively detected to approach the boundary of the qualified range.
In one embodiment, a second testing parameter of a plurality of batches of chips with historical yields reaching a reference yield may be selected, and the edge range may be determined based on the second testing parameter, where the second testing parameter is a testing result of the historical batches of chips in the preset testing item. For example, 20 lots of chips with historical yields close to the reference yield may be selected and second testing parameters for the lots of chips may be obtained.
Specifically, all the lots of the chip product in the near term (for example, the last quarter) may be selected, the average yield (average) and the standard deviation (sigma) of the yield may be calculated, and the average value recalculated after the wafers with the yields lower than average-6 × sigma are removed may be used as the reference yield of the chip product.
The average yield may be the sum and average of the respective yields of all the batches of chips. For any batch of chips, the yield of the batch of chips refers to the ratio of the number of qualified chips to the number of valid chips in the batch of chips.
The standard deviation of the yield may be a total standard deviation
Wherein n is the total number of recent batches of all the batches of the chip product, xiFor the yield of the ith lot of chips,
is the average yield.
The standard deviation of the yield may also be a sample standard deviation
Further, a second test parameter of a pass chip (pass die) in the plurality of batches of chips may be obtained. The qualified chip refers to a chip whose test results of various test parameters obtained by testing according to a test program all fall within a qualified range specified by a chip specification, namely a 'good' chip in a general sense.
Further, yield test buffer data of the historical batch of chips can be obtained according to the second test parameter, and the yield test buffer data is used for representing the numerical value distribution of the second test parameter. In particular, the numerical distribution may be used to characterize numerical fluctuations and distributions of the second test parameter. For example, the numerical distribution may be an Inter Quartile Range (IQR) of the second test parameter.
Further, a shrinkage limit can be determined according to the yield test buffer data, and the qualified range of the preset test item is shrunk according to the shrinkage limit, so that the edge range of the preset test item is obtained.
Assuming that the qualified range of the preset test item only includes a lower limit (low spec), the corresponding edge range may be the lower limit plus IQR times a preset coefficient. Wherein the predetermined coefficient may be 0.5.
Assuming that the qualified range of the preset test item only includes an upper limit (high spec), the corresponding edge range may be the upper limit minus IQR multiplied by a preset coefficient. Wherein the predetermined coefficient may be 0.5.
Assuming that the pass range of the preset test item includes a lower limit and an upper limit, i.e., [ low spec, high spec ], the corresponding edge range may be [ low spec +0.5 × IQR, high spec-0.5 × IQR ].
The reason why only the test result of the qualified chip is considered is that the present embodiment focuses on the abnormality detection of the test parameters whose test results are within the qualified range. Furthermore, by combining the resistance of the IQR to the abnormal value, the specific implementation can objectively and accurately represent the numerical distribution condition of the test parameter of the test result in the qualified range.
In one variation, the quartering distance may be replaced with a standard deviation (sigma). That is, the standard deviation of the second test parameter may be calculated to obtain the yield test buffer data.
In one embodiment, chips with test parameters having values between the margin and the pass range may be referred to as margin chips (margin die) to characterize the chips as chips of the adjacent chip test specification, i.e., chips that may have reliability problems as described above.
In the step S102, the edge chip ratio may be calculated based on a formula of a margin bit ratio, wherein the margin bit ratio is the edge chip ratio, the margin _ bit _ count is the number of edge chips in the current batch of chips, and the good _ bit _ count is the number of qualified chips in the current batch of chips.
Specifically, the qualified chips in the current batch of chips are good chips for actual shipment.
Further, for the current batch of chips, the margin _ die _ count is the number of chips in the current batch of chips, in which the value of the first test parameter falls within the qualified range but exceeds the margin range.
In one implementation, the reference edge chip fraction may be determined by statistical analysis of historical data, wherein the historical data includes second test parameters for a plurality of batches of chips historically. Specifically, the reference edge chip ratio can be used to describe the ratio of edge chips when the numerical distribution of the chip test parameter is the reference distribution. The values of the test parameters in the baseline distribution fall within the pass range and are further from the edge of the pass range, as shown in fig. 1.
For example, after the edge range is determined, for the historical multiple batches of chips for determining the edge range, a first number of chips may be obtained by screening according to the second test results of the batches of chips, where the first number of chips is a chip with a value of the second test parameter falling within the qualified range but exceeding the edge range, that is, an edge chip in the historical multiple batches of chips. Further, the first number is divided by the number of good chips that are finally shipped in the plurality of historical batches of chips (i.e., the number of qualified chips in the plurality of historical batches of chips), so as to obtain the reference edge chip ratio (R) which is recorded as RMD_Baseline。
In one implementation, the step S102 may include the steps of: acquiring the number of qualified chips in the current batch of chips; screening the chips in the current batch to obtain the edge chips according to the qualified range and the edge range; and determining the ratio of the number of the edge chips obtained by screening to the number of the qualified chips in the current batch of chips as the edge chip proportion of the current batch of chips.
In one embodiment, in the step S103, the formula i _ Δ R is usedMD-Lotx＝i_RMD_Lotx-i_RMD_baselineAnd calculating to obtain the difference between the edge chip proportion and the reference edge chip proportion. Wherein, i _ Δ RMD-LotxIs the difference between the edge chip proportion of the ith preset test item and the corresponding reference edge chip proportion of the x batch of chips, i _ RMD_LotxChip proportion i _ R of ith preset test item for x batch of chipsMD_baselineThe reference edge chip proportion of the ith preset test item.
In one embodiment, the first predetermined hint value may be determined based on a return rate of the chip, such as a part per million (ppm) characterization. Specifically, the return rate of the chips due to early failure of the chips after shipment to the terminal can be characterized by ppm.
Further, the ppm requirements of different chip products are different, and the return rate of the shipped chips per fixed period (e.g., weekly, monthly or quarterly) cannot exceed the agreed ppm.
For example, the first preset cue value may be 1000 ppm.
In one embodiment, the detection method of the present embodiment may further include: counting the average edge chip proportion of all batches of chips detected in a preset detection period; and when the difference value between the average edge chip proportion and the reference edge chip proportion is larger than a second preset prompt value, determining that the chip test parameter abnormity is detected.
Specifically, the second preset prompt value may be determined according to a return rate of the chip, and the second preset prompt value is smaller than the first preset prompt value. For example, the second preset cue value may be 500 ppm.
For example, the average edge chip proportion of all batches of chips manufactured in the present period may be counted every 7 days, and if the average edge chip proportion is greater than the second preset prompt value, it is determined that the chips manufactured in the present period have abnormal test parameters.
In one embodiment, when it is determined that the chip test parameter is detected to be abnormal, a prompt message may be sent to the outside to prompt the detection result.
Specifically, the prompt information may be sent to a quality inspector, a quality controller, and the like of the chip manufacturing enterprise, who need to obtain abnormal information of the chip test parameters.
Further, the prompt message may be sent to a server, such as a computer, where the person logs in, or may be sent to a personal terminal, such as a mobile phone or an IPAD.
For example, when the reminder is triggered, the reminder may be automatically generated by the device executing the present embodiment and transmitted to the server and/or the personal terminal described above.
Further, the prompt information may include a batch in which the test parameter is abnormal, a numerical distribution of the abnormal test parameter, an analysis of a reason for the abnormality, and the like.
This implementation converts the numerical distribution of the test parameters from graphical to numerical descriptions. That is, the huge scalar data result formed by one value of the original chip for each test parameter is converted into a calculation value (i.e. margin) which can be used to describe the reliability of each test parameter. Therefore, the detection of the test parameter abnormity is realized while the data volume required to be stored is reduced by thousands of times.
Further, the implementation can realize the abnormality detection and simultaneously reduce false alarms as much as possible, thereby ensuring the accuracy of the system operating the scheme of the embodiment. That is, even if the numerical distribution of a certain test parameter of a certain batch of chips has a discrepancy such as a distribution broadening, a tailing, etc., as long as the clutch grid range is still relatively far or the difference between the edge chip proportion and the corresponding reference edge chip proportion is not increased, no prompt message is sent, and the user is prevented from being troubled.
Further, the present embodiment can be run by the system at regular time to realize automatic calculation and user push for anomaly detection.
Further, flexible feedback correction can be achieved by entering the notion of edge chips and ppm. Specifically, the method can be flexibly optimized according to the actual condition of the product, and corrects each test parameter to determine the preset coefficient, the first preset prompt value and the second preset prompt value of the edge range by combining the feedback of the classification of the reasons of the shipment return rate (namely how much ppm return rate is contributed by different test failures respectively). Therefore, the ppm calculated by each test parameter is ensured to be as close as possible to the actual value of the final chip return rate, and the early warning of batch disposal and shipment is accurately known.
In one embodiment, the detection method of the present embodiment may further include the steps of: acquiring the variation trend of the numerical values of third test parameters of a plurality of batches of chips along with time within a preset time period, wherein the third test parameters are the test results of the plurality of batches of chips in the preset test items; and when the variation trend is continuously beyond the control range, determining that the chip test parameter abnormality is detected.
Specifically, the control range may be an upper limit and/or a lower limit narrowed on the basis of the acceptable range. When the trend of the value of the third testing parameter over time is continuously beyond the control range, it indicates that the testing results of a plurality of batches of chips manufactured in a period of time are approaching towards the edge of the qualified range, such as the continuously higher trend in fig. 2. Experiments show that the occurrence of the variation trend most possibly means that a certain process parameter of a chip production line deviates, and if the deviation is not interfered, the value of the corresponding test parameter of the chip still manufactured according to the current process in the future most possibly exceeds the qualified range. Therefore, the embodiment of the invention automatically detects the deviation of the process parameters by increasing the control range, so as to enable the automatic detection of the condition that the value of the test parameter shown in fig. 2 becomes continuously higher or lower.
Further, the degree of narrowing of the control range compared to the qualified range may be determined by statistical analysis of historical data, where the historical data includes fourth test parameters of multiple batches of chips in history, and the fourth test parameters are test results of the multiple batches of chips in the history in the preset test item. By reasonably setting the control range, false alarm can be avoided while the numerical distribution of the effective detection test parameters continuously and gradually approaches to the boundary of the qualified range.
In one implementation, a fourth test parameter may be selected for qualified chips in the plurality of batches of chips having a historical yield that meets the reference yield.
Further, key statistics for the fourth test parameter may be calculated. For example, the key statistics may be selected from: median, 95 quantile, 5 quantile, 99 quantile and 1 quantile.
Further, a control range may be determined according to the key statistics and the standard deviation of the key statistics.
Assuming that the qualifying range for the test parameter includes only a lower bound (low spec), the corresponding control range may be static-3 × static value's sigma, where static is the key statistical value and static value's sigma is the standard deviation of the key statistical value. The control range is the lower limit. In scenarios where only the lower bound is considered, the high-side percentiles such as the 95 quantile and the 99 quantile may not be considered.
Assuming that the qualified range of the test parameter only includes an upper limit (high spec), the corresponding control range may be static +3 × static value's sigma, where static is the key statistical value and static value's sigma is the standard deviation of the key statistical value. The control range is the upper limit. In scenarios where only the upper limit is considered, the low-side percentiles such as the 1-quantile and the 5-quantile may not be considered.
Assuming that the qualified range of the test parameter includes a lower limit and an upper limit, i.e., [ low spec, high spec ], the corresponding control range may be [ static-3 × static value's sigma, static +3 × static value's sigma ].
The value 3 of the preset coefficient adopted in the above assumption is only used for example, and in practical applications, the specific value of the preset coefficient may be adjusted as needed.
In one implementation, key statistics for the third test parameter may be calculated. Further, the trend of the key statistics over time may be plotted.
Specifically, if any one of the key statistics exceeds the control range in a predetermined number of consecutive batches, it may be determined that the chip test parameter abnormality is detected.
For example, the preset number may be 8. In practical application, the preset quantity can be optimized according to the actual condition of the product.
By adopting the scheme of the embodiment, the abnormal chip test parameters can be automatically detected and pushed, so that the chip reliability problem and the possible problems in the production process and the test link can be early warned before the Bin failure actually occurs. Specifically, by analyzing the edge chip proportion in the current batch of chips, the test result distribution condition of the current batch of chips in the preset test items can be accurately obtained. Further, if the ratio of the edge chips of the current batch is increased to a value that is greater than a first preset prompt value, it indicates that the value distribution of the first test parameter deviates from the reference distribution, that is, the chip test parameter is abnormal. Therefore, the embodiment can realize automatic detection of the test parameter abnormity. When the numerical distribution of the first test parameter deviates from the reference distribution, even if the numerical change of the first test parameter does not cause Bin failure, the abnormal deviation condition can be accurately and automatically detected and early warning can be timely sent out by adopting the embodiment, so that the problem of chip reliability is favorably solved.
Furthermore, potential production process and test problems can be detected as early as possible, so that the process and test defects are possible before Bin fails. Specifically, when the test result values of a plurality of batches of chips in the same test parameter are continuously increased or decreased for a period of time, even if the test result values still fall within the qualified range specified by the specification, the deviation of a certain process parameter of the production line is very likely to be actually implied, and if the deviation is not solved in advance, a lot of low yield problems may occur later. Therefore, the present embodiment sets the control range and matches with the time variation trend of the test result to realize automatic detection. When the variation trend continuously exceeds the control range, the test result of the test parameters corresponding to the plurality of batches of chips is close to the upper limit or the lower limit of the qualified range, and early warning needs to be sent out.
Further, for failure conditions outside the test specification, it can be characterized by a specific Bin failure rate.
In a first exemplary application scenario, FIG. 4 illustrates a sessionThe difference between the edge chip ratio of the test item IDDQ _ GPU and the reference edge chip ratio (denoted as IDDQ _ GPU _ Δ R) of the multiple batches of chips obtained by inter-monitoringMDUnit ppm) over time, and fig. 5 is a distribution of values of the test parameters of the lot a chips in fig. 4 under the test item IDDQ _ GPU.
Fig. 4 shows that 1000ppm is the first preset hint value and 500ppm is the second preset hint value for the test item IDDQ _ GPU.
Referring to fig. 4, it can be seen that lot a has exceeded the first predetermined hint value of 1000ppm at an edge chip rate of 1200ppm for the test item IDDQ _ GPU. Although it is seen from FIG. 5 that the distribution of values of the test parameters of lot A in the test item IDDQ _ GPU does not trigger qualified lines, the distribution of values of the lot A substantially deviates from the baseline distribution of the test item IDDQ _ GPU.
Therefore, according to the embodiment, by setting the edge line, the condition that the value distribution of the test parameter of the test item IDDQ _ GPU such as the lot a is smeared compared with the reference distribution is automatically detected, and a prompt is sent.
In a second exemplary application scenario, FIG. 6 shows the difference between the edge chip ratio of the test item Vmin _ CPU and the reference edge chip ratio (denoted as Vmin _ CPU _ Δ R) of multiple batches of chips monitored over timeMDUnit ppm) over time, wherein the edge chip proportion at week 20 is 800ppm and has exceeded the second preset hint value of 500ppm, fig. 7 is the distribution of the values of the test parameters of Vmin _ CPU for all the lots of chips tested at week 20 in fig. 6. The solid line in fig. 7 represents the reference distribution, and the broken line represents the numerical distribution of the test parameters of all the test lots at week 20 in fig. 6 at test item Vmin _ CPU.
Fig. 8 is a schematic structural diagram of a device for detecting abnormal chip test parameters according to an embodiment of the present invention. Those skilled in the art understand that the device 8 for detecting abnormal chip test parameters in this embodiment can be used to implement the method of the embodiment described in fig. 3.
Specifically, referring to fig. 8, the device 8 for detecting abnormal chip test parameters in this embodiment may include: an obtaining module 81, configured to obtain a first test parameter of a current batch of chips, where the first test parameter is a test result of the current batch of chips in a preset test item; a calculating module 82, configured to calculate an edge chip ratio of the current batch of chips according to the first testing parameter, where the edge chip ratio is a ratio of edge chips in the current batch of chips, and the edge chips are chips whose values of the first testing parameter fall within a qualified range but exceed the edge range; and the detection module 83 determines to detect that the chip test parameter is abnormal when the difference between the edge chip proportion and the reference edge chip proportion is greater than a first preset prompt value, wherein the reference edge chip proportion corresponds to the preset test item.
For more details of the working principle and working mode of the chip test parameter abnormality detection device 8, reference may be made to the related description in fig. 3, which is not repeated herein.
Further, the embodiment of the present invention also discloses a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method technical solution described in the embodiment shown in fig. 3 is executed. Preferably, the storage medium may include a computer-readable storage medium such as a non-volatile (non-volatile) memory or a non-transitory (non-transient) memory. The storage medium may include ROM, RAM, magnetic or optical disks, etc.
Further, an embodiment of the present invention further discloses a terminal, which includes a memory and a processor, where the memory stores a computer program capable of running on the processor, and the processor executes the technical solution of the method in the embodiment shown in fig. 3 when running the computer program. Specifically, the terminal may be a computer, a server, or the like.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method for detecting chip test parameter abnormality is characterized by comprising the following steps:
acquiring a first test parameter of a current batch of chips, wherein the first test parameter is a test result of the current batch of chips in a preset test item;
calculating the proportion of the edge chips of the current batch of chips according to the first test parameter, wherein the proportion of the edge chips is the proportion of the edge chips in the current batch of chips, and the edge chips are the chips of which the numerical value of the first test parameter falls into a qualified range but exceeds an edge range;
and when the difference between the edge chip proportion and the reference edge chip proportion is larger than a first preset prompt value, determining that the chip test parameter abnormity is detected, wherein the reference edge chip proportion corresponds to the preset test item.
2. The detection method as claimed in claim 1, wherein the step of calculating the reference edge chip ratio comprises:
acquiring a second test parameter of the historical batch of chips, wherein the second test parameter is a test result of the historical batch of chips in the preset test item;
acquiring the number of qualified chips in the historical batch of chips and yield test buffer data according to the second test parameter, wherein the yield test buffer data is used for representing the numerical distribution of the second test parameter;
narrowing the qualified range based on the yield test buffer data to obtain the edge range;
screening a first number of chips from the historical batch of chips according to the edge range and the qualified range, wherein the first number of chips are chips with the numerical value of a second test parameter falling into the qualified range but exceeding the edge range;
determining a ratio of the first number to the number of qualified chips as the reference edge chip ratio.
3. The detecting method as claimed in claim 2, wherein said obtaining yield test buffer data of said historical lots of chips according to said second test parameter comprises:
calculating the four-bit distance of the second test parameter to obtain the yield test buffer data; or calculating the standard deviation of the second test parameter to obtain the yield test buffer data.
4. The detection method as claimed in any one of claims 1 to 3, wherein said calculating the edge chip proportion of the current batch of chips according to the first test parameter comprises:
acquiring the number of qualified chips in the current batch of chips;
screening the chips in the current batch to obtain the edge chips according to the qualified range and the edge range;
and determining the ratio of the number of the edge chips obtained by screening to the number of the qualified chips in the current batch of chips as the edge chip proportion of the current batch of chips.
5. A detection method as claimed in claim 1, further comprising:
counting the average edge chip proportion of all batches of chips detected in a preset detection period;
and when the difference value between the average edge chip proportion and the reference edge chip proportion is larger than a second preset prompt value, determining that the chip test parameter abnormity is detected.
6. A detection method as claimed in claim 5, wherein said first predetermined hint value and said second predetermined hint value are both determined according to a return rate of said chip, and said second predetermined hint value is smaller than said first predetermined hint value.
7. A detection method as claimed in any one of claims 1 to 3 or 5 or 6, further comprising:
acquiring the variation trend of the numerical values of third test parameters of a plurality of batches of chips along with time within a preset time period, wherein the third test parameters are the test results of the plurality of batches of chips in the preset test items;
and when the variation trend is continuously beyond the control range, determining that the chip test parameter abnormality is detected.
8. A detection method as claimed in claim 7, wherein said control range determination process comprises the following steps:
obtaining a fourth test parameter of historical multi-batch chips, wherein the fourth test parameter is a test result of the historical multi-batch chips in the preset test item;
calculating key statistical values of the fourth test parameters;
and determining a control range according to the key statistical value and the standard deviation of the key statistical value.
9. A storage medium having a computer program stored thereon, the computer program, when being executed by a processor, performing the steps of the method according to any of the claims 1 to 8.
10. A terminal comprising a memory and a processor, the memory having stored thereon a computer program operable on the processor, wherein the processor, when executing the computer program, performs the steps of the method of any of claims 1 to 8.
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