CN112151449A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112151449A
CN112151449A CN201910579466.4A CN201910579466A CN112151449A CN 112151449 A CN112151449 A CN 112151449A CN 201910579466 A CN201910579466 A CN 201910579466A CN 112151449 A CN112151449 A CN 112151449A
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layer
forming
side wall
sidewall
semiconductor structure
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a base, wherein the base comprises a substrate and a gate structure positioned on the substrate, and the extending direction vertical to the gate structure is transverse; forming a first side wall material layer on the side wall of the grid structure; after the first side wall material layer is formed, etching the substrates on two sides of the grid structure to form a groove; after the groove is formed, thinning the first side wall material layer from the transverse direction to form a first side wall layer; and forming a source-drain doped layer in the groove exposed by the first side wall layer. According to the embodiment of the invention, the first side wall material layer is thinned from the transverse direction to form the first side wall layer, so that the distance between the first side wall layers on the side walls of the adjacent gate structures is increased, and in the process of forming the source and drain doped layers by adopting an epitaxial growth method, reaction gas can easily enter the groove, so that the forming quality of the source and drain doped layers is improved, the migration rate of carriers in the groove is improved, and the improvement of the electrical property of the semiconductor structure is facilitated.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the length of the channel of the device is shortened, the distance between the source region and the drain region of the device is also shortened, so that the control capability of the gate structure to the channel is deteriorated, the difficulty of the gate voltage pinch-off (ping off) channel is increased, and the sub-threshold leakage (SCE) phenomenon, namely, the so-called short-channel effect (SCE) is easier to occur.
Therefore, in order to reduce the impact of short channel effects, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same to optimize performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a gate structure positioned on the substrate, and the extending direction perpendicular to the gate structure is transverse; forming a first side wall material layer on the side wall of the grid structure; after the first side wall material layer is formed, etching the substrate on two sides of the grid structure to form a groove; after the groove is formed, thinning the first side wall material layer from the transverse direction to form a first side wall layer; and forming a source-drain doped layer in the groove exposed by the first side wall layer.
Optionally, after forming the trench, before forming the first sidewall layer, the method further includes: forming a seed layer conformally covering the trench; or after the first sidewall layer is formed, the method further includes, before the source-drain doping layer is formed: a seed layer is formed that conformally covers the trench.
Optionally, the first sidewall layer is made of one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride and silicon carbonitride.
Optionally, the thickness of the first sidewall layer is 1 nm to 2 nm.
Optionally, the first sidewall material layer is thinned by a wet etching process to form the first sidewall layer.
Optionally, the first sidewall material layer is etched by using a phosphoric acid solution to form the first sidewall layer.
Optionally, after forming the trench, before forming the first sidewall layer, the method further includes: and cleaning the groove.
Optionally, the gas used in the cleaning process includes He and NH3And Ar.
Optionally, the material of the seed layer includes: and (3) Si.
Optionally, the seed layer is formed by using a selective epitaxial growth process or a molecular beam epitaxy technique.
Optionally, in the step of forming the source-drain doping layer, a first type of ion is doped in the source-drain doping layer; in the step of forming the seed layer, doping second type ions in the seed layer, wherein when the semiconductor structure is an NMOS, the second type ions are P-type ions, and the P-type ions include boron ions, gallium ions or indium ions; alternatively, when the semiconductor structure is a PMOS, the second type of ions are N-type ions, including phosphorous, arsenic, or antimony ions.
Optionally, after the source-drain doped layer is formed, a second sidewall layer is formed on the sidewall of the first sidewall layer.
Optionally, the material of the second sidewall layer is a low-K material.
Optionally, the material of the second sidewall layer includes: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN.
Optionally, after forming the trench, before forming the first sidewall layer, the method further includes: forming a seed layer conformally covering the trench; and in the process of etching the first side wall material layer to form the first side wall layer, the etched rate of the first side wall material layer is greater than that of the seed layer.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the grid structure is positioned on the substrate; the source-drain doping layers are positioned in the substrate on two sides of the grid structure; the first side wall layer is positioned on the side wall of the grid structure; and the second side wall layer is positioned on the side wall of the first side wall layer, and the second side wall layer is positioned on the source drain doping layer.
Optionally, the thickness of the first sidewall layer is 1 nm to 2 nm.
Optionally, the first sidewall layer is made of one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride and silicon carbonitride.
Optionally, the material of the second sidewall layer is a low-K material.
Optionally, the material of the second sidewall layer includes: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the source-drain doped layer is formed by adopting a selective epitaxial growth process. Compared with the situation that the source and drain doping layers are formed in the grooves exposed out of the first side wall material layer, the first side wall material layer is thinned from the transverse direction to form the first side wall layer, so that the distance between the first side wall layers on the side walls of the adjacent gate structures is longer, and in the process of forming the source and drain doping layers by adopting a selective epitaxial growth method, the reaction gas is easier to enter the grooves, so that the forming quality of the source and drain doping layers is good, the stress of the source and drain doping layers on the grooves is favorably improved, the migration rate of carriers in the grooves is higher, and the electrical performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 4 to fig. 11 are schematic structural views corresponding to steps in a first embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 12 and 13 are schematic structural views corresponding to respective steps in a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Fig. 1 to 3 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
As shown in fig. 1, providing a base, where the base includes a substrate 1, a fin 2 on the substrate 1, and a gate structure 3 crossing the fin 2, and the gate structure 3 covers a part of a top wall and a part of a sidewall of the fin 2; forming side wall layers 6 on the side walls of the gate structures 3, wherein the dimension between the side wall layers 6 on the adjacent side walls of the gate structures 3 is taken as D1。
As shown in fig. 2, the fin portions 2 on both sides of the gate structure 3 are etched, and a groove 4 is formed in the fin portion 2.
As shown in fig. 3, a source-drain doped layer 5 is formed in the recess 4 (shown in fig. 2).
As semiconductor manufacturing technology advances, the semiconductor process node is continuously reduced, and thus, the D is perpendicular to the extending direction of the gate structure 31Is smaller and smaller, the source drain doping layer 5 is generally formed by a selective epitaxial growth process because the D1The dimension of the gate structure is too small, so that reaction gas is not easy to enter the groove 4 in the epitaxial growth process, the forming quality of the source-drain doping layer 5 is poor, when the semiconductor structure works, the stress of the source-drain doping layer 5 on a channel below the gate structure 3 is small, the migration rate of carriers in the channel is reduced, and the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a gate structure positioned on the substrate, and the extending direction perpendicular to the gate structure is transverse; forming a first side wall material layer on the side wall of the grid structure; after the first side wall material layer is formed, etching the substrate on two sides of the grid structure to form a groove; after the groove is formed, thinning the first side wall material layer from the transverse direction to form a first side wall layer; and forming a source-drain doped layer in the groove exposed by the first side wall layer.
The source-drain doped layer is formed by adopting a selective epitaxial growth process. Compared with the situation that the source and drain doping layers are formed in the grooves exposed out of the first side wall material layer, the first side wall material layer is thinned from the transverse direction to form the first side wall layer, so that the distance between the first side wall layers on the side walls of the adjacent gate structures is longer, and in the process of forming the source and drain doping layers by adopting a selective epitaxial growth method, the reaction gas is easier to enter the grooves, so that the forming quality of the source and drain doping layers is good, the stress of the source and drain doping layers on the grooves is favorably improved, the migration rate of carriers in the grooves is higher, and the electrical performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 4 to 11 are schematic structural diagrams corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.
Referring to fig. 4, a base is provided, and the base includes a substrate 100 and a gate structure 102 on the substrate 100, and an extending direction perpendicular to the gate structure 102 is a lateral direction.
The substrate provides a process foundation for subsequently forming the semiconductor structure.
In this embodiment, the formed semiconductor structure is a fin field effect transistor (FinFET), and the substrate 100 is the substrate 100 having the fin 101. In other embodiments, the formed semiconductor structure may also be a planar structure, and accordingly, the substrate is a planar substrate.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The surface of the substrate 100 may also be formed with an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the fin 101 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The gate structure 102 is used to occupy a spatial location for a subsequently formed metal gate structure.
In this embodiment, the gate structure 102 is a polysilicon gate structure.
Specifically, the gate structure 102 crosses over the fin 101, and the gate structure 102 covers a portion of the sidewall and the top wall of the fin 101.
In this embodiment, the gate structure 102 is a stacked structure, and includes a gate oxide layer 1021 conformally covering a portion of the top surface and a portion of the sidewall of the fin 101, and a gate layer 1022 located on the gate oxide layer 1021. In other embodiments, the gate structure may also be a single-layer structure, i.e., the gate structure includes only the gate layer.
In this embodiment, the gate oxide layer 1021 is made of silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
In this embodiment, the gate layer 1022 is made of polysilicon. In other embodiments, the material of the gate layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
Referring to fig. 5, a first sidewall material layer 103 is formed on the sidewalls of the gate structure 102.
The first layer of sidewall material 103 provides for the subsequent formation of a first sidewall layer. The first sidewall material layer 103 protects the sidewall of the gate structure 102 in the subsequent trench formation process, and is used to define the formation region of the subsequent source-drain doping layer.
The material of the first sidewall material layer 103 is a dielectric material.
Specifically, the material of the first sidewall material layer 103 is one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride and silicon carbonitride. In this embodiment, the first sidewall material layer 103 is made of silicon nitride.
The step of forming the first sidewall material layer 103 includes: conformally covering the gate structure 102 and the exposed fin 101 of the gate structure 102 with the first sidewall material film (not shown); the first sidewall material film on the gate structure 102 and on the fin 101 is removed, and the remaining first sidewall material film on the sidewall of the gate structure 102 is used as a first sidewall material layer 103.
In this embodiment, the first sidewall material film is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process comprises multiple atomic layer deposition cycles, and is beneficial to improving the thickness uniformity of the first side wall material film; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the first sidewall material film is correspondingly improved. In other embodiments, other deposition processes may be used to form the first sidewall material film, such as: plasma chemical vapor deposition processes, and the like.
It should be noted that the first sidewall material layer 103 should not be too thick or too thin. Subsequently, grooves are formed in the fin portions 101 on the two sides of the gate structure 102 and the first sidewall material layer 103, if the first sidewall material layer 103 is too thick, the distance d1 between the first sidewall material layers 103 on the adjacent sidewalls of the gate structure 102 is too short, which easily causes that the transverse dimension of the grooves formed in the fin portions 101 on the two sides of the gate structure 102 is too small, and after source and drain doped layers are formed in the grooves, the distance between the source and drain doped layers on the two sides of the gate structure 102 is too long, so that the channel formed between the source and drain doped layers is long when the semiconductor structure works, and the improvement of the migration rate of carriers in the channel is not facilitated. If the first sidewall material layer 103 is too thin, the first sidewall material layer 103 is easily removed in the subsequent trench forming process, which easily causes the gate structure 102 to be damaged, and when the semiconductor structure works, the control capability of the gate structure 102 on the trench is easily poor. In this embodiment, the thickness of the first sidewall material layer 103 is 6 nm to 12 nm.
Referring to fig. 6, after the first sidewall material layer 103 is formed, the substrate 100 on both sides of the gate structure 102 is etched to form a trench 104.
The trench 104 provides a process space for the subsequent formation of a source-drain doped layer.
Specifically, trenches 104 are formed in the fin 101 on both sides of the gate structure 102.
In this embodiment, the trench 104 is formed by a dry etching process. The dry etching process is an anisotropic etching process, has good etching profile controllability, is beneficial to enabling the appearance of the groove 104 to meet the process requirement, and reduces the damage to other film layer structures.
The method for forming the semiconductor structure further includes: after the forming the trench 104, before forming the first sidewall layer, the method further includes: the trench 104 is subjected to a cleaning process.
After the fin 101 is dry etched to form the trench 104, polymer impurities remain on the bottom and the side wall of the trench 104. The cleaning treatment is used for removing polymer impurities in the groove 104, so that the purity of the subsequently formed source and drain doping layers is improved, the probability of growth dislocation of the source and drain doping layers can be reduced, and the electrical performance of the semiconductor structure is improved.
The process parameters of the cleaning treatment comprise: the gas includes He and NH3And Ar; the pressure of the chamber is 2Torr to 5Torr, and NH is introduced3The flow rate of (c) may be between 500 and 1000 sccm; the flow rate of the He is between 1000 and 2000 sccm.
It should be further noted that the method for forming the semiconductor structure further includes: after the cleaning process is performed on the groove 104, the baking process is performed on the groove 104.
The baking treatment is used for further removing polymer impurities attached to the side wall and the bottom of the groove 104, so that the purity of the source and drain doping layers formed subsequently is improved, and the probability of growth dislocation of the source and drain doping layers is reduced.
The baking process typically employs hydrogen gas, which undergoes an oxidation reaction with the polymer impurities in the recess 104 to form carbon monoxide or carbon dioxide.
In this embodiment, the baking treatment temperature is 700 to 800 ℃.
Referring to fig. 7, the method for forming the semiconductor structure further includes: after the forming the trench 104, before forming the first sidewall layer, the method further includes: a seed layer 105 is formed that conformally covers the trenches 104.
The seed layer 105 is used for improving the surface smoothness and smoothness of the trench 104, so as to provide a good interface state, provide a process foundation for the subsequent formation of a source-drain doping layer, and enable the source-drain doping layer to have good formation quality.
In this embodiment, the material of the seed layer 105 includes: and (3) Si. The material of the seed layer 105 is the same as that of the fin portion 101, so that defects in the seed layer 105 are reduced, and the formation quality of the seed layer 105 is improved.
In this embodiment, the seed layer 105 is formed by a Selective Epitaxial Growth (SEG) process. The film obtained by the selective epitaxial growth process has high purity and few defects, and is beneficial to improving the formation quality of the seed layer 105, thereby being beneficial to optimizing the electrical property of the semiconductor structure. In other embodiments, the seed layer may be formed by a molecular beam epitaxy technique.
The process parameters for forming the seed layer 105 include: the reaction gas comprises SiH2Cl2Or SiH4。
It should be noted that the seed layer 105 is not too thick nor too thin. If the seed layer 105 is too thick, the distance between a subsequently formed source-drain doped layer and a channel region below the gate structure 102 is too far, and when the semiconductor structure works, the stress of the source-drain doped layer on the channel is small, so that the migration rate of carriers in the channel is small. If the seed layer 105 is too thin, poor surface flatness and smoothness of the trench 104 are easily caused, and a region which is not covered by the seed layer 105 exists on the surface of the trench 104, so that poor quality of a subsequently formed source-drain doping layer is caused. In this embodiment, the thickness of the seed layer 105 is 2 nm to 4 nm.
In addition, it should be noted that in the subsequent step of forming the source-drain doped layer, the source-drain doped layer is doped with first type ions. When the semiconductor structure works, the first type ions are used for improving the stress of the source-drain doped layer on a channel and improving the migration rate of carriers in the channel.
In this embodiment, in the step of forming the seed layer 105, the seed layer 105 is doped with a second type of ions, and when the semiconductor structure is an NMOS, the second type of ions are P-type ions.
When the semiconductor structure works, the depletion layer of the source electrode and the depletion layer of the drain electrode of the source-drain doped layer are not easy to expand due to the P-type ions, and the probability of punch-through of the source electrode and the drain electrode is reduced.
Specifically, the P-type ions include boron ions, gallium ions, or indium ions.
In other embodiments, when the transistor is a PMOS, the second type ions are N-type ions. Specifically, the N-type ions include phosphorus ions, arsenic ions, or antimony ions.
Referring to fig. 8, after the trenches 104 are formed, the first sidewall material layer 103 is thinned in the transverse direction to form a first sidewall layer 106.
Compared with the case that the source and drain doping layers are formed in the groove 104 exposed by the first sidewall material layer 103, in the embodiment of the invention, the first sidewall material layer 103 is thinned from the transverse direction to form the first sidewall layer 106, so that the distance d2 between the first sidewall layers 106 on the sidewalls of the adjacent gate structures 102 is longer, and in the process of forming the source and drain doping layers in the groove 104 by adopting a selective epitaxial growth method, the reaction gas is easier to enter the groove 104, so that the forming quality of the source and drain doping layers is good, the stress of the source and drain doping layers on the groove is favorably improved, the migration rate of carriers in the groove is higher, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the first sidewall material layer 103 is thinned by a wet etching process to form the first sidewall layer 106. The wet etching process is isotropic etching, is simple to operate and low in process cost, has a high etching rate, and is beneficial to controlling the removal thickness of the first side wall material layer 103 and avoiding damage to the gate structure 102.
It should be further noted that the etching rate of the wet etching solution to the first sidewall material layer 103 is greater than the etching rate to the seed layer 105.
Specifically, the first sidewall material layer 103 is etched with a phosphoric acid solution to form the first sidewall layer 106.
It should be noted that the first sidewall layer 106 is not too thick or too thin. If the first sidewall layer 106 is too thick, the distance d2 between the first sidewall layers 106 adjacent to the sidewall of the gate structure 102 is too small, and in the subsequent process of forming a source-drain doped layer by using a selective epitaxial growth method, the reaction gas is not easy to enter the trench 104, so that the formation quality of the source-drain doped layer is poor, and the improvement of the electrical performance of the semiconductor structure is not facilitated. If the first sidewall layer 106 is too thin, a portion of the sidewall of the gate structure 102 is easily exposed by the first sidewall layer 106; in the process of forming the source-drain doping layer by subsequent selective epitaxial growth, an excess source-drain doping layer is easy to grow on the side wall of the gate structure 102, and the excess source-drain doping layer can cause a high capacitive coupling effect between the gate structure 102 and a subsequently formed contact hole plug, thereby causing poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the first sidewall layer 106 is 1 nm to 2 nm.
It should be noted that, in the process of etching the first sidewall material layer 103 to form the first sidewall layer 106, the etched rate of the seed layer 105 is relatively low, and accordingly, the surface of the seed layer 105 is relatively flat and smooth, which is beneficial to improving the formation quality of the source-drain doping layer subsequently formed in the trench 104.
Referring to fig. 9, a source-drain doping layer 107 is formed in the trench 104 exposed by the first sidewall layer 116.
When the semiconductor structure works, the source-drain doping layer 107 provides stress for the channel, and the migration rate of carriers in the channel is improved.
In this embodiment, the source-drain doping layer 107 is formed by a selective epitaxial growth method, and the source-drain doping layer 107 is doped with first type ions in the process of forming the source-drain doping layer 107. The doped ions can achieve the purpose of improving the carrier mobility in the channel.
In this embodiment, the semiconductor structure is used to form a pmos (positive Channel Metal Oxide semiconductor) transistor, that is, the source-drain doping layer 107 is made of silicon germanium doped with P-type ions. In this embodiment, P-type ions are doped in silicon germanium, so that the P-type ions replace positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the P-type ions include B, Ga or In.
In other embodiments, the semiconductor structure is used for forming an nmos (negative channel metallic oxide semiconductor) transistor, and the material of the source and drain doping layer is silicon carbide or silicon phosphide doped with N-type ions. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions are used for replacing the positions of silicon atoms in crystal lattices, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the N-type ions include P, As or Sb.
Referring to fig. 10, the method for forming the semiconductor structure further includes: after the source-drain doping layer 107 is formed, a second sidewall layer 108 is formed on the sidewall of the first sidewall layer 106.
Subsequently forming an interlayer dielectric layer which covers the side wall of the gate structure 102 and exposes the top wall of the gate structure 102; in order to improve the electrical performance of the semiconductor structure, the gate structure 102 is subsequently removed, and a gate opening surrounded by the interlayer dielectric layer and the fin portion 101 is formed; and forming a metal gate structure in the gate opening. The first side wall layer 106 is too thin, the first side wall layer 106 is easy to etch in the process of forming the gate opening, and the second side wall layer 108 is used for protecting the interlayer dielectric layer from being damaged easily in the process of forming the gate opening, so that the space position of a metal gate structure formed subsequently is controlled, the metal gate structure is not easy to contact with the source-drain doping layer 107, and the probability of leakage current of the semiconductor structure is reduced.
In this embodiment, the material of the second sidewall layer 108 is a low-K material. And forming a contact hole plug connected with the source-drain doping layer 107, wherein the second side wall layer 108 is used for reducing the capacitive coupling effect of the contact hole plug and the gate structure 102.
Specifically, the material of the second side wall layer includes: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN.
Referring to fig. 11, the method for forming the semiconductor structure further includes: after the second side wall layer 108 is formed, an anti-etching layer 109 which conformally covers the side wall of the gate structure 102 and the source-drain doping layer 107 is formed; after the anti-etching layer 109 is formed, an interlayer dielectric layer 110 covering the sidewalls of the gate structure 102 and exposing the top wall of the gate structure 102 is formed.
In the subsequent process of forming an opening for filling the contact hole plug in the interlayer dielectric layer 110, the etching rate of the anti-etching layer 109 is less than that of the interlayer dielectric layer 110, the anti-etching layer 109 is used for defining a temporary etching stop position, and then the anti-etching layer 109 is further etched until the source-drain doping layer 107 is exposed, so that the etching rates of the openings on the source-drain doping layers 107 are easy to be consistent, the problems of excessive etching or insufficient etching and the like are not easy to cause, and the electrical performance and reliability of the semiconductor structure are further improved.
The material of the anti-etching layer 109 may be one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron silicon, and boron nitride silicon carbide. In this embodiment, the material of the anti-etching layer 109 is silicon nitride.
The interlevel dielectric layer 110 is used to electrically isolate adjacent devices.
The interlayer dielectric layer 110 is made of a dielectric material.
Specifically, in this embodiment, the interlayer dielectric layer 110 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
It should be noted that, in the subsequent process, the gate structure 102 is replaced by a metal gate structure, and the specific process is not described herein again.
Fig. 12 and 13 are schematic structural views corresponding to respective steps in a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.
The same points of the embodiment of the present invention as the first embodiment are not described herein again, but the difference between the present invention and the first embodiment is that after the first sidewall layer 206 is formed and before the source-drain doping layer is formed, a seed layer 205 that conformally covers the trench 204 is formed.
The source-drain doped layer is formed by adopting a selective epitaxial growth process. Compared with the case that the source and drain doping layers are formed in the trench 204 exposed from the first sidewall material layer (not shown in the figure), in the embodiment of the invention, the first sidewall material layer is thinned from the transverse direction to form the first sidewall layer 206, so that the distance between the first sidewall layers 206 on the sidewalls of the adjacent gate structures 202 is longer, and in the process of forming the source and drain doping layers by adopting a selective epitaxial growth method, the reaction gas is easier to enter the trench 204, so that the forming quality of the source and drain doping layers is good, the stress of the source and drain doping layers on the trench is favorably improved, the migration rate of carriers in the trench is higher, and the electrical performance of the semiconductor structure is improved.
Compared with the case that the seed layer 205 is formed firstly and then the first sidewall material layer is thinned to form the first sidewall layer 206, the seed layer 205 which conformally covers the groove 204 is formed after the first sidewall layer 206 is formed, so that the damage of the seed layer 205 caused by thinning the first sidewall material layer is avoided, the surface of the seed layer 205 is smooth and flat, and the formation quality of the source-drain doped layer is improved.
In the embodiment of the present invention, the forming method of the seed layer 205 is the same as that of the first embodiment, and is not described herein again.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 11, a schematic diagram of a first embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a gate structure 102 on the substrate 100; the source-drain doping layer 107 is positioned in the substrate 100 on two sides of the gate structure 102; a first sidewall layer 106 on sidewalls of the gate structure 102; and a second sidewall layer 108 located on the sidewall of the first sidewall layer 106, wherein the second sidewall layer 108 is located on the source-drain doping layer 107.
In the process of forming the semiconductor structure, after the substrate 100 and the gate structure 102 are formed, a first sidewall material layer 103 is formed on the sidewall of the gate structure 102 (as shown in fig. 7); the first side wall material layer 103 is thinned from the transverse direction by taking the extending direction perpendicular to the gate structure 102 as the transverse direction, so that the first side wall layer 106 is formed, the distance between the first side wall layers 106 on the side walls of the adjacent gate structures 102 is longer, and in the process of forming the source and drain doping layers 107 by adopting an epitaxial growth method, the reaction gas is easier to enter the groove 104, so that the forming quality of the source and drain doping layers 107 is improved, the migration rate of carriers in the groove is improved, and the improvement of the electrical performance of the semiconductor structure is facilitated.
In this embodiment, the formed semiconductor structure is a fin field effect transistor (FinFET), and the substrate 100 is the substrate 100 having the fin 101. In other embodiments, the formed semiconductor structure may also be a planar structure, and accordingly, the substrate is a planar substrate.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The surface of the substrate 100 may also be formed with an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the fin 101 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The gate structure 102 is used to occupy a spatial location for a subsequently formed metal gate structure.
In this embodiment, the gate structure 102 is a polysilicon gate structure.
In this embodiment, the gate structure 102 is a stacked structure, and includes a gate oxide layer 1021 conformally covering a portion of the top surface and a portion of the sidewall of the fin 101, and a gate layer 1022 located on the gate oxide layer 1021. In other embodiments, the gate structure may also be a single-layer structure, i.e., the gate structure includes only the gate layer.
In this embodiment, the gate oxide layer 1021 is made of silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
In this embodiment, the gate layer 1022 is made of polysilicon. In other embodiments, the material of the gate layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
When the semiconductor structure works, the source-drain doping layer 107 provides stress for the channel, and the migration rate of carriers in the channel is improved.
In this embodiment, the semiconductor structure is used to form a pmos (positive Channel Metal Oxide semiconductor) transistor, that is, the source/drain doping layer 107 is made of silicon germanium doped with first type ions. In this embodiment, P-type ions are doped in silicon germanium, so that the P-type ions replace positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the P-type ions include B, Ga or In.
In other embodiments, the semiconductor structure is used to form an nmos (negative channel Metal Oxide semiconductor) transistor, and the material of the source and drain doping layer is silicon carbide or silicon phosphide doped with first type ions. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions are used for replacing the positions of silicon atoms in crystal lattices, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the N-type ions include P, As or Sb.
In the formation process of the semiconductor structure, a first sidewall material layer 103 is formed on the sidewall of the gate structure 102 (as shown in fig. 5), and the first sidewall layer 106 is formed by thinning the first sidewall material layer 103. Compared with the distance d1 between the first sidewall material layers 103 on the sidewalls of the adjacent gate structures 102, the distance d2 between the first sidewall layers 106 on the sidewalls of the adjacent gate structures 102 is larger, so that more reaction gas can enter the trench 104 (as shown in fig. 6) during the process of forming the source-drain doped layer 107 by the selective epitaxial growth method, and the formation quality of the source-drain doped layer 107 is better.
The material of the first sidewall layer 106 is a dielectric material.
Specifically, the material of the first sidewall layer 106 is one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride and silicon carbonitride. In this embodiment, the first sidewall layer 106 is made of silicon nitride.
It should be noted that the first sidewall layer 106 is not too thick or too thin. If the first sidewall layer 106 is too thick, the distance d2 between the first sidewall layers 106 adjacent to the sidewall of the gate structure 102 is too small, and in the process of forming the source/drain doping layer 107 by using an epitaxial growth method, the reaction gas is not easy to enter the trench 104, which is not favorable for improving the migration rate of carriers in the trench, and thus the formation quality of the source/drain doping layer 107 is poor. If the first sidewall layer 106 is too thin, the gate structure 102 is easily exposed, the gate structure 102 is made of polysilicon, and in the process of forming the source-drain doping layer 107 through selective epitaxial growth, redundant source-drain doping layers are easily grown on the sidewall of the gate structure 102, and the redundant source-drain doping layers can cause the capacitive coupling effect between the gate structure 102 and a subsequently formed contact hole plug to be improved, so that the electrical property of the semiconductor structure is poor. In this embodiment, the thickness of the first sidewall layer 106 is 1 nm to 2 nm.
The semiconductor structure further includes: and the interlayer dielectric layer 110 covers the side wall of the gate structure 102, and the interlayer dielectric layer 110 exposes the top of the gate structure 102.
The interlevel dielectric layer 110 is used to electrically isolate adjacent devices.
The interlayer dielectric layer 110 is made of a dielectric material.
Specifically, in this embodiment, the interlayer dielectric layer 110 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In order to improve the electrical performance of the semiconductor structure, the gate structure 102 is subsequently removed, and a gate opening (not shown) surrounded by the interlayer dielectric layer 110 and the fin 101 is formed; and forming a metal gate structure in the gate opening. The second sidewall layer 108 is used for preventing the dielectric layer 110 between the protective layers from being damaged in the process of forming the gate opening, and is beneficial to controlling the spatial position of the metal gate structure, so that the metal gate structure is not easy to contact with the source-drain doped layer 107, and the probability of leakage current of the semiconductor structure is reduced.
In this embodiment, the material of the second sidewall layer 108 is a low-K material. And forming a contact hole plug connected with the source-drain doping layer 107, wherein the second side wall layer 108 is used for reducing the capacitive coupling effect of the contact hole plug and the gate structure 102.
Specifically, the material of the second sidewall layer 108 includes: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN.
The semiconductor structure further includes: and the anti-etching layer 109 is positioned between the interlayer dielectric layer 110 and the second side wall layer 108, and between the source-drain doping layer 107 and the interlayer dielectric layer 110.
In the subsequent process of forming an opening for filling the contact hole plug in the interlayer dielectric layer 110, the etching rate of the anti-etching layer 109 is less than that of the interlayer dielectric layer 110, the anti-etching layer 109 is used for defining a temporary etching stop position, and then the anti-etching layer 109 is further etched until the source-drain doping layer 107 is exposed, so that the etching rates of the openings on the source-drain doping layers 107 are easy to be consistent, the problems of excessive etching or insufficient etching and the like are not easy to cause, and the electrical performance and reliability of the semiconductor structure are further improved.
The material of the anti-etching layer 109 may be one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron silicon, and boron nitride silicon carbide. In this embodiment, the material of the anti-etching layer 109 is silicon nitride.
The semiconductor structure further includes: and the seed layer 105 is positioned between the source drain doping layer 107 and the fin 101.
The surface flatness and smoothness of the surface of the seed layer 105 are high, and a good interface state can be provided, so that the source-drain doping layer 107 has good formation quality.
In this embodiment, the material of the seed layer 105 includes: and (3) Si. The material of the seed layer 105 is the same as the material of the substrate 100 and the material of the fin portion 101, so that defects in the seed layer 105 are reduced, and the formation quality of the seed layer 105 is improved.
It should be noted that the seed layer 105 is doped with a second type of ions, and when the semiconductor structure is an NMOS, the second type of ions are P-type ions.
When the semiconductor structure works, the depletion layer of the source electrode and the depletion layer of the drain electrode of the source-drain doping layer 107 are not easy to expand due to the P-type ions, and the probability of punch-through of the source electrode and the drain electrode is reduced.
Specifically, the P-type ions include boron ions, gallium ions, or indium ions.
In other embodiments, when the first type transistor is a PMOS, the second type ions are N-type ions. Specifically, the N-type ions include phosphorus ions, arsenic ions, or antimony ions.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a gate structure positioned on the substrate, and the extending direction perpendicular to the gate structure is transverse;
forming a first side wall material layer on the side wall of the grid structure;
after the first side wall material layer is formed, etching the substrate on two sides of the grid structure to form a groove;
after the groove is formed, thinning the first side wall material layer from the transverse direction to form a first side wall layer;
and forming a source-drain doped layer in the groove exposed by the first side wall layer.
2. The method of forming a semiconductor structure of claim 1, wherein after forming the trench, before forming the first sidewall layer further comprises: forming a seed layer conformally covering the trench; or after the first sidewall layer is formed, the method further includes, before the source-drain doping layer is formed: a seed layer is formed that conformally covers the trench.
3. The method of claim 1 or 2, wherein the material of the first sidewall layer is one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, and silicon carbonitride.
4. The method of claim 1 or 2, wherein the first sidewall layer has a thickness of 1 nm to 2 nm.
5. The method for forming a semiconductor structure according to claim 1 or 2, wherein the first sidewall layer is formed by thinning the first sidewall material layer by a wet etching process.
6. The method of forming a semiconductor structure of claim 5, wherein the first sidewall layer is formed by etching the first sidewall material layer with a phosphoric acid solution.
7. The method of forming a semiconductor structure of claim 1 or 2, further comprising, after forming the trench and before forming the first sidewall layer: and cleaning the groove.
8. The method of claim 7, wherein the gas used in the cleaning process comprises He, NH3And Ar.
9. The method of forming a semiconductor structure of claim 2, wherein the material of the seed layer comprises: and (3) Si.
10. The method of claim 2, wherein the seed layer is formed using a selective epitaxial growth process or a molecular beam epitaxy technique.
11. The method for forming the semiconductor structure according to claim 2, wherein in the step of forming the source-drain doping layer, first type ions are doped in the source-drain doping layer;
in the step of forming the seed layer, doping second type ions in the seed layer, wherein when the semiconductor structure is an NMOS, the second type ions are P-type ions, and the P-type ions include boron ions, gallium ions or indium ions;
alternatively, the first and second electrodes may be,
when the semiconductor structure is a PMOS, the second type of ions are N-type ions, including phosphorous, arsenic, or antimony ions.
12. The method for forming the semiconductor structure according to claim 1 or 2, wherein after the source-drain doping layer is formed, a second sidewall layer is formed on a sidewall of the first sidewall layer.
13. The method of claim 12, wherein the second sidewall layer is formed of a low-K material.
14. The method of forming a semiconductor structure of claim 13, wherein the material of the second sidewall layer comprises: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN.
15. The method of forming a semiconductor structure of claim 1, wherein after forming the trench, before forming the first sidewall layer further comprises: forming a seed layer conformally covering the trench; and in the process of etching the first side wall material layer to form the first side wall layer, the etched rate of the first side wall material layer is greater than that of the seed layer.
16. A semiconductor structure, comprising:
a substrate;
the grid structure is positioned on the substrate;
the source-drain doping layers are positioned in the substrate on two sides of the grid structure;
the first side wall layer is positioned on the side wall of the grid structure;
and the second side wall layer is positioned on the side wall of the first side wall layer, and the second side wall layer is positioned on the source drain doping layer.
17. The semiconductor structure of claim 16, wherein the first sidewall layer has a thickness of 1 nm to 2 nm.
18. The semiconductor structure of claim 16, wherein the material of the first sidewall layer is one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, and silicon carbonitride.
19. The semiconductor structure of claim 16, wherein the material of the second sidewall layer is a low-K material.
20. The semiconductor structure of claim 16, wherein the material of the second sidewall layer comprises: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN.
CN201910579466.4A 2019-06-28 2019-06-28 Semiconductor structure and forming method thereof Pending CN112151449A (en)

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