CN113130311A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN113130311A
CN113130311A CN201911393147.0A CN201911393147A CN113130311A CN 113130311 A CN113130311 A CN 113130311A CN 201911393147 A CN201911393147 A CN 201911393147A CN 113130311 A CN113130311 A CN 113130311A
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layer
channel
gate
forming
sacrificial
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CN113130311B (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, removing a side wall with partial thickness of a first sacrificial layer on the substrate, enabling the bottom dimension of a first target sacrificial layer formed along the width direction of the channel layer to be smaller than the dimension of the channel layer, taking a channel lamination including the first target sacrificial layer as a target channel lamination, forming a pseudo gate layer crossing the target channel lamination and pseudo gate side walls positioned at two sides of the pseudo gate layer, removing the pseudo gate layer and the first target sacrificial layer at the overlapping part of the pseudo gate layer, and forming a gate opening and a first channel communicated with the gate opening, thereby forming a gate structure in the gate opening and the channel. The method reduces the size of the gate structure formed at the position of the first target sacrificial layer at the overlapping part of the dummy gate layer, so that the size of the parasitic MOS at the position is reduced, the influence of the parasitic MOS at the position is further reduced, and the performance of the device is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the fully-surrounded metal gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the fully-surrounded metal gate transistor has stronger control capability on the channel by the gate, and can better inhibit a short-channel effect.
The full-gate nanowire can be obtained by adding only two process modules in the existing replacement gate fin field effect transistor (FinTET) process flow, wherein the two process modules are as follows: one is to grow a layer of Silicon on bulk Silicon (bulk Silicon) or SOI wafer, which avoids leakage of bulk Silicon material. Second, selectively remove the silicon germanium on the replaceable metal gate loop, and then use HKMG (high-k insulating layer + metal gate) to stack the surrounding silicon channel to form the all-around metal gate transistor.
However, the performance of the devices formed by the current process is not good.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which improve the performance of a device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including:
providing a substrate, wherein a channel lamination layer is formed on the substrate and comprises a sacrificial layer and a channel layer which are alternately stacked, wherein the sacrificial layer at the bottom of the channel lamination layer, which is connected with the substrate, is a first sacrificial layer;
removing the side wall of the first sacrificial layer with partial thickness to form a first target sacrificial layer, wherein the bottom size of the first target sacrificial layer is smaller than the size of the channel layer in the width direction of the channel layer, and the channel lamination including the first target sacrificial layer is a target channel lamination;
forming a pseudo gate layer crossing the target channel lamination and pseudo gate side walls positioned on two sides of the pseudo gate layer;
removing the pseudo gate layer and the first target sacrificial layer at the part overlapped with the pseudo gate layer, forming a gate opening between the pseudo gate side walls at the position of the pseudo gate structure, and forming a first channel communicated with the gate opening at the position of the part overlapped with the pseudo gate layer of the first target sacrificial layer;
and forming a gate structure in the gate opening and the first channel, wherein the gate structure formed in the gate opening is used as the first gate structure, and the gate structure formed in the first channel is used as the second gate structure.
Optionally, in the step of removing the sidewall of the partial thickness of the first sacrificial layer, the removal thickness of the first sacrificial layer is 10% to 40% of a dimension of the channel layer in the width direction.
Optionally, the channel stack includes a plurality of alternately stacked sacrificial layers and channel layers, wherein the sacrificial layers other than the first sacrificial layer are second sacrificial layers;
and removing the side wall of the first sacrificial layer with partial thickness by adopting an etching process, wherein the etching rate of the etching process corresponding to the first sacrificial layer is greater than that of the etching process corresponding to the second sacrificial layer.
Optionally, the base includes a substrate and a fin portion protruding from the substrate, and the step of forming the channel stack on the base includes:
providing an initial substrate;
forming stacked material layers on the initial substrate, wherein the stacked material layers comprise sacrificial material layers and channel material layers which are alternately stacked, the sacrificial material layer which is positioned at the bottom of the stacked material layers and connected with the initial substrate is a first sacrificial material layer, the other sacrificial material layers except the first sacrificial material layer in the stacked material layers are second sacrificial material layers, and the first sacrificial material layer is different from the second sacrificial material layers;
removing the stacked material layers in the partial region and the initial base with partial thickness in the partial region, taking the initial base with residual thickness as the substrate, taking the initial base protruding out of the substrate as the fin portion, and taking the residual stacked material layers on the fin portion as the channel lamination.
Optionally, forming a stacked material layer on the initial substrate by using an epitaxial growth process; wherein, in the stage of forming the sacrificial material layer and the stage of forming the channel material layer, the introduced epitaxial gases are different; in the stage of forming the first sacrificial material layer and the stage of forming the second sacrificial material layer, the introduced epitaxial gases are the same, and the flow rates of the introduced epitaxial gases are different.
Optionally, the step of forming a stacked material layer on the substrate by using an epitaxial growth process includes:
forming a first sacrificial material layer, wherein the epitaxial gas introduced in the stage of forming the first sacrificial material layer is germane and silane;
forming a channel material layer, wherein the epitaxial gas introduced in the channel material layer forming stage is silane;
and forming a second sacrificial material layer, wherein the epitaxial gas introduced in the second sacrificial material layer forming stage is germane and silane, and the flow rate of introducing germane in the second sacrificial material layer forming stage is less than that of introducing germane in the first sacrificial material layer forming stage.
Optionally, in the stage of forming the first sacrificial material layer, the flow rate of germane gradually decreases, and the minimum value of the flow rate of germane introduced in the stage of forming the first sacrificial material layer is greater than the maximum value of the flow rate of germane introduced in the stage of forming the second sacrificial material layer.
Optionally, an etching process is used to remove the sidewall of the first sacrificial layer with a partial thickness, wherein the higher the germanium content in the etched material is, the higher the etching rate corresponding to the etching process is.
Optionally, the sidewalls of the first sacrificial layer with a partial thickness are removed by using HCl solution or HCl vapor etching.
Optionally, after the step of removing the sidewall with the partial thickness of the first sacrificial layer, before the step of forming the dummy gate layer crossing the target channel stack and the dummy gate sidewalls located at two sides of the dummy gate layer, the method further includes:
forming an isolation layer, wherein the isolation layer covers the substrate exposed out of the first target sacrificial layer;
the step of forming the dummy gate layer crossing the target channel stack and the dummy gate side walls located at two sides of the dummy gate layer specifically comprises: and forming a pseudo gate layer crossing the target channel lamination layer and pseudo gate side walls positioned at two sides of the pseudo gate layer on the isolation layer.
Optionally, the method further includes, after the step of forming the dummy gate layer crossing the target channel stack and the dummy gate sidewalls on the two sides of the dummy gate layer, and before the step of removing the dummy gate layer and the first target sacrificial layer overlapping with the dummy gate layer, using the dummy gate layer and the dummy gate sidewalls on the two sides of the dummy gate layer as a dummy gate structure:
removing the target channel lamination layers on two sides of the pseudo gate structure to form a first groove, wherein the residual target channel lamination layers overlapped with the pseudo gate layer are effective channel lamination layers;
forming a source-drain doped layer in the first groove, wherein the source-drain doped layer is in contact with the channel layer in the effective channel laminated layer;
and forming an interlayer dielectric layer on the substrate exposed out of the pseudo gate structure, wherein the interlayer dielectric layer covers the source-drain doping layer and exposes out of the top of the pseudo gate structure.
Optionally, after the step of removing the target channel stacking layers on the two sides of the dummy gate structure and before the step of forming the source-drain doping layers on the two sides of the effective channel stacking layer, the method further includes:
removing the side wall of the sacrificial layer in the effective channel lamination layer with partial thickness to form a second groove surrounded by the channel layer and the residual sacrificial layer or the channel layer, the residual sacrificial layer and the fin part;
forming an inner side wall in the second groove;
wherein the formation process of the second groove is the same as the formation process of the first target sacrificial layer.
Optionally, in the step of removing the dummy gate layer and the first target sacrificial layer overlapping with the dummy gate layer, a second sacrificial layer in the effective channel stack is also removed, and a second channel communicating with the gate opening is formed at a position of the second sacrificial layer;
in the step of forming the gate structure in the gate opening and the first channel, a gate structure is further formed in the second channel, and the gate structure formed in the second channel is taken as a third gate structure.
Optionally, the first gate structure includes a first gate electrode and a first gate dielectric layer located at the bottom and the sidewall of the first gate electrode; the second gate structure comprises a second gate electrode and a second gate medium layer positioned at the bottom and the side wall of the second gate electrode and between the second gate electrode and the channel layer; the third gate structure includes a third gate electrode and a third gate dielectric layer between the third gate electrode and the channel layer.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including:
the device comprises a substrate, a grid structure positioned on the substrate and pseudo grid side walls positioned on two sides of the grid structure;
a channel layer traversing the gate structure, a width direction of the channel layer being an extension direction of the gate structure;
the gate structure crossing the channel layer is taken as a first gate structure, the gate structure is positioned at the bottom of the overlapped part of the first gate structure and the channel layer, and the gate structure connected with the substrate is taken as a second gate structure; a bottom dimension of the second gate structure is smaller than a dimension of the channel layer in a width direction of the channel layer.
Optionally, in the width direction of the channel layer, a size ratio of a bottom size of the second gate structure to a size of the channel layer is 0.6 to 0.9.
Optionally, the number of the channel layers is multiple, the channel layers are suspended on the substrate at intervals, the gate structure further includes a third gate structure, the third gate structure is located between the channel layers overlapping with the first gate structure and connected to the first gate structure, and the size of the third gate structure is larger than the size of the bottom of the second gate structure.
Optionally, the semiconductor structure further includes an isolation layer located between the first gate structure and the substrate.
Optionally, the substrate includes a substrate and a fin portion protruding from the substrate, the channel layer is located on the fin portion, and the gate structure spans the fin portion and the channel layer on the fin portion.
Optionally, the semiconductor structure further includes:
the source-drain doping layer is positioned on the fin parts on two sides of the grid structure and is in contact with the channel layer;
and the interlayer dielectric layers are positioned on two sides of the grid structure and cover the source drain doping layer, and the top of each interlayer dielectric layer is flush with the top of the grid structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, the bottom dimension of a first target sacrificial layer formed along the width direction of the channel layer is smaller than the dimension of the channel layer by removing the side wall with partial thickness of the first sacrificial layer with the bottom connected with the substrate, a channel lamination including the first target sacrificial layer is used as a target channel lamination to form a pseudo gate layer crossing the target channel lamination and pseudo gate side walls positioned at two sides of the pseudo gate layer, a gate opening positioned between the pseudo gate side walls is formed by removing the pseudo gate layer and the first target sacrificial layer at the overlapping part of the pseudo gate layer, and a first channel communicated with the gate opening is formed at the overlapping part of the first target sacrificial layer and the pseudo gate layer, so that a gate structure is formed in the gate opening and the first channel. It can be seen that, by making the bottom dimension of the first target sacrificial layer in the width direction of the channel layer smaller than the dimension of the channel layer, the dimension of the second gate structure formed at the position of the overlapping portion of the first target sacrificial layer and the dummy gate layer is reduced, so that the dimension of the parasitic MOS located there is also reduced, the influence of the parasitic MOS at this position is further reduced, and the performance of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 16 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is not good, and the reason for the poor performance of the devices is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown. As shown in fig. 1, the base includes a substrate 1 and a fin portion 2 protruding from the substrate 1; the source drain doping layer 3 is separated on the fin part 2; the channel lamination layer 4 is suspended between the source-drain doping layers 3 and is in contact with the source-drain doping layers 3, the channel lamination layer 4 comprises a sacrificial layer 41 and a channel layer 42 positioned on the sacrificial layer 41, wherein the transport direction of carriers in the channel layer 42 is taken as the length direction of the channel layer, and the transport direction perpendicular to the carriers is taken as the width direction of the channel layer 42; a metal gate structure 5 spanning the channel stack 4 on the fin 2 and surrounding the channel stack 4; and the interlayer dielectric layer 6 covers the source-drain doping layer 3 and the side wall of the metal gate structure 5.
In the channel stack 4, a bottom parasitic MOS is formed in a region surrounded by the channel layer 42 close to the fin 2, and the source-drain doping layer 3, and the bottom parasitic MOS is likely to form a channel at a low voltage, thereby causing a leakage problem.
In the embodiment of the invention, the bottom dimension of a first target sacrificial layer formed along the width direction of the channel layer is smaller than the dimension of the channel layer by removing the side wall with partial thickness of the first sacrificial layer with the bottom connected with the substrate, a channel lamination including the first target sacrificial layer is used as a target channel lamination to form a pseudo gate layer crossing the target channel lamination and pseudo gate side walls positioned at two sides of the pseudo gate layer, a gate opening positioned between the pseudo gate side walls is formed by removing the pseudo gate layer and the first target sacrificial layer at the overlapping part of the pseudo gate layer, and a first channel communicated with the gate opening is formed at the overlapping part of the first target sacrificial layer and the pseudo gate layer, so that a gate structure is formed in the gate opening and the first channel.
It can be seen that, by making the bottom dimension of the first target sacrificial layer in the width direction of the channel layer smaller than the dimension of the channel layer, the dimension of the second gate structure formed at the position of the overlapping portion of the first target sacrificial layer and the dummy gate layer is reduced, so that the dimension of the parasitic MOS located there is also reduced, the influence of the parasitic MOS at this position is further reduced, and the performance of the device is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 2 to fig. 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
With combined reference to fig. 2 to 5, providing a substrate, as shown in fig. 5, forming a channel stack 21 on the substrate 10, where the channel stack 21 includes sacrificial layers and channel layers 221 stacked alternately, and a sacrificial layer at the bottom of the channel stack 21 and contacting the substrate 10 is a first sacrificial layer 211A;
the substrate 10 is used for providing a process platform for the subsequent formation of a gate structure, the channel stack 21 on the substrate 10 is used for providing a process base for the subsequent formation of a target channel stack, and the first sacrificial layer 211A at the bottom of the channel stack 21 is used for forming a first target sacrificial layer with a smaller size by removing a partial thickness of a sidewall in a subsequent step.
In the embodiment of the present invention, the channel stack 21 includes a plurality of sacrificial layers 211 and channel layers 221 stacked alternately, and the channel stack 21 may include 2 sacrificial layers and 2 channel layers stacked alternately, or the channel stack 21 may include 3 sacrificial layers and 3 channel layers stacked alternately, which is described in this embodiment by taking as an example that the channel stack 21 includes 3 sacrificial layers and 3 channel layers stacked alternately, and the other sacrificial layers except for the first sacrificial layer 211A are the second sacrificial layers 211B.
In this embodiment, the substrate 10 may include a substrate 101 and a fin 102 protruding from the substrate, and accordingly, the process of forming the channel stack 21 on the substrate 10 may include:
referring to fig. 2, an initial substrate 100 is provided;
with reference to fig. 2 to 5, the initial base 100 is used to provide a process platform for forming a stack of material layers, and further, the initial base 100 is removed by removing a portion of the thickness in a portion of the initial base to form a substrate 101 and a fin 102 protruding from the substrate.
In this embodiment, the initial substrate 100 is made of silicon. In other embodiments, the initial substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the initial substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.
In addition, in other embodiments, the initial base may further include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, where the first semiconductor layer is used to provide a process foundation for a subsequent substrate formation, and the second semiconductor layer is used to provide a process foundation for a subsequent fin formation.
Next, referring to fig. 3, a stacked material layer 20 is formed on the initial substrate 100;
the stacked material layers 20 include sacrificial material layers 210 and channel material layers 220 stacked alternately, wherein the sacrificial material layer at the bottom of the stacked material layers 20 and connected to the initial substrate 100 is a first sacrificial material layer 210A, the sacrificial material layers other than the first sacrificial material layer 210A in the stacked material layers are second sacrificial material layers 210B, and the first sacrificial material layer 210A is different from the second sacrificial material layer 210B.
The stacked material layer 20 is used for forming a channel stack by subsequently removing the stacked material layer in a partial region, the first sacrificial material layer 210A provides a process basis for subsequently forming a first sacrificial layer, the second sacrificial material layer 210B provides a process basis for subsequently forming a second sacrificial layer, and the channel material layer 220 is used for providing a process basis for subsequently forming a channel layer.
Based on the first sacrificial layer to be formed later and finally forming a first target sacrificial layer with a size smaller than that of the second sacrificial layer, a first sacrificial material layer 210A and a second sacrificial material layer 210B which are different are formed in this step and used for being distinguished from the second sacrificial layer when the sidewall of the first sacrificial layer with a partial thickness is removed later.
The number of layers of the sacrificial material layer 210 and the channel material layer 220 in the stacked material layer 20 is matched with the number of sacrificial layers and channel layers to be formed, and the stacked material layer correspondingly includes 3 sacrificial material layers and 3 channel material layers when 3 sacrificial layers and 3 channel layers are alternately stacked in the channel stack of the present embodiment.
In the present embodiment, an Epitaxial Growth process (Epitaxial Growth) is used to form the stacked material layer 20 on the initial substrate 100. The epitaxial growth process is adopted, so that the lattice structure of the semiconductor structure is not easy to damage, and the subsequently formed semiconductor structure is not easy to leak electricity.
In this embodiment, the process of forming the stacked material layer by using the epitaxial growth process may include a sacrificial material layer forming stage and a channel material layer forming stage, where the introduced epitaxial gases are different in the sacrificial material layer forming stage and the channel material layer forming stage; in the stage of forming the first sacrificial material layer and the stage of forming the second sacrificial material layer, the introduced epitaxial gases are the same, and the flow rates of the introduced epitaxial gases are different.
The method comprises the steps of filling different epitaxial gases into a channel material layer and a sacrificial material layer, wherein the channel material layer and the sacrificial material layer are formed by different materials through controlling the filling of different epitaxial gases, and the channel material layer and the sacrificial material layer are formed by different components through controlling the flow of the filled epitaxial gases, so that the channel material layer and the sacrificial material layer are separated from a second sacrificial layer formed by the second sacrificial material layer when the side wall of the first sacrificial layer formed by the first sacrificial material layer is removed in the follow-up process, and the influence of the step on the second sacrificial material layer is avoided or reduced.
In the present embodiment, the material of the sacrificial material layer 210 is silicon germanium, and the material of the channel material layer 220 is silicon. Specifically, the step of forming the stacked material layer on the substrate by using an epitaxial growth process may include: forming a first sacrificial material layer, wherein the epitaxial gas introduced in the stage of forming the first sacrificial material layer is germane and silane; forming a channel material layer, wherein the epitaxial gas introduced in the channel material layer forming stage is silane; and forming a second sacrificial material layer, wherein the epitaxial gas introduced in the second sacrificial material layer forming stage is germane and silane, and the flow rate of introducing germane in the second sacrificial material layer forming stage is less than that of introducing germane in the first sacrificial material layer forming stage.
In this embodiment, the shape of the first target sacrificial layer to be formed subsequently may be implemented by controlling the material and the component of the first sacrificial material layer, specifically, an etching process may be subsequently used to remove the sidewall of the first sacrificial layer with a partial thickness, and the higher the content of germanium in the etched material is, the higher the etching rate corresponding to the etching process is, so that different shapes are obtained according to the change of the content of germanium in the first sacrificial material layer. For example, in the first sacrificial material layer stage, the flow rate of germane is controlled to be gradually reduced, the content of germanium in the correspondingly formed first sacrificial material layer is gradually reduced, and the size of the correspondingly etched first target sacrificial layer is gradually increased; in the first sacrificial material layer stage, controlling the flow of germane to gradually increase, the content of germanium in the correspondingly formed first sacrificial material layer to gradually increase, and the size of the correspondingly etched first target sacrificial layer to gradually decrease; or, in the first sacrificial material layer stage, controlling the flow of germane to be unchanged, keeping the germanium content in the correspondingly formed first sacrificial material layer unchanged, and keeping the size of the correspondingly etched first target sacrificial layer unchanged. In an alternative example, the expected shape of the first target sacrificial layer may be a shape with a small bottom and a large top (e.g. a rounded truncated shape or a reversed truncated shape), and correspondingly, the flow rate of germane is controlled to be gradually reduced in the stage of the first sacrificial material layer, so as to form the first sacrificial material layer with the germanium content gradually reduced from bottom to top.
It should be noted that, in the stage of forming the first sacrificial material layer, the minimum value of the flow rate of introducing germane is greater than the maximum value of the flow rate of introducing germane in the stage of forming the second sacrificial material layer, so that the content of germanium in the first sacrificial material layer is generally far greater than that in the second sacrificial material layer, and the influence of the subsequent etching step on the second sacrificial material layer is further reduced.
Next, referring to fig. 4 and fig. 5, removing the stacked material layer in a partial region and the initial base with a partial thickness in the partial region, taking the initial base with the remaining thickness as the substrate 101, the initial base protruding from the substrate as the fin portion 102, and the remaining stacked material layer on the fin portion 102 as the channel stack 21.
It should be noted that, in the embodiments of the present invention, a length direction Y and a width direction X of the channel layer are defined according to a carrier transport direction in the channel layer, where the carrier transport direction in the channel layer is the length direction Y of the channel layer, and a direction perpendicular to the direction is the width direction X of the channel layer. FIG. 4 is a top view of a top surface of a substrate according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line AA' of FIG. 4.
The stacked material layer in a partial region and the initial base with a partial thickness in the partial region are removed to implement patterning of the stacked material layer and the initial base, so as to form the substrate 101, the fin 102 protruding from the substrate, and the channel stack 21 on the fin 102. In the present embodiment, the fin 102 extends along the length direction Y of the channel layer.
In the present embodiment, the substrate 101, the fin portion 102 protruding from the substrate, and the channel stack 21 on the fin portion 102 may be implemented in a patterning process. Specifically, the process of the substrate 101, the fin portion 102 protruding from the substrate, and the channel stack 21 on the fin portion 102 includes: forming a patterned first mask layer 110 on the stacked material layer, wherein the first mask layer 110 covers a preset region for forming a fin portion and exposes other regions except the region; and taking the first mask layer 110 as a mask, and etching to remove the stacked material layer in the exposed area of the first mask layer 110 and the initial substrate with partial thickness in the partial area.
The first mask layer 110 may be a photoresist layer or a hard mask layer, and is preferably a hard mask layer in this embodiment, and correspondingly, the hard mask layer may be made of silicon nitride (SiN) or silicon oxide (SiO)2) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (a-C), silicon oxycarbonitride (SiOCN), and when multiple materials are used, the hardmask layer may be a stack of multiple material layers. In this embodiment, the hard mask layer may be made of silicon nitride. Also, after forming the channel stack 21, the first mask layer 110 may remain to a subsequent step to continue to protect the top surface of the channel stack 21 in the subsequent step.
In the formed channel stack 21, the remaining channel material layer is used as a channel layer 221, and the remaining sacrificial material layer is used as a sacrificial layer 211, wherein the sacrificial layer located at the bottom of the channel stack and connected to the fin portion is a first sacrificial layer 211A, and the other sacrificial layers except the first sacrificial layer 211A are second sacrificial layers 211B.
Referring to fig. 6, a partial thickness of the sidewall of the first sacrificial layer 211A is removed to form a first target sacrificial layer 211C. Fig. 6 is a cross-sectional view taken along the direction of fig. 5.
The bottom dimension of the first target sacrificial layer 211C is smaller than the dimension of the channel layer 221 in the width direction of the channel layer, wherein the channel stack including the first target sacrificial layer is a target channel stack 22.
In the present embodiment, a dimension D1 of the bottom of the first target sacrificial layer 211C in the width direction of the channel layer is further smaller than a dimension D2 of the second sacrificial layer 211B in the width direction of the channel layer.
In this embodiment, the sacrificial layers (including the first target sacrificial layer and the second sacrificial layer) in the target channel stack 22 are used to occupy spatial locations for forming a gate structure in a subsequent process.
By forming the first target sacrificial layer 211C having a size in the width direction of the channel layer smaller than that of the second sacrificial layer 211B in the width direction of the channel layer, the size of the gate structure formed at the position of the first target sacrificial layer subsequently can be reduced, so that the size of the parasitic MOS located there is also reduced, the influence of the parasitic MOS located there is further reduced, and the performance of the device is improved.
The thickness ratio of the first sacrificial layer to be removed is not too large or too small. In the embodiment of the present invention, the larger the thickness ratio of the first sacrificial layer is removed, the smaller the size of the subsequent parasitic MOS located therein is, however, the first sacrificial layer provides a process location for the subsequent gate structure and also provides support for the channel layer in the channel stack, and the removed thickness ratio is too large, and collapse of the channel layer due to too small support force provided for the channel layer may occur. In this embodiment, in the step of removing the sidewall of the partial thickness of the first sacrificial layer, the thickness removed by the first sacrificial layer is 10% to 40% of the dimension in the width direction of the channel layer, and illustratively, the thickness removed by the first sacrificial layer is 30% of the dimension in the width direction of the channel layer.
In addition, in this embodiment, an etching process may be used to remove a sidewall of a partial thickness of the first sacrificial layer, where an etching rate of the etching process corresponding to the first sacrificial layer is greater than an etching rate of the etching process corresponding to the second sacrificial layer, so as to avoid or reduce an influence of this step on the second sacrificial material layer.
In the etching of the sacrificial layer containing germanium in the embodiment, the higher the content of germanium in the etched material is, the higher the etching rate corresponding to the etching process is. Specifically, the sidewalls of the first sacrificial layer with a partial thickness may be removed by etching with an HCl solution or an HCl vapor.
Based on the gradual decrease of the germanium content of the first sacrificial layer from bottom to top in the present embodiment, the cross section of the first target sacrificial layer formed by etching is an inverted trapezoid (refer to fig. 6), so that the bottom dimension of the first target sacrificial layer is reduced as much as possible on the premise of effectively supporting the channel layer 221. In other embodiments of the present invention, the shape of the first target sacrificial layer formed in this step may also be controlled by controlling the germanium content of the first sacrificial material layer. In particular, where the desired shape is one in which the top and bottom dimensions are uniform, the germanium content of the first sacrificial material can be controlled to remain uniform when the first sacrificial material layer is formed.
With continued reference to fig. 6, after the step of removing the sidewall of the partial thickness of the first sacrificial layer, an isolation layer 120 may be further formed, where the isolation layer 120 covers the substrate exposed by the first target sacrificial layer 211C.
The isolation layer 120 is used to electrically isolate the fins 102 from each other, and at the same time, electrically isolate the first target sacrificial layer 211C on each fin from each other.
In this embodiment, the isolation layer 120 covers the substrate 101 and the fin portion 102 exposed by the first target sacrificial layer 211C. The material of the isolation layer 120 includes silicon oxide. In other embodiments, the material of the isolation layer 150 may further include one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
It should be noted that the top surface of the isolation layer 120 is not higher than the top surface of the first target sacrificial layer 211C, which is beneficial for removing the first target sacrificial layer 211C subsequently.
In the embodiment of the present invention, after the isolation layer 120 is formed, the first mask layer 110 may be removed, and a dummy gate oxide layer (not shown in the figure) may be further formed on a portion of the top surface and a portion of the sidewall of the target channel stack 22, where the dummy gate oxide layer is made of silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
Referring to fig. 7 and 8, a dummy gate layer 310 crossing the target channel stack 22 and dummy gate spacers 320 located at both sides of the dummy gate layer 310 are formed. Fig. 8 is a top view of the top of the substrate according to the embodiment of the present invention, and fig. 7 is a cross-sectional view along line BB'.
When the isolation layer is formed in this embodiment, in this step, a dummy gate layer 310 crossing the target channel stack 22 and dummy gate spacers 320 located at two sides of the dummy gate layer 310 are formed on the isolation layer.
In this embodiment, the dummy gate layer 310 and the dummy gate sidewall 320 on both sides of the dummy gate layer 310 are used as the dummy gate structure 30, the dummy gate layer 310 occupies a space for forming a gate structure in a subsequent process, the dummy gate sidewall 320 plays a role in protecting a sidewall of the dummy gate layer, and defines a formation region of a source-drain doped region in the subsequent process.
The material of the dummy gate layer 310 is polysilicon. In other embodiments, the material of the dummy gate layer 310 may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
The material of the dummy gate sidewall 320 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, the dummy gate sidewall 320 may have a single-layer structure or a stacked-layer structure, and the dummy gate sidewall 320 is different from the material of the dummy gate layer.
The step of forming the dummy gate structure 30 includes: forming a dummy gate material layer (not shown) on the isolation layer and crossing the target channel stack; forming a patterned gate mask layer 130 on the dummy gate material layer; etching the dummy gate material layer by using the gate mask layer 130 as a mask to form a dummy gate layer 310; forming a sidewall material layer (not shown) conformally covering the dummy gate layer 310; and removing the side wall material layers on the top of the pseudo gate layer, the top of the target channel layer and the top of the isolation layer, and keeping the side wall material layer on the side wall of the pseudo gate layer as the pseudo gate side wall 320.
The gate mask layer 130 may remain in the subsequent steps to protect the top of the dummy gate layer 310.
In this embodiment, the dummy gate material Layer may be formed by an epitaxial growth process, and the sidewall material Layer may be formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process.
In the embodiment of the present invention, after the step of forming the dummy gate layer crossing the target channel stack and the dummy gate spacers located at both sides of the dummy gate layer, referring to fig. 9 (fig. 9 is a cross-sectional view based on the direction of fig. 8), the target channel stacks at both sides of the dummy gate structure are further removed, and a first groove (referring to the space at both sides of the effective channel stack in fig. 9) is formed, where the remaining target channel stack overlapped with the dummy gate layer is an effective channel stack 23.
The first groove is used for providing a space position for the subsequent formation of a source-drain doped layer. The sacrificial layer in the effective channel stack 23 is used to support the channel layer, provide process conditions for the spaced-apart suspension of the subsequent channel layer, and also to occupy spatial positions for the subsequently formed gate structure.
In this embodiment, a wet etching process or a dry etching process may be used to etch the target channel stacks on both sides of the dummy gate structure, so as to form the first groove.
Further, in order to isolate the sacrificial layer from the source-drain doping layer formed subsequently, an inner sidewall is further formed on the sidewall of the sacrificial layer in this embodiment. Specifically, referring to fig. 10 (fig. 10 is a cross-sectional view based on the direction of fig. 9), after the target channel stacks on both sides of the pseudo gate structure are removed by etching, sidewalls of a partial thickness of the sacrificial layer in the effective channel stack may be further removed, a second groove surrounded by the channel layer and the remaining sacrificial layer or surrounded by the channel layer, the remaining sacrificial layer, and the fin portion is formed, and an inner sidewall 140 is formed in the second groove.
It should be noted that, in the process of etching the sidewall of the sacrificial layer to form the second groove, the same process as the aforementioned process of etching the sidewall of the first sacrificial layer to form the first target sacrificial layer may be adopted, so that in this step, the dimension of the sacrificial layer connected to the substrate along the length direction of the channel layer may be reduced, thereby further reducing the influence of the parasitic MOS at this position, and improving the performance of the device.
Referring to fig. 11 (fig. 11 is a cross-sectional view based on the direction of fig. 10), source and drain doping layers 150 are formed in the first recess, and the source and drain doping layers 150 are in contact with the channel layer 222 in the effective channel stack.
The source-drain doping layer 150 may be silicon, and in other embodiments, the material of the source-drain doping layer may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
In this embodiment, the source-drain doping layer 150 is formed by an epitaxial process.
When the device is an NMOS device, the doped ions in the source drain doped layer are N-type ions, and the N-type ions are P ions, As ions or Sb ions; when the device is a PMOS device, the doped ions In the source drain doped layer are P-type ions, and the P-type ions are B ions, Ga ions or In ions.
Referring to fig. 12 (fig. 12 is a cross-sectional view based on the direction of fig. 11), an interlayer dielectric layer 160 is formed on the substrate where the dummy gate structure is exposed, and the interlayer dielectric layer 160 covers the source-drain doping layer 150 and exposes the top of the dummy gate structure 30.
The interlayer dielectric layer 160 is used for realizing electrical isolation between adjacent devices, and the material of the interlayer dielectric layer 160 is an insulating material. In this embodiment, the interlayer dielectric layer 160 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
Specifically, the step of forming the interlayer dielectric layer 160 includes: forming an interlayer dielectric material layer (not shown) on the dummy gate structure and the exposed part of the dummy gate structure, wherein the interlayer dielectric material layer covers the top of the dummy gate structure; and carrying out planarization treatment on the interlayer dielectric material layer, removing the interlayer dielectric material layer higher than the pseudo gate structure 30, and taking the rest interlayer dielectric material layer after the planarization treatment as the interlayer dielectric layer 160.
In this embodiment, with reference to fig. 11 and 12, during the planarization process, the gate mask layer 130 is also removed at the same time.
Referring to fig. 13 (fig. 13 is a cross-sectional view based on the direction of fig. 12), the dummy gate layer and the first target sacrificial layer overlapping with the dummy gate layer are removed, a gate opening 410 between the dummy gate sidewalls is formed, and a first channel 420 communicating with the gate opening is formed at the position where the first target sacrificial layer overlaps with the dummy gate layer.
In this embodiment, the dummy gate layer and the first target sacrificial layer overlapping with the dummy gate layer are removed simultaneously, the second sacrificial layer in the effective channel stack is also removed, and a second channel 430 communicating with the gate opening is formed at the position of the second sacrificial layer.
The gate opening 410, the first channel 420 and the second channel 430 are used for providing a space position for forming a gate structure.
The dummy gate layer, the first target sacrificial layer and the second sacrificial layer can be removed by adopting an etching process, and in the etching process of the first target sacrificial layer and the second sacrificial layer, the etching rates of the first target sacrificial layer and the second sacrificial layer are both greater than the etching rate of the channel layer, so that the channel layer is not easily damaged in the etching process. Specifically, the etching process, the first channel and the second channel may be performed using an HCl solution.
Referring to fig. 14 to 16, a gate structure is formed in the gate opening and the first channel. Wherein fig. 14 is a top view of the top surface of the substrate, fig. 15 is a cross-sectional view taken along a line BB ', and fig. 16 is a cross-sectional view taken along a line AA'.
The gate structure formed in the gate opening is used as a first gate structure 411, and the gate structure formed in the first channel is used as a second gate structure 421.
Based on the bottom dimension of the first target sacrificial layer being smaller than the channel layer in the width direction of the channel layer, the dimension D1 of the second gate structure 421 formed at the corresponding position is smaller than the dimension D2 of the channel layer.
In this embodiment, a gate structure is formed in the second channel while forming a gate structure in the gate opening and the first channel, and the gate structure formed in the second channel is taken as a third gate structure 431. Wherein the dimension of the third gate structure 431 in the width direction of the channel layer is identical to the dimension of the channel layer, and is D2.
The gate structure comprises a gate electrode and a gate dielectric layer located on the bottom and the side wall of the gate electrode and between the gate electrode and the channel layer. In this embodiment, the gate structure includes a first gate structure, a second gate structure, and a third gate structure, where the first gate structure includes a first gate electrode and a first gate dielectric layer (not shown) located at the bottom and on the sidewall of the first gate electrode; the second gate structure comprises a second gate electrode and a second gate medium layer (not shown in the figure) positioned at the bottom and the side wall of the second gate electrode and between the second gate electrode and the channel layer; the third gate structure includes a third gate electrode and a third gate dielectric layer (not shown) between the third gate electrode and the channel layer.
In this embodiment, the gate structure is a metal gate structure, and thus the first gate electrode, the second gate electrode, and the third gate electrode are metal gate layers. In this embodiment, the material of the metal gate layer is magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer may also be W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like. Alternatively, in other embodiments, the gate structure may also be a polysilicon gate structure, and the first gate electrode, the second gate electrode, and the third gate electrode are polysilicon gate layers correspondingly.
The first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are all gate dielectric layers, the gate dielectric layers can be high-k dielectric layers, and the high-k dielectric layers are dielectric materials with relative dielectric constants larger than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3One or more of them.
Because the second gate structure is formed in the space position occupied by the first target sacrificial layer, the size of the correspondingly formed second gate structure in the width direction of the channel layer is reduced, so that the size of the parasitic MOS at the position is reduced, the influence of the parasitic MOS at the position is further reduced, and the performance of the device is improved.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 14 to 16, schematic structural diagrams of an embodiment of a semiconductor structure of the present invention are shown.
The semiconductor device comprises a substrate 10, a gate structure positioned on the substrate 10 and pseudo gate side walls 320 positioned on two sides of the gate structure; a channel layer 222 traversing the gate structure, a width direction (X direction) of the channel layer 222 being an extension direction of the gate structure;
wherein, the gate structure crossing the channel layer is taken as a first gate structure 411, the gate structure which is located at the bottom of the overlapped part of the first gate structure 411 and the channel layer 222 and is connected with the substrate 10 is taken as a second gate structure 421; in a width direction along the channel layer 222, a bottom dimension D1 of the second gate structure 421 is smaller than a dimension D2 of the channel layer 222.
The bottom dimension D1 of the second gate structure 421 is smaller than the dimension D2 of the channel layer 222, so that the dimension of the parasitic MOS located therein is also reduced, the influence of the parasitic MOS is further reduced, and the performance of the device is improved.
In the width direction of the channel layer, the ratio of the bottom dimension of the second gate structure 421 to the dimension of the channel layer 222 is 0.6-0.9. For example, a ratio of a bottom size of the second gate structure 421 to a size of the channel layer 222 may be 0.7.
In this embodiment, the substrate 10 may include a substrate 101 and a fin 102 protruding from the substrate, and the substrate 101 and the fin 102 protruding from the substrate are made of silicon. In other embodiments, the substrate and the fin portion protruding from the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The number of the channel layers may be 1, or may be multiple, and in this embodiment, the plurality of channel layers 222 are suspended on the substrate 10 at intervals. The channel layer 222 may be silicon, and in other embodiments, the channel layer may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
According to the embodiment of the invention, the length direction Y and the width direction X of the channel layer are defined according to the transport direction of carriers in the channel layer, wherein the transport direction of the carriers in the channel layer is taken as the length direction Y of the channel layer, and the direction vertical to the transport direction is taken as the width direction X of the channel layer.
Corresponding to the plurality of channel layers 222 in the present embodiment, the gate structure further includes a third gate structure 431 located between the plurality of channel layers 222 at the portion overlapping the first gate structure 411, the third gate structure 431 is connected to the first gate structure 411, and the size of the third gate structure 431 is larger than the size of the bottom of the second gate structure 421.
The first gate structure 411 includes a first gate electrode and a first gate dielectric layer located at the bottom and the sidewall of the first gate electrode; the second gate structure 421 includes a second gate electrode and a second gate dielectric layer located at the bottom and the sidewall of the second gate electrode and between the second gate electrode and the channel layer; the third gate structure 431 includes a third gate electrode and a third gate dielectric layer between the third gate electrode and the channel layer.
In this embodiment, the gate structure is a metal gate structure, and thus the first gate electrode, the second gate electrode, and the third gate electrode are metal gate layers. In this embodiment, the material of the metal gate layer is magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer may also be W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like. Alternatively, in other embodiments, the gate structure may also be a polysilicon gate structure, and the first gate electrode, the second gate electrode, and the third gate electrode are polysilicon gate layers correspondingly.
The first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are all gate dielectric layers, the gate dielectric layers can be high-k dielectric layers, and the high-k dielectric layers are dielectric materials with relative dielectric constants larger than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3One or more of them.
In this embodiment, the dummy gate sidewall spacers 320 are located at two sides of the first gate structure 411, and play a role in isolating and protecting the sidewalls of the gate structure. The material of the dummy gate sidewall 320 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, the dummy gate sidewall 320 may have a single-layer structure or a stacked-layer structure, and the dummy gate sidewall 320 is different from the material of the dummy gate layer.
In the embodiment of the present invention, inner sidewalls 140 are further disposed on two sides of the second gate structure and the third gate structure, and the inner sidewalls are used for isolating and protecting the second gate structure and the third gate structure. The material of the inner sidewall spacers may be the same as the material of the dummy gate sidewall spacers 320.
In this embodiment, the semiconductor structure further includes an isolation layer 120 located between the first gate structure 411 and the substrate 10. The isolation layer 120 is used to electrically isolate the fins 102 from each other, and at the same time, electrically isolate the first gate structures 411 on the fins from each other.
The material of the isolation layer 120 includes silicon oxide. In other embodiments, the material of the isolation layer 120 may further include one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Note that the top surface of the isolation layer 120 is not higher than the top surface of the second gate structure 421.
In the embodiment of the present invention, the semiconductor structure further includes a source-drain doping layer 150 located on the fin portion 102 at two sides of the gate structure and contacting the channel layer; the source-drain doping layer 150 may be silicon, and in other embodiments, the material of the source-drain doping layer 150 may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
When the device is an NMOS device, the doped ions in the source drain doped layer are N-type ions, and the N-type ions are P ions, As ions or Sb ions; when the device is a PMOS device, the doped ions In the source drain doped layer are P-type ions, and the P-type ions are B ions, Ga ions or In ions.
In the embodiment of the present invention, the semiconductor structure further includes interlayer dielectric layers 160 located at two sides of the gate structure and covering the source-drain doping layer 150, and the top of the interlayer dielectric layer 160 is flush with the top of the gate structure.
The interlayer dielectric layer 160 is used for realizing electrical isolation between adjacent devices, and the material of the interlayer dielectric layer is an insulating material. In this embodiment, the interlayer dielectric layer is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In the embodiment of the present invention, the bottom dimension D1 of the second gate structure 421 is smaller than the dimension D2 of the channel layer 222, so that the dimension of the parasitic MOS located therein is also reduced, the influence of the parasitic MOS located therein is further reduced, and the performance of the device is improved.
The semiconductor structure of the embodiment of the invention may be formed by using the forming method of the foregoing embodiment, or may be formed by using other forming methods. For a detailed description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a channel lamination layer is formed on the substrate and comprises a sacrificial layer and a channel layer which are alternately stacked, wherein the sacrificial layer at the bottom of the channel lamination layer, which is connected with the substrate, is a first sacrificial layer;
removing the side wall of the first sacrificial layer with partial thickness to form a first target sacrificial layer, wherein the bottom size of the first target sacrificial layer is smaller than the size of the channel layer in the width direction of the channel layer, and the channel lamination including the first target sacrificial layer is a target channel lamination;
forming a pseudo gate layer crossing the target channel lamination and pseudo gate side walls positioned on two sides of the pseudo gate layer;
removing the pseudo gate layer and the first target sacrificial layer at the part overlapped with the pseudo gate layer, forming a gate opening between the pseudo gate side walls at the position of the pseudo gate structure, and forming a first channel communicated with the gate opening at the position of the part overlapped with the pseudo gate layer of the first target sacrificial layer;
and forming a gate structure in the gate opening and the first channel, wherein the gate structure formed in the gate opening is used as the first gate structure, and the gate structure formed in the first channel is used as the second gate structure.
2. The method of forming a semiconductor structure according to claim 1, wherein in the step of removing the partial thickness of the sidewall of the first sacrificial layer, the removal thickness of the first sacrificial layer is 10% to 40% of a dimension in a width direction of the channel layer.
3. The method of forming a semiconductor structure according to claim 1, wherein the channel stack includes a plurality of alternately stacked sacrificial layers and channel layers, wherein the sacrificial layer other than the first sacrificial layer is a second sacrificial layer;
and removing the side wall of the first sacrificial layer with partial thickness by adopting an etching process, wherein the etching rate of the etching process corresponding to the first sacrificial layer is greater than that of the etching process corresponding to the second sacrificial layer.
4. The method of claim 3, wherein the base comprises a substrate and a fin protruding from the substrate, and wherein the step of forming the channel stack on the base comprises:
providing an initial substrate;
forming stacked material layers on the initial substrate, wherein the stacked material layers comprise sacrificial material layers and channel material layers which are alternately stacked, the sacrificial material layer which is positioned at the bottom of the stacked material layers and connected with the initial substrate is a first sacrificial material layer, the other sacrificial material layers except the first sacrificial material layer in the stacked material layers are second sacrificial material layers, and the first sacrificial material layer is different from the second sacrificial material layers;
removing the stacked material layers in the partial region and the initial base with partial thickness in the partial region, taking the initial base with residual thickness as the substrate, taking the initial base protruding out of the substrate as the fin portion, and taking the residual stacked material layers on the fin portion as the channel lamination.
5. The method of forming a semiconductor structure of claim 4, wherein an epitaxial growth process is used to form stacked material layers on the initial substrate; wherein, in the stage of forming the sacrificial material layer and the stage of forming the channel material layer, the introduced epitaxial gases are different; in the stage of forming the first sacrificial material layer and the stage of forming the second sacrificial material layer, the introduced epitaxial gases are the same, and the flow rates of the introduced epitaxial gases are different.
6. The method of forming a semiconductor structure of claim 5, wherein the step of forming stacked material layers on the substrate using an epitaxial growth process comprises:
forming a first sacrificial material layer, wherein the epitaxial gas introduced in the stage of forming the first sacrificial material layer is germane and silane;
forming a channel material layer, wherein the epitaxial gas introduced in the channel material layer forming stage is silane;
and forming a second sacrificial material layer, wherein the epitaxial gas introduced in the second sacrificial material layer forming stage is germane and silane, and the flow rate of introducing germane in the second sacrificial material layer forming stage is less than that of introducing germane in the first sacrificial material layer forming stage.
7. The method as claimed in claim 6, wherein the flow of germane is gradually decreased during the step of forming the first sacrificial material layer, and a minimum value of the flow of germane introduced during the step of forming the first sacrificial material layer is greater than a maximum value of the flow of germane introduced during the step of forming the second sacrificial material layer.
8. The method for forming the semiconductor structure according to claim 6 or 7, wherein the sidewall of the partial thickness of the first sacrificial layer is removed by using an etching process, wherein the higher the content of germanium in the etched material is, the higher the etching rate corresponding to the etching process is.
9. The method of claim 8, wherein the partial thickness of the sidewalls of the first sacrificial layer are removed using a HCl solution or a HCl vapor etch.
10. The method for forming a semiconductor structure according to claim 1, wherein after the step of removing the sidewall with a partial thickness of the first sacrificial layer and before the step of forming the dummy gate layer crossing the target channel stack and the dummy gate sidewall spacers located at two sides of the dummy gate layer, the method further comprises:
forming an isolation layer, wherein the isolation layer covers the substrate exposed out of the first target sacrificial layer;
the step of forming the dummy gate layer crossing the target channel stack and the dummy gate side walls located at two sides of the dummy gate layer specifically comprises: and forming a pseudo gate layer crossing the target channel lamination layer and pseudo gate side walls positioned at two sides of the pseudo gate layer on the isolation layer.
11. The method for forming a semiconductor structure according to claim 3, wherein the steps of forming the dummy gate layer crossing the target channel stack and the dummy gate spacers located on both sides of the dummy gate layer are performed after the step of forming the dummy gate layer crossing the target channel stack and the dummy gate spacers located on both sides of the dummy gate layer, and before the step of removing the dummy gate layer and the first target sacrificial layer overlapping with the dummy gate layer, further comprise:
removing the target channel lamination layers on two sides of the pseudo gate structure to form a first groove, wherein the residual target channel lamination layers overlapped with the pseudo gate layer are effective channel lamination layers;
forming a source-drain doped layer in the first groove, wherein the source-drain doped layer is in contact with the channel layer in the effective channel laminated layer;
and forming an interlayer dielectric layer on the substrate exposed out of the pseudo gate structure, wherein the interlayer dielectric layer covers the source-drain doping layer and exposes out of the top of the pseudo gate structure.
12. The method for forming a semiconductor structure according to claim 11, wherein after the step of removing the target channel stack on both sides of the dummy gate structure and before the step of forming source-drain doping layers on both sides of the effective channel stack, the method further comprises:
removing the side wall of the sacrificial layer in the effective channel lamination layer with partial thickness to form a second groove surrounded by the channel layer and the residual sacrificial layer or the channel layer, the residual sacrificial layer and the fin part;
forming an inner side wall in the second groove;
wherein the formation process of the second groove is the same as the formation process of the first target sacrificial layer.
13. The method of forming a semiconductor structure according to claim 11, wherein in the step of removing the dummy gate layer and the first target sacrificial layer at a portion overlapping with the dummy gate layer, the second sacrificial layer in the effective channel stack is also removed, and a second channel communicating with the gate opening is formed at a position of the second sacrificial layer;
in the step of forming the gate structure in the gate opening and the first channel, a gate structure is further formed in the second channel, and the gate structure formed in the second channel is taken as a third gate structure.
14. The method of forming a semiconductor structure of claim 13, wherein the first gate structure comprises a first gate electrode and a first gate dielectric layer located at a bottom and sidewalls of the first gate electrode; the second gate structure comprises a second gate electrode and a second gate medium layer positioned at the bottom and the side wall of the second gate electrode and between the second gate electrode and the channel layer; the third gate structure includes a third gate electrode and a third gate dielectric layer between the third gate electrode and the channel layer.
15. A semiconductor structure, comprising:
the device comprises a substrate, a grid structure positioned on the substrate and pseudo grid side walls positioned on two sides of the grid structure;
a channel layer traversing the gate structure, a width direction of the channel layer being an extension direction of the gate structure;
the gate structure crossing the channel layer is taken as a first gate structure, the gate structure is positioned at the bottom of the overlapped part of the first gate structure and the channel layer, and the gate structure connected with the substrate is taken as a second gate structure; a bottom dimension of the second gate structure is smaller than a dimension of the channel layer in a width direction of the channel layer.
16. The semiconductor structure of claim 15, wherein a ratio of a dimension of a bottom of the second gate structure to a dimension of the channel layer in a width direction of the channel layer is 0.6 to 0.9.
17. The semiconductor structure of claim 15, wherein the channel layer is a plurality of, the plurality of channel layers are suspended in a spaced apart relationship on the substrate, the gate structure further comprising a third gate structure between the plurality of channel layers in an overlapping portion with the first gate structure and connected to the first gate structure, the third gate structure having a dimension greater than a bottom dimension of the second gate structure.
18. The semiconductor structure of claim 15, further comprising an isolation layer between the first gate structure and the substrate.
19. The semiconductor structure of claim 15, wherein the base comprises a substrate and a fin protruding from the substrate, the channel layer is on the fin, and the gate structure spans the fin and the channel layer on the fin.
20. The semiconductor structure of claim 19, wherein the semiconductor structure further comprises: the source-drain doping layer is positioned on the fin parts on two sides of the grid structure and is in contact with the channel layer;
and the interlayer dielectric layers are positioned on two sides of the grid structure and cover the source drain doping layer, and the top of each interlayer dielectric layer is flush with the top of the grid structure.
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