CN112151365A

CN112151365A - Semiconductor structure and forming method thereof

Info

Publication number: CN112151365A
Application number: CN201910577067.4A
Authority: CN
Inventors: 谭颖
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2020-12-29
Anticipated expiration: 2039-06-28

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a plurality of channel laminated layers are sequentially formed on the substrate; forming a dummy gate structure crossing the channel stack; etching the channel lamination layers on two sides of the pseudo-gate structure, enabling the channel lamination layers to sequentially retract along the direction in which the top of the pseudo-gate structure points to the substrate, and enabling the rest channel lamination layers and the substrate to enclose a groove; forming a source drain doping layer in the groove; removing the dummy gate structure to form a gate opening exposing the channel lamination; removing the sacrificial layer in the channel lamination to form a through groove, wherein the through groove is surrounded by the adjacent channel layer and the source-drain doping layer, or is surrounded by the substrate, the channel layer adjacent to the substrate and the source-drain doping layer, and the through groove is communicated with the grid opening; forming an inner wall layer on the side wall of the source drain doping layer exposed from the through groove; and forming a gate structure in the gate opening and the through groove. The embodiment of the invention meets the requirement that the semiconductor structure can be applied to circuits with different working voltages.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving toward higher element density and higher integration, and the trend of semiconductor process nodes following moore's law is decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the device density and integration of semiconductor devices increase, the channel length of transistors has to be continuously shortened in order to accommodate the reduction of process nodes.

The shortening of the channel length of the transistor has the advantages of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is also shortened, so the control capability of the gate to the channel is deteriorated, so that the sub-threshold leakage (SCE), which is called short-channel effects, is more likely to occur, and the channel leakage current of the transistor is increased.

Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the all-around gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the all-around gate transistor has stronger control capability on the channel, and can better inhibit a short-channel effect.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which satisfy the requirement that a fully-wrapped-gate transistor can be applied to circuits with different operating voltages.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a plurality of channel lamination layers are sequentially formed on the substrate, and each channel lamination layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer; forming a dummy gate structure crossing the channel lamination layer, wherein the dummy gate structure covers part of the top and part of the side wall of the channel lamination layer; etching the channel lamination layers on two sides of the pseudo-gate structure to enable the channel lamination layers to be in the direction pointing to the substrate along the top of the pseudo-gate structure, enabling the end parts of the channel layers to be sequentially retracted, and enabling the residual channel lamination layers and the substrate to form a groove in a surrounding mode; forming a source drain doping layer in the groove; removing the pseudo gate structure to form a gate opening exposing the channel lamination; removing the sacrificial layer in the channel lamination to form a through groove, wherein the through groove is surrounded by the adjacent channel layer and the source-drain doping layer, or the through groove is surrounded by the substrate, the channel layer adjacent to the substrate and the source-drain doping layer, and the through groove is communicated with the grid opening; forming an inner wall layer on the side wall of the source drain doping layer exposed out of the through groove; and forming a gate structure in the gate opening and the through groove formed with the inner wall layer.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the channel structure layer is positioned on the substrate and is arranged at intervals with the substrate, the channel structure layer comprises a plurality of channel layers arranged at intervals, and the end parts of the channel layers are sequentially retracted along the direction in which the top of the channel structure layer points to the substrate; the grid structure stretches across the channel structure layer, the grid structure covers the top of part of the substrate and surrounds the channel layer, the grid structure positioned between the substrate and the channel layer adjacent to the substrate and the grid structure positioned between the adjacent channel layers are first parts of the grid structure, and the rest grid structure is a second part of the grid structure; the source-drain doping layer is positioned in the channel structure layers at two sides of the grid structure; and the inner wall layer is positioned between the first part of the grid structure and the source-drain doping layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the embodiment of the invention, the channel lamination layers on two sides of the pseudo-gate structure are etched, so that the channel lamination layers are sequentially retracted along the direction in which the top of the pseudo-gate structure points to the substrate, the end parts of the channel layers are sequentially retracted, and the lengths of the channel layers are different, so that after a transistor with a full-surrounding gate structure (GAA) is formed, each channel layer in the transistor with the full-surrounding gate structure has different starting voltages, therefore, when a device works, the effect of starting different channel layers in the transistor can be realized by applying different voltages to the transistor, and the requirement that the transistor with the full-surrounding gate structure is applied to circuits with different working voltages is met; furthermore, after removing the dummy gate structure and the sacrificial layer in the channel stack, the embodiment of the present invention further includes: and forming an inner wall layer on the side walls of the source-drain doping layers exposed by the through grooves, wherein after a grid structure is formed subsequently, the grid structure positioned in the through grooves is used as a first part of the grid structure, the inner wall layer is positioned between the first part of the grid structure and the source-drain doping layers, and the distance between the first part of the grid structure and the source-drain doping layers is increased, so that the parasitic capacitance between the grid structure and the source-drain doping layers is favorably reduced, and the performance of the semiconductor structure is further improved.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

FIGS. 2-14 are schematic structural diagrams corresponding to steps of a method of forming a semiconductor structure according to an embodiment of the present invention;

FIGS. 15-27 are schematic structural views corresponding to steps in a method of forming a semiconductor structure according to an embodiment of the present invention;

FIG. 28 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

Detailed Description

The transistor with the fully-enclosed gate structure formed at present is difficult to be applied to circuits with different working voltages. The reason why the transistor is difficult to be applied to circuits with different operating voltages is analyzed in combination with a semiconductor structure.

Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.

The semiconductor structure includes: a substrate 600; a channel structure layer 614 disposed on the substrate 600 and spaced apart from the substrate 600, wherein the channel structure layer 614 includes a plurality of channel layers 613 spaced apart; a gate structure 620 crossing the channel structure layer 614, the gate structure 620 covering a portion of the top of the substrate 600 and surrounding the channel layer 613; and the source-drain doping layer 650 is positioned in the channel structure layer 614 at two sides of the gate structure 620.

The semiconductor structure is a fully-surrounded gate structure transistor, in which the widths of the channel layers 613 are the same, and the turn-on voltages of each of the channel layers 613 in the semiconductor structure are also the same, and when the device operates, the semiconductor structure can only be applied to a circuit with a single operating voltage, or the semiconductor structure cannot be applied to different circuits with different operating voltages, which makes it difficult to meet the requirement of applying the semiconductor structure to circuits with different operating voltages.

In order to solve the technical problem, in the embodiments of the present invention, the channel stacks on both sides of the dummy gate structure are etched, so that the channel stacks are sequentially retracted along a direction in which the top of the dummy gate structure points to the substrate, and the end portions of the channel layers are different, so that after a transistor with a fully-surrounded gate structure is formed, each channel layer in the transistor with the fully-surrounded gate structure has a different turn-on voltage, and therefore, when a device is in operation, the effect of turning on different channel layers in the transistor can be achieved by applying different voltages to the transistor, thereby meeting the requirement that the transistor with the fully-surrounded gate structure is applied to circuits with different operating voltages; furthermore, after removing the dummy gate structure and removing the sacrificial layer in the channel stack, the embodiment of the present invention further includes: and after the dummy gate structure and the sacrificial layer in the channel lamination are removed, the inner wall layer is formed, so that the inner wall layers can be formed on the side walls of the source-drain doping layers exposed from all the through grooves in the same step, the process flow is simplified, and the process steps are simple.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 2 to 14 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 2, a substrate (not labeled) is provided, on which a plurality of channel stacks 114 are sequentially formed, each of the channel stacks 114 including a sacrificial layer 112 and a channel layer 113 on the sacrificial layer 112.

The substrate provides a process platform for subsequently forming a Gate-all-around (GAA) transistor.

In this embodiment, the base is a three-dimensional structure, and includes the substrate 100 and the fin portion 110 protruding from the substrate 100. In other embodiments, when the base is a planar structure, the base comprises only the substrate, respectively.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The fins 110 expose portions of the substrate 100, thereby providing a process foundation for the subsequent formation of isolation structures.

In this embodiment, the material of the fin 110 is the same as that of the substrate 100, and the material of the fin 110 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming the fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin may also be different from that of the substrate.

The channel stack 114 provides a process foundation for the subsequent formation of the spaced apart channel layer 113. Specifically, the sacrificial layer 112 supports the channel layer 113, so as to provide a process foundation for realizing the spaced-apart suspension arrangement of the channel layer 113 subsequently, and also occupy a space position for the formation of a subsequent metal gate structure, and the channel layer 113 is used for providing a channel of a fully-surrounded gate transistor. In the present embodiment, the channel stack 114 is formed on the fin 110.

In this embodiment, the channel layer 113 is made of Si, and the sacrificial layer 112 is made of SiGe. In the subsequent process of removing the sacrificial layer 112, the etching selectivity of SiGe and Si is relatively high, so that by setting the material of the sacrificial layer 112 to be SiGe and the material of the channel layer 113 to be Si, the influence of the removal process of the sacrificial layer 112 on the channel layer 113 can be effectively reduced, thereby improving the quality of the channel layer 113 and further facilitating the improvement of the device performance. In other embodiments, when forming a PMOS transistor, to improve the performance of the PMOS transistor, a SiGe channel technology may be used, the fin and the channel layer are made of SiGe, and the sacrificial layer is made of Si.

In this embodiment, the number of the channel stacks 114 is two, and includes a first channel stack 114a and a second channel stack 114b on the first channel stack 114 a. In other embodiments, the number of channel stacks may also be greater than or equal to three, depending on the actual process requirements.

In this embodiment, the method for forming a semiconductor structure further includes: an isolation structure 111 is formed on the substrate 100 where the channel stack 114 is exposed, the isolation structure 111 exposing sidewalls of the channel stack 114.

Isolation structures 111 are used to isolate adjacent devices or adjacent channel stacks 114. In this embodiment, the isolation structure 111 is made of silicon oxide. In other embodiments, the isolation structure may be made of other insulating materials such as silicon nitride or silicon oxynitride.

In this embodiment, the top surface of the isolation structure 111 is flush with the top surface of the fin 110, thereby preventing the fin 110 from acting as a channel.

With continued reference to fig. 2, a dummy gate structure 130 is formed across the channel stack 114, the dummy gate structure 130 covering a portion of the top and a portion of the sidewalls of the channel stack 114.

Dummy gate structure 130 occupies a spatial location for subsequently formed gate structures. In this embodiment, the dummy gate structure 130 includes a dummy gate layer 120, and the dummy gate layer 120 crosses over the channel stack 114 and covers a portion of the top and a portion of the sidewall of the channel stack 114.

In this embodiment, the material of the dummy gate layer 120 is polysilicon. In other embodiments, the material of the dummy gate layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, amorphous carbon, or other materials.

In this embodiment, the dummy gate structure 120 is a stacked structure, and before forming the dummy gate layer 120, the method further includes: a gate oxide layer 121 (shown in fig. 2) is formed conformally covering the surface of the channel stack 114, and the dummy gate layer 120 and the gate oxide layer 121 at the bottom of the dummy gate layer 120 are used to form a dummy gate structure 130. In other embodiments, the dummy gate structure may also be a single-layer structure, and the dummy gate structure only includes the dummy gate layer.

In this embodiment, the gate oxide layer 121 is made of silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride.

In this embodiment, a gate mask layer 123 is further formed on the top of the dummy gate layer 120. The gate mask layer 123 is used as an etching mask when the dummy gate layer 120 is formed, and the gate mask layer 123 is also used for protecting the dummy gate layer 120. In this embodiment, the gate mask layer 123 is made of silicon nitride.

In this embodiment, after forming the dummy gate structure 130, the method further includes: a first sidewall 122 is formed on a sidewall of the dummy gate layer 120. The first sidewall 122 is used as an etching mask for a subsequent etching process to define a formation region of a subsequent source/drain doping layer, and the first sidewall 122 is also used for protecting a sidewall of the dummy gate layer 120.

The material of the first sidewall 122 may be selected from silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the first sidewall 122 may have a single-layer structure or a stacked-layer structure. In this embodiment, the first sidewall 122 has a single-layer structure, and the material of the first sidewall 122 is silicon oxide.

Note that after the first sidewalls 122 are formed, the gate oxide layer 121 exposed by the first sidewalls 122 and the dummy gate layer 120 remains, and the gate oxide layer 121 can protect the channel stack 114 in a subsequent process. In other embodiments, the gate oxide layer exposed by the first side wall and the dummy gate layer may also be removed, only the gate oxide layer covered by the dummy gate layer and the first side wall is reserved, and the channel stacks on both sides of the dummy gate layer are exposed, which is convenient for the subsequent process steps.

Referring to fig. 3 to 8, the channel stacks 114 on both sides of the dummy gate structure 130 are etched, so that the plurality of channel stacks 114 are in a direction pointing to the substrate along the top of the dummy gate structure 130, the ends of the channel layer 113 are sequentially recessed, and a groove 150 is defined by the remaining channel stacks 114 and the substrate (as shown in fig. 8).

By enabling the channel lamination layers 114 to be along the direction of the top of the pseudo gate structure 130 pointing to the substrate, the ends of the channel layers 113 are sequentially retracted, so that the lengths of the channel layers 113 are different, after a transistor with a fully-surrounded gate structure is formed, each channel layer 113 in the transistor has different starting voltages, and therefore when the device works, the effect of starting different channel layers 113 in the transistor can be achieved by applying different voltages to the transistor, and the requirement that the transistor with the fully-surrounded gate structure is applied to circuits with different working voltages is met.

The distance of the recess at the end of the channel layer 113 should not be too small or too large. If the retracting distance of the end of the channel layer 113 is too small, the difference of the starting voltage of each channel layer 113 is small when the device works, and the difference of the starting voltages of different channel layers 113 is small, so that the effect of distinguishing different starting voltages is difficult to achieve; if the distance of the end portion of the channel layer 113 is too large, when the number of the channel layers 113 is large, the width of the channel layer 113 close to the substrate is too small, which easily increases the risk of the channel stack collapsing, and also easily affects the effective channel length of the device, thereby affecting the performance of the device. For this reason, in the present embodiment, the end portion of the channel layer 113 is recessed by a distance greater than 0nm and less than or equal to 5nm on one side.

In this embodiment, the number of the channel stacks 114 is two, and the step of etching the channel stacks 114 on both sides of the dummy gate structure 130 includes:

as shown in fig. 3, the second channel stack 114b exposed by the dummy gate structure 130 is etched by using the dummy gate structure 130 as a mask (as shown in fig. 2), and the remaining second channel stack 114b after etching is used as a top channel stack 114 c; as shown in fig. 4, a second sidewall 115 is formed on the sidewall of the top channel stack 114 c; as shown in fig. 5, the exposed first channel stack 114a of the second sidewall 115 is etched (as shown in fig. 4), and the remaining first channel stack 114a after etching is used as the bottom channel stack 114 d.

The second channel stack 114b exposed by etching the dummy gate structure 130 is prepared for forming the second sidewall 115. Specifically, the second channel stack 114b is etched by using the first sidewall 122 and the dummy gate structure 130 as masks.

In this embodiment, the second channel stack 114b exposed by the dummy gate structure 130 is etched by using an anisotropic dry etching process. By selecting the dry etching process, anisotropic etching is easily realized, so that the second channel lamination layer 114b exposed out of the dummy gate structure 130 can be removed, and the profile controllability of the dry etching process is better, which is beneficial to forming the second side wall 115 on the side wall of the top channel lamination layer 114c in the subsequent process. Specifically, the anisotropic dry etching process may be a plasma etching process.

In this embodiment, the material of the sacrificial layer 112 is SiGe, and the material of the channel layer 113 is Si, so the main etching gas used in the dry etching process includes fluorine-based gases, such as: CF (compact flash)₄、CHF₃Or C₂F₆And the like.

The second sidewalls 115 are used as an etching mask for the subsequent etching of the first channel stack 114a, and the second sidewalls 115 also protect the sidewalls of the top channel stack 114 c. In this embodiment, the second sidewall 115 is located on the sidewalls of the top channel stack 114c and the first sidewall 122.

In this embodiment, the second sidewall 115 and the first sidewall 122 are made of different materials, so that the second sidewall 115 can be removed conveniently, and the loss of the first sidewall 122 is reduced. In this embodiment, the second sidewall spacers 115 are made of silicon nitride. In other embodiments, the material of the second sidewall spacers may also be selected from silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

The thickness of the second sidewall 115 should not be too small, and should not be too large. If the thickness of the second sidewall 115 is too small, the effect of the second sidewall 115 as an etching mask is easily reduced, and the subsequent processes further include: the channel layer 113 in the bottom channel stack is laterally etched, and the second side wall 115 is easily consumed due to the fact that the thickness of the second side wall 115 is too small, so that the second side wall 115 is difficult to play a corresponding protection role; if the thickness of the second sidewall 115 is too large, the second sidewall 115 is difficult to remove subsequently, which is easy to increase process risk and reduce process compatibility, and the thickness of the second sidewall 115 is too large, the width of the bottom channel stack is correspondingly large, the time spent for subsequently and laterally etching the channel layer 113 in the bottom channel stack is also correspondingly too long, which is easy to reduce production capacity. For this reason, in the present embodiment, the thickness of the second sidewall spacers 115 is 3nm to 10 nm.

In this embodiment, the step of forming the second sidewall spacers 115 includes: forming a sidewall material layer (not shown) conformally covering the top and sidewalls of the dummy gate structure 130 and the substrate; and removing the side wall material layer on the top 130 of the pseudo gate structure and the substrate, and using the remaining side wall material layer as a second side wall 115.

In this embodiment, the sidewall material layer is formed by using an atomic layer deposition process. The atomic layer deposition process has good gap filling performance and step coverage capability, so that the conformal coverage capability of the side wall material layer is improved, and the atomic layer deposition process comprises multiple atomic layer deposition cycles to form a film layer with required thickness, thereby being beneficial to improving the thickness uniformity of the side wall material layer and accurately controlling the thickness of the second side wall 115.

In the embodiment, the side wall material layers on the top 130 of the dummy gate structure and the substrate are removed by using a maskless etching process, so that the process steps are simple, and the process cost is low. Specifically, the second sidewall 115 is formed by etching the sidewall material layer by an anisotropic dry etching process.

In this embodiment, the process of etching the first channel stack 114a exposed by the second sidewall 115 is the same as the process of etching the second channel stack 114b exposed by the dummy gate structure 130, and is not repeated herein.

In this embodiment, the number of the channel stacks 114 is two, so that only one second sidewall 115 is formed. In other embodiments, when the number of the channel stacks is greater than or equal to three, the number of times of forming the second side wall and etching the channel stack is correspondingly adjusted according to the number of the channel stacks.

As shown in fig. 6, the channel layer 113 in the underlying channel stack 114d is laterally etched in a direction perpendicular to the sidewalls of the dummy gate structure 120.

The channel layer 113 in the bottom channel stack 114d is made to differ in width from the channel layer 113 in the top channel stack 114c by laterally etching the channel layer 113 in the bottom channel stack 114d to set back the ends of the channel layer 113 in the bottom channel stack 114 d.

Specifically, the channel layer 113 in the bottom channel stack 114d is etched by an isotropic etching process, so that the channel layer 113 in the bottom channel stack 114d can be laterally etched in a direction perpendicular to the sidewall of the dummy gate structure 120.

In this embodiment, the channel layer 113 exposed by the bottom channel stack 114d is laterally etched by an isotropic dry etching process. The dry etching process has good process controllability and etching uniformity, and is easy to ensure that the transverse etching amount of the channel layer 113 meets the process requirements. Specifically, isotropic etching can be achieved by adjusting the process pressure and bias voltage of the dry etching process, for example: and a dry etching process with high process pressure and low bias voltage is adopted.

In this embodiment, the channel layer 113 is made of silicon, and therefore, the main etching gas of the isotropic dry etching process may be a fluorine-based gas, for example: CF (compact flash)₄、CHF₃Or C₂F₆And the like. In other embodiments, when the channel layer is SiGe, a wet etching process may be used to laterally etch the channel layer in the underlying channel stack.

In other embodiments, the channel layer in the bottom channel stack may be etched by a wet etching process according to actual process requirements. The wet etching process is simple to operate and low in process cost.

In this embodiment, after laterally etching the channel layer 113 in the bottom channel stack 114d, the method further includes: as shown in fig. 6, the sacrificial layer 112 in the bottom channel stack 114d is laterally etched in a direction perpendicular to the sidewalls of the dummy gate structure 130.

By laterally etching the sacrificial layer 112 in the bottom channel lamination layer 114d, the end of the remaining sacrificial layer 112 in the bottom channel lamination layer 114d is retracted from the end of the channel layer 113 in the bottom channel lamination layer 114d, and after the first portion of the gate structure is formed at the position of the remaining sacrificial layer 112, the end of the first portion of the gate structure does not protrude out of the channel layer 113 located above the first portion of the gate structure, so that the problems of large parasitic capacitance, leakage current and the like caused by too close distance between the gate structure and the source-drain doped layer are favorably prevented, and the performance of the semiconductor structure is correspondingly improved.

In this embodiment, a wet etching process is used to laterally etch the sacrificial layer 112 in the bottom channel stack 114 d. The wet etching process has a characteristic of isotropic etching, so that the sacrificial layer 112 can be laterally etched in a direction perpendicular to the sidewalls of the dummy gate structure 130.

In this embodiment, the sacrificial layer 112 is made of SiGe, and the channel layer 113 is made of Si; thus, the sacrificial layer 112 is laterally etched by the HCl vapor. The etching rate of the HCl vapor to the SiGe material is far greater than that to the Si material, so that the sacrificial layer 112 is etched by the HCl vapor, the probability of loss of the channel layer 113 can be effectively reduced, and the device performance can be improved.

In other embodiments, when the channel layer and the fin portion are made of SiGe and the sacrificial layer is made of Si, the etching solution used in the wet etching process is a tetramethylammonium hydroxide (TMAH) solution. The difference between the etching rate of the tetramethylammonium hydroxide solution to the Si material and the etching rate of the SiGe material is larger, so that the probability of loss of the channel layer can be effectively reduced by etching the sacrificial layer by adopting the tetramethylammonium hydroxide solution.

As shown in fig. 7, the second sidewalls 115 are removed, exposing the sidewalls of the top channel stack 114 c. Thereby preparing for the subsequent formation of source-drain doped layers.

In this embodiment, the second sidewalls 115 are removed by a wet etching process. The wet etching process is easy to realize larger etching selection ratio, thereby reducing the loss of other film layer structures. Specifically, a phosphoric acid solution may be used for the wet etching process.

In other embodiments, according to the actual process, a dry etching process may also be used to remove the second sidewall.

Referring to fig. 8, in this embodiment, after removing the second sidewall 115, the method further includes: the sacrificial layer 112 in the top channel stack 114c is laterally etched in a direction perpendicular to the sidewalls of the dummy gate structure 130.

The sacrificial layer 112 in the top channel lamination layer 114c is laterally etched, so that the end of the sacrificial layer 112 in the top channel lamination layer 114c is retracted from the end of the channel layer 113 in the top channel bottom layer 114c, and after the first part of the gate structure is formed at the position of the remaining sacrificial layer 112, the end of the first part of the gate structure does not protrude out of the channel layer 113 above the first part of the gate structure, thereby being beneficial to preventing the gate structure from being too close to the source-drain doping layer to generate the problems of larger parasitic capacitance, leakage current and the like, and correspondingly improving the performance of the semiconductor structure.

In this embodiment, the sacrificial layer 112 is laterally etched by a wet etching process. The process steps for laterally etching the sacrificial layer 112 in the top channel stack 114c are the same as the process steps for laterally etching the sacrificial layer 112 in the bottom channel stack 114d, and are not described herein again.

It should be noted that, in the process of laterally etching the sacrificial layer 112 in the top channel stack 114c, the sacrificial layer 112 in the bottom channel stack 114d is also laterally etched; after the sacrificial layer 112 in the top channel stack 114c is laterally etched, the sidewall of the sacrificial layer 112 in the bottom channel stack 114d is located at one side of the sidewall of the top channel stack 114 close to the dummy gate structure 130.

Referring to fig. 9, source drain doped layers 140 are formed in the recess 150 (shown in fig. 8).

In this embodiment, the source-drain doping layer 140 is formed by epitaxy and doping processes, and the source-drain doping layer 140 includes a stress layer. When the all-around gate transistor is a PMOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the stress layer are P-type ions; when the all-around gate transistor is an NMOS transistor, the stress layer is made of Si or SiC, and the doped ions in the stress layer are N-type ions.

In this embodiment, the step of forming the source-drain doping layer 140 includes: and filling a stress material into the groove 150 by adopting a selective epitaxial process to form a stress layer, and in the process of forming the stress layer, self-doping ions of corresponding types in situ to form the source-drain doping layer 140.

In this embodiment, the top of the source-drain doping layer 140 is higher than the top of the channel stack layer 114, and the source-drain doping layer 140 also covers a part of the sidewall of the first sidewall 122. In other embodiments, the top of the source and drain doped layers may also be flush with the top of the channel stack.

Referring to fig. 10, the dummy gate structure 130 is removed, forming a gate opening 160 exposing the channel stack 114.

The dummy gate structure 130 is removed to provide a spatial location for a subsequently formed gate structure, and simultaneously expose the channel stack 114, which provides a process basis for a subsequent removal of the sacrificial layer 112 in the channel stack 114.

In this embodiment, the step of forming the gate opening 160 includes: forming an interlayer dielectric layer 124 on the substrate exposed by the dummy gate structure 130 (as shown in fig. 10), wherein the interlayer dielectric layer 124 exposes the top of the dummy gate structure 130; dummy gate structure 130 is removed and a gate opening 160 is formed in interlevel dielectric layer 124 exposing channel stack 114.

Interlevel dielectric layer 124 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the interlayer dielectric layer 124 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

Specifically, the step of forming the interlayer dielectric layer 124 includes: forming a dielectric material layer (not shown) on the substrate 111 exposed by the dummy gate layer 120, wherein the dielectric material layer covers the top of the dummy gate layer 120; and performing planarization treatment on the dielectric material layer, removing the dielectric material layer higher than the top of the dummy gate layer 120, and using the residual dielectric material layer after the planarization treatment as the interlayer dielectric layer 124.

In this embodiment, the dielectric material layer covers the top of the gate mask layer 123 (as shown in fig. 9), so that the gate mask layer 123 is also removed during the process of forming the interlayer dielectric layer 124.

In this embodiment, the dummy gate layer 120 crosses over the channel stack 114 and covers a portion of the top and a portion of the sidewall of the channel stack 114, so that after the dummy gate layer 120 and the gate oxide layer 121 at the bottom of the dummy gate layer 120 are removed, the gate opening 160 exposes at least a portion of the top and a portion of the sidewall of the channel stack 114. Specifically, after forming the gate opening 160, the channel stack 114 protrudes from the bottom of the gate opening 160, and the gate opening 160 exposes sidewalls of the remaining sacrificial layer 112 along a direction perpendicular to the extending direction of the fin 110.

Referring to fig. 11, the sacrificial layer 112 in the channel stack 114 is removed, and a through trench 170 is formed, where the through trench 170 is surrounded by the adjacent channel layer 113 and the source-drain doping layer 140, or the through trench 170 is surrounded by the substrate, the channel layer 113 adjacent to the substrate, and the source-drain doping layer 140, and the through trench 170 is communicated with the gate opening 160.

Sacrificial layer 112 in channel stack 114 is removed to form through trenches 170 that provide spatial locations for subsequent gate structure formation.

In this embodiment, the sacrificial layer 112 exposed by the gate opening 160 is removed by wet etching. Specifically, the channel layer 113 is made of Si, and the sacrificial layer 112 is made of SiGe, so that the sacrificial layer 112 exposed by the gate opening 160 is removed by HCl vapor, and the etching rate of the sacrificial layer 112 by the wet etching process is much greater than that of the channel layer 113 and the fin 110.

It should be noted that, since the sacrificial layer 112 is removed after the source-drain doping layer 140 is formed, after the sacrificial layer 112 exposed by the gate opening 160 is removed, along the extending direction of the fin 110, two ends of the channel layer 113 are connected to the source-drain doping layer 140 and suspended in the gate opening 160, so as to provide a foundation for the subsequent gate structure to surround the channel layer 113.

In this embodiment, after removing the sacrificial layer 112, the channel layers 113 are disposed at intervals, and all the channel structure layers 12 and 113 form a channel structure layer 125, and the channel structure layer 125 is located on the fin 110 and disposed at intervals with the fin 110.

Referring to fig. 12 to 13, an inner wall layer 117 is formed on the sidewalls of the source-drain doping layer 140 exposed by the through trench 170 (as shown in fig. 13).

The inner wall layer 117 serves as an inner sidewall (inner spacer) and is used for covering a sidewall of a gate structure formed in the through groove 170 subsequently, the gate structure formed in the through groove 170 subsequently serves as a first part of the gate structure, the inner wall layer 117 is located between the first part of the gate structure and the source-drain doping layer 140, and the distance between the first part of the gate structure and the source-drain doping layer 140 is increased, so that parasitic capacitance between the gate structure and the source-drain doping layer 140 is reduced, and the performance of the semiconductor structure is improved.

In addition, in the embodiment, the inner wall layer 117 is formed after the dummy gate structure 130 and the sacrificial layer 112 are removed, so that the inner wall layer 117 can be formed on the sidewalls of the source-drain doping layers 120 exposed by all the through grooves 170 in the same step, which is beneficial to simplifying the process flow and simplifying the process steps.

Thus, the material of the inner wall layer 117 is a dielectric material. In this embodiment, the inner wall layer 117 is made of silicon oxide, which is a commonly used dielectric material in a semiconductor process, and is beneficial to reducing process cost and improving process compatibility. In other embodiments, the material of the inner wall layer may also be silicon nitride, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material. Wherein, the low-k dielectric material refers to a dielectric material with a relative dielectric constant of more than or equal to 2.6 and less than or equal to 3.9, and the ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant of less than 2.6.

In this embodiment, the step of forming the inner wall layer 117 includes: as shown in fig. 12, forming an inner wall material layer 116 conformally covering the source-drain doping layer 140 exposed by the via groove 170, the channel layer 113 and the substrate surface; as shown in fig. 13, the channel layer 113 and the inner wall material layer 116 on the substrate surface are removed, and the remaining inner wall material layer 116 on the sidewalls of the source-drain doping layer 140 exposed by the through-trench 170 serves as the inner wall layer 117.

In this embodiment, the inner wall material layer 116 is formed by an atomic layer deposition process. The atomic layer deposition process has good gap filling performance and step coverage capability, so that conformal coverage capability of the inner wall material layer 116 is improved, and the atomic layer deposition process comprises multiple atomic layer deposition cycles to form a film layer with a required thickness, thereby being beneficial to improving thickness uniformity of the inner wall material layer 116 and accurately controlling the thickness of the inner wall layer 117.

The ald process has a better conformal coverage capability, and therefore, in the embodiment, in the step of forming the inner wall material layer 116, the inner wall material layer 116 is further formed on the sidewall of the gate opening 160 and the sidewall of the channel layer 113 exposed by the gate opening 160.

Accordingly, after removing the channel layer 113 and the inner wall material layer 116 of the substrate surface, an inner wall layer 117 is also formed on the sidewalls of the gate opening 170. The gate structure formed in the gate opening 170 is used as the second portion of the gate structure, and the inner wall layer 117 is also located on the sidewall of the second portion of the gate structure, so that the distance between the second portion of the gate structure and the source-drain doping layer 140 can be increased correspondingly, and the parasitic capacitance between the gate structure and the source-drain doping layer 140 can be reduced.

The thickness of the inner wall layer 117 should not be too small or too large. If the thickness of the inner wall layer 117 is too small, it is easy to make the inner wall layer 117 difficult to perform a corresponding isolation function; if the thickness of the inner wall layer 117 is too large, the volume of the gate structure formed in the through trench 170 is too small, which may affect the effective channel length of the device and thus the performance of the semiconductor device. For this reason, in the present embodiment, the thickness of the inner wall layer 117 is 1nm to 10 nm.

In this embodiment, a remote plasma etch (remote plasma etch) process is used to remove the channel layer 113 and the inner wall material layer 116 on the substrate surface.

The remote plasma etching process is an etching process which utilizes a plasma source to form plasma outside an etching reaction zone and then introduces the plasma into the etching reaction zone through air flow, an electric field, a magnetic field and the like so as to etch a material to be etched. In the remote plasma etching process, the distance between the ionization region and the etching reaction region of the plasma is far, which is beneficial to obtaining better space uniformity, or more suitable ion and neutral component proportion and different free radical proportion are obtained, thereby being beneficial to improving the etching effect of the plasma etching process.

Specifically, in this embodiment, in the step of the remote plasma etching process, under the carrying of the gas flow, the plasma can drill into the through-groove 170 to etch the surface of the channel layer 113 and the inner wall material layer 116 on the substrate, and because the gas flow has a slow flowing speed along the direction perpendicular to the side wall of the through-groove 170, the etching rate of the remote plasma etching process on the inner wall material layer 116 on the side wall of the source/drain doping layer 140 exposed by the through-groove 170 is also slow, so that after the inner wall material layer 116 on the side wall of the source/drain doping layer 140 and on the side wall of the gate opening 160 exposed by the through-groove 170 is etched away, a part of the thickness of the inner wall material layer 116 on the side wall of the source/drain doping layer 140 and on the side.

In this embodiment, the material of the inner wall material layer 116 is silicon oxide, and therefore, the main etching gas for the remote plasma processing includes fluorine-based gases, such as: CF (compact flash)₄、NF₃Or SF₆And the like.

The bias voltage of the remote plasma etching process is not too small and not too large. If the bias voltage is too small, the etching rate is easy to reduce; if the bias voltage is too large, the etching rate is easy to be too fast, and further the isotropic etching effect of the remote plasma etching process is easy to reduce. For this reason, in the present embodiment, the bias voltage of the remote plasma etching process is 30 v to 500 v.

The process pressure of the remote plasma etching process is not too low or too high. If the process pressure is too low, the density of the plasma is easily reduced, and further the etching efficiency is easily reduced; if the process pressure is too high, the stability and uniformity of the etching process are easily reduced. For this reason, in the present embodiment, the process pressure of the remote plasma etching process is 0.1Torr to 760 Torr.

Referring to fig. 14, a gate structure 135 is formed in the gate opening 160 and the trench 170 formed with the inner wall layer 117.

In this embodiment, the gate opening 160 is communicated with the through groove 170, so that after the gate structure 135 is formed in the gate opening 160, the gate structure 135 is further located in the through groove 170, the gate structure 135 can surround the channel layer 113 from the periphery of the channel layer 113 exposed in the gate opening 160, and further cover the top of the fin 110, that is, the gate structure 135 can cover the upper surface, the lower surface, and the side surfaces of the channel layer 113 and part of the top and part of the side walls of the fin 110. Specifically, gate structure 135 spans channel structure layer 125.

In the present embodiment, the gate structure 135 between the substrate and the channel layer 113 adjacent to the substrate, and the gate structure 135 between the adjacent channel layers 113 are the gate structure first portion 131, and the remaining gate structure 135 is the gate structure second portion 132.

An inner wall layer 117 is further formed between the first portion 131 of the gate structure and the source-drain doping layer 140, so that the distance between the first portion 131 of the gate structure and the source-drain doping layer 140 is increased, the parasitic capacitance between the gate structure 135 and the source-drain doping layer 140 is correspondingly reduced, and the performance of the semiconductor structure is further improved.

In this embodiment, the gate structure 135 is a metal gate structure, and includes a gate dielectric layer (not shown) and a gate electrode (not shown) on the gate dielectric layer. Specifically, the gate dielectric layer covers the upper surface, the lower surface, and the side surfaces of the channel layer 113, and also covers a portion of the top and a portion of the sidewalls of the fin 110.

In this embodiment, the gate dielectric layer is made of a high-k dielectric material; wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the gate dielectric layer is HfO₂. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO₂HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al₂O₃And the like.

In this embodiment, the gate electrode is made of W. In other embodiments, the material of the gate electrode may also be a conductive material such as Al, Cu, Ag, Au, Pt, Ni, or Ti.

In this embodiment, in the direction along which the top of the gate structure 135 points to the substrate, the ends of the channel layers 113 are sequentially retracted, the lengths of the channel layers 113 are all different, and the widths of the channel layers 113 covered by the gate structure 135 are also sequentially different, so that each channel layer 113 in the transistor with the fully-surrounded gate structure has different turn-on voltages, and therefore, when the device works, the mode of applying voltages with different sizes to the transistor is enabled, thereby achieving the effect of turning on different channel layers 113 in the transistor, and further meeting the requirement of applying the transistor with the fully-surrounded gate structure to circuits with different working voltages.

Fig. 15 to 27 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: in the step of providing the substrate, the number of the channel lamination layers is more than or equal to three, and the steps of etching the channel lamination layers on the two sides of the pseudo gate structure are different.

Referring to fig. 15, a substrate (not labeled) is provided on which a plurality of channel stacks 214 are sequentially formed, each channel stack 214 including a sacrificial layer 212 and a channel layer 213 on the sacrificial layer 212.

In this embodiment, the number of channel stacks 214 is greater than or equal to three. Specifically, the number of the channel stacks 214 is three in the present embodiment. For a detailed description of the substrate and the channel stack 214, reference may be made to the description of the foregoing embodiments, and no further description is provided herein.

With continued reference to fig. 15, a dummy gate structure 230 is formed across the channel stack 214, the dummy gate structure 230 covering a portion of the top and a portion of the sidewalls of the channel stack 214. For a detailed description of the dummy gate structure 230, reference may be made to the related description of the foregoing embodiments, and further description is omitted here.

Referring to fig. 16 to 27, the channel stacks 214 on both sides of the dummy gate structure 230 are etched, such that the channel layers 213 are sequentially recessed from the ends of the channel layers 214 in a direction pointing to the substrate along the top of the dummy gate structure 230, and the remaining channel stacks 214 and the substrate enclose a recess 250 (as shown in fig. 27).

In this embodiment, the number of the channel stacks 214 is greater than or equal to three, and the step of etching the channel stacks 214 on both sides of the dummy gate structure 230 includes:

referring to fig. 16, one of the channel stacks 214 exposed by the dummy gate structure 230 is etched using the dummy gate structure 230 as a mask, and the remaining channel stack 214 after etching is used as an upper channel stack (not shown). Thereby preparing for the subsequent formation of the side wall on the upper channel lamination.

In this embodiment, the first sidewall 222 is formed on the sidewall of the dummy gate structure 230, so that the exposed channel stack 214 of the dummy gate structure 230 is etched by using the first sidewall 222 and the dummy gate structure 230 as masks.

In this embodiment, an anisotropic dry etching process is used to etch the exposed channel stack 214 of the dummy gate structure 230. For a detailed description of the process for etching the exposed one channel stack 214 of the dummy gate structure 230, reference may be made to the related description of the previous embodiment for etching the exposed second channel stack of the dummy gate structure.

Referring to fig. 17 to 20, the pretreatment is performed at least twice, and the pretreatment includes: forming a second sidewall 215 on a sidewall of the upper channel stack; etching one channel stack 214 exposed by the second sidewall 215 adjacent to and below the upper channel stack 214, and using the remaining etched channel stack 214 as a lower channel stack (not shown); in the direction along the substrate toward the top of the dummy gate structure 230, the upper channel stack farthest from the substrate is the top channel stack 214a (as shown in fig. 20), and the lower channel stack 214 closest to the substrate is the bottom channel stack 214b (as shown in fig. 20).

By performing the pretreatment at least twice, a plurality of second sidewalls 215 are sequentially formed on the sidewalls of all the remaining channel stacks 214 except for the bottom channel stack 214b, so that each second sidewall 215 can protect the upper channel stack covered by the second sidewall 215 in the subsequent process step of laterally etching the lower channel stack 214, thereby making the number of times of etching different channel layers 213 different, and further achieving the effect of different widths of different channel layers 213.

The second sidewall 215 is used as an etching mask for subsequent etching of the lower channel stack, and the second sidewall 215 also protects sidewalls of the upper channel stack adjacent to the lower channel stack during subsequent etching of the lower channel stack. In order to ensure that the second sidewall 215 can perform a corresponding protection function, in this embodiment, the thickness of the second sidewall 115 is also 3nm to 10 nm.

In this embodiment, the second sidewall 215 is made of a different material than the first sidewall 222, thereby facilitating subsequent removal of the second sidewall 215. For a detailed description of the material of the second sidewall 215, reference may be made to the related description of the material of the second sidewall in the foregoing embodiments, and details are not repeated herein.

In this embodiment, the number of the channel stacks 214 is three, and thus, the preprocessing is performed twice. Accordingly, after performing the pretreatment twice, two second sidewalls 215(215a and 215b) are sequentially formed.

In this embodiment, the two second sidewalls 215 are made of different materials, which is correspondingly beneficial to sequentially removing one second sidewall 215 in the following process.

In other embodiments, when the number of the channel stacks is greater than three, the number of times of preprocessing is reduced by one, and the number of the formed second side walls is the same as the number of times of preprocessing. Correspondingly, in order to facilitate the subsequent sequential removal of one second side wall, the materials of the adjacent second side walls are different.

In this embodiment, the process steps for forming the second sidewall 215 are the same as those in the previous embodiments, and are not described again.

In this embodiment, the process of etching the channel stack 214 exposed by the second sidewall 215, adjacent to and below the upper channel stack, is the same as the process of etching the channel stack 214 exposed by the dummy gate structure 230, and is not described herein again.

Referring to fig. 21, after performing the pre-treatment at least twice, the exposed channel layer 213 in the bottom channel stack 214b is laterally etched in a direction perpendicular to the sidewalls of the dummy gate structure 230.

In this embodiment, after the channel layer 213 in the bottom channel stack 214b is etched, the end of the channel layer 213 in the bottom channel stack 214b is recessed compared to the channel layer 213 in the upper channel stack adjacent to the bottom channel stack 214b, so that after the sidewall 215 on the sidewall of the upper channel stack is subsequently removed and the exposed channel layer 213 is etched, the end of the remaining channel layer 213 in the bottom channel stack 214b is still recessed compared to the channel layer 213 in the remaining upper channel stack.

In this embodiment, the channel layer 213 in the bottom channel stack 214b is etched using an isotropic etching process. The process of etching the channel layer 213 in the underlying channel stack 214b is the same as in the previous embodiment.

In this embodiment, the number of the channel stacks 214 is greater than or equal to three, and after the channel layer 213 in the exposed bottom channel stack 214b is laterally etched, the method further includes: as shown in fig. 22, the exposed sacrificial layer 212 in the bottom channel stack 214b is laterally etched in a direction perpendicular to the sidewalls of the dummy gate structure 230.

The exposed sacrificial layer 212 in the bottom channel lamination 214b is laterally etched, so that the end of the remaining sacrificial layer 212 in the bottom channel lamination 214b is retracted compared with the end of the channel layer 213 in the bottom channel lamination 214b, and after a first part of the gate structure is formed at the position of the remaining sacrificial layer 212, the end of the first part of the gate structure does not protrude out of the channel layer 213 above the first part of the gate structure, thereby being beneficial to preventing the gate structure from being too close to a source-drain doped layer to generate the problems of large parasitic capacitance, leakage current and the like, and improving the performance of the semiconductor structure.

In this embodiment, a wet etching process is used to laterally etch the sacrificial layer 212 in the bottom channel stack 214 b. The process of laterally etching the sacrificial layer 212 in the underlying channel stack 214b is the same as in the previous embodiment.

Referring to fig. 23 to 25, after laterally etching the exposed channel layer 213 in the underlying channel stack 214b, a lateral etching process is performed at least once, and the lateral etching process includes: removing a second sidewall 215 to expose a sidewall of the upper channel stack adjacent to the lower channel stack; the exposed channel layer 213 is laterally etched in a direction perpendicular to the sidewalls of the dummy gate structure 230.

By sequentially removing one second side wall 215 and laterally etching the exposed channel layer 213, the etched times of each channel layer 213 are different in the direction pointing to the top of the dummy gate structure 230 along the substrate, so that the etched times of the channel layer 213 closer to the substrate are more, the etched amount of the channel layer 213 closer to the substrate is more, and the end portions of the channel layer 213 are sequentially retracted in the direction pointing to the substrate along the top of the dummy gate structure 230.

For example, the step of the lateral etching process includes: as shown in fig. 23, the second sidewalls 215b on the sidewalls of the upper channel stack adjacent to the bottom channel stack 214b are removed (as shown in fig. 22); as shown in fig. 24, the exposed channel layer 213 is laterally etched in a direction perpendicular to the sidewalls of the dummy gate structure 230. Specifically, the exposed channel layer 213 in the bottom channel stack 214b and the channel layer 213 in the upper channel stack adjacent to the bottom channel stack 214b are laterally etched.

In this embodiment, a wet etching process is used to remove one of the second sidewalls 215. The process of removing one second sidewall 215 is the same as that of the second sidewall in the previous embodiment, and is not described herein again.

In this embodiment, the process of laterally etching the exposed channel layer 213 is the same as the process of etching the channel layer 213 in the bottom channel stack 214b, and is not described herein again.

In this embodiment, the number of the channel stacks 214 is three, and therefore, the number of times of performing the lateral etching process is one. In other embodiments, when the number of the channel stacks is greater than three, the number of times of performing the lateral etching process is correspondingly reduced by two.

In the step of performing the lateral etching process, after laterally etching the exposed channel layer 213 in a direction perpendicular to the sidewall of the dummy gate structure 230, the method further includes: the sacrificial layer 212 in the upper channel stack is etched laterally in a direction perpendicular to the sidewalls of the dummy gate structure 230.

For example: as shown in fig. 25, after the exposed channel layer 213 in the bottom channel stack 214b is laterally etched, the sacrificial layer 212 in the upper channel stack adjacent to the bottom channel stack 214b is laterally etched in a direction perpendicular to the sidewalls of the dummy gate structure 230.

In the step of performing the lateral etching process, the sacrificial layer 212 in the upper channel stack is laterally etched along a direction perpendicular to the sidewall of the dummy gate structure 230, so that the end of the sacrificial layer 212 in the upper channel stack is retracted from the end of the channel layer 213 in the upper channel stack, and then the first portion of the gate structure is formed at the position of the sacrificial layer 212, and the end of the first portion of the gate structure does not protrude out of the channel layer 213 located above the first portion of the gate structure, thereby being beneficial to preventing the gate structure from generating problems of large parasitic capacitance, large leakage current and the like due to being too close to the source-drain doped layer, and correspondingly improving the performance of the semiconductor structure.

In this embodiment, the process step of laterally etching the sacrificial layer 212 in the upper channel stack is the same as the process of laterally etching the sacrificial layer 212 in the bottom channel stack 214b, and is not described herein again.

Referring to fig. 26, after at least one lateral etching process, the second sidewalls 215a on the sidewalls of the top channel stack 214a are removed (as shown in fig. 25). Thereby preparing for the subsequent formation of source-drain doped layers.

In this embodiment, the second sidewall 215a on the sidewall of the top channel stack 214a is removed by a wet etching process. The process of removing the second sidewall 215a is the same as the process of removing the second sidewall in the previous embodiment, and is not repeated herein.

It should be noted that after removing the second sidewall 215 on the sidewall of the top channel stack 214a, the method further includes: as shown in fig. 27, the sacrificial layer 212 in the top trench stack 214a is etched laterally in a direction perpendicular to the sidewalls of the dummy gate structure 230.

In this embodiment, the process of laterally etching the sacrificial layer 212 in the top channel stack 214a is the same as the previous embodiment, and is not described herein again.

The subsequent process steps are the same as those in the previous embodiment, and are not described herein again.

Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 28, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate (not labeled); a channel structure layer 425 on the substrate and spaced apart from the substrate, wherein the channel structure layer 425 includes a plurality of channel layers 413 spaced apart from each other, and ends of the channel layers 413 are sequentially recessed along a direction from a top of the channel structure layer 425 to the substrate; a gate structure 435 spanning the channel structure layer 425, the gate structure 435 overlying a portion of the top of the substrate and surrounding the channel layer 413, the gate structure 435 between the substrate and the channel layer 413 adjacent to the substrate, and the gate structure 435 between adjacent channel layers 413 being a gate structure first portion 431, the remaining gate structure 435 being a gate structure second portion 432; a source-drain doped layer located in the channel structure layer 425 at both sides of the gate structure 435; and the inner wall layer is positioned between the first part 431 of the grid structure and the source-drain doping layer.

By sequentially retracting the ends of the channel layers 413 in the direction pointing to the substrate along the top of the channel structure layer 425, the lengths of the channel layers 413 are different, the channel layer 413 covered by the gate structure 435 is used as a channel region, and the lengths of the channel regions are different, so that each channel layer 413 in the formed transistor with the fully-surrounding gate structure has different starting voltages, and therefore, when the device works, the effect of starting different channel layers 413 in the transistor can be realized by applying voltages with different magnitudes to the transistor, and the requirement that the transistor with the fully-surrounding gate structure is applied to circuits with different working voltages is met.

The inner wall layer 417 is located between the first portion 431 of the gate structure and the source-drain doping layer 440, and increases the distance between the first portion 431 of the gate structure and the source-drain doping layer 440, so that the parasitic capacitance between the first portion 431 of the gate structure and the source-drain doping layer 440 is reduced, and the performance of the semiconductor structure is improved.

The substrate provides a process platform for forming the transistor with the fully-enclosed gate structure. In this embodiment, the base is a three-dimensional structure, and includes a substrate 400 and a fin portion 410 protruding from the substrate 400. In other embodiments, when the base is a planar structure, the base comprises only the substrate, respectively.

In this embodiment, the substrate 400 is a silicon substrate. In this embodiment, the material of the fin 410 is the same as that of the substrate 400, and the material of the fin 410 is silicon. In other embodiments, the fin may be of a different material than the substrate.

The fin 410 exposes a portion of the substrate 400, enabling the formation of an isolation structure 411.

Therefore, in this embodiment, the semiconductor structure further includes: an isolation structure 411 is located on the substrate 400 where the fin 410 is exposed. Isolation structures 411 are used to isolate adjacent devices. In this embodiment, the isolation structure 411 is made of silicon oxide. In other embodiments, the isolation structure may be made of other insulating materials such as silicon nitride or silicon oxynitride.

In this embodiment, the top of the isolation structure 411 is flush with the top of the fin 410, thereby preventing the fin 410 from acting as a channel.

The channel structure layer 425 is on the fin 410 and spaced apart from the fin 410, and the channel structure layer 425 includes at least two channel layers 413 spaced apart, thereby enabling the gate structure 435 to surround the channel layers 413.

The channel of the all-around gate transistor is located within the channel structure layer 425 (i.e., the channel layer 413). In this embodiment, the material of the channel layer 413 is the same as the material of the fin 410, and the material of the channel layer 413 is Si. In other embodiments, when the all-around gate transistor is a PMOS transistor, a SiGe channel technology is usually adopted to improve the performance of the PMOS transistor, and accordingly, the fin and the channel layer are both made of SiGe.

In the present embodiment, the channel structure layer 425 includes two channel layers 413 disposed at intervals. In other embodiments, the number of channel layers may also be greater than or equal to three, depending on the actual process requirements.

It should be noted that the distance of the end of the channel layer 413 is not too small, nor too large. If the retraction distance of the end of the channel layer 413 is too small, the difference of the starting voltage of each channel layer 413 is relatively small when the device works, and the effect of distinguishing different starting voltages is difficult to achieve; if the distance of the end of the channel layer 413 is too large, when the number of the channel layers 413 is large, the width of the channel layer 413 close to the substrate is too small, which is easy to increase the process risk, and also easy to affect the effective channel length of the device, and further the performance of the device. For this reason, in the present embodiment, the end of the channel layer 413 is recessed by a distance greater than 0nm and less than or equal to 5 nm.

In this embodiment, the gate structure 435 crosses the channel structure layer 425, and the gate structure 435 surrounds the channel layer 413 and also covers a portion of the top of the fin 410, i.e., the gate structure 435 covers the upper surface, the lower surface, and the side surfaces of the channel layer 413 and a portion of the top of the fin 410.

In this embodiment, the gate structure 435 is a metal gate structure, and the gate structure 435 includes a gate dielectric layer (not shown) and a gate electrode (not shown) on the gate dielectric layer. Since the channel of the fully-wrapped-gate transistor is located within the channel layer 413 and the fin 410, the gate dielectric layer covers the upper surface, the lower surface, and the sides of the channel layer 413 and also covers a portion of the top of the fin 410.

In this embodiment, the gate dielectric layer is made of HfO₂The material of the gate electrode is W.

In the present embodiment, the gate structure 435 between the substrate and the channel layer 413 adjacent to the substrate, and the gate structure 435 between the adjacent channel layers 413 are the gate structure first portion 431, and the remaining gate structure 435 is the gate structure second portion 432.

In this embodiment, in a direction in which the top of the gate structure 435 points to the substrate, the end portions of the first portions 431 of the gate structure are sequentially retracted, and the width of the first portions 431 of the gate structure is smaller than the width of the channel layer 413 adjacent to the first portions 431 of the gate structure and located above the first portions 431 of the gate structure, so that the end portions of the first portions 431 of the gate structure do not protrude out of the channel layer 413 located above the first portions 431 of the gate structure, thereby preventing the first portions 431 of the gate structure and the source-drain doping layer 440 from being too close to each other to generate a large parasitic capacitance, a large leakage current, and other problems, and accordingly improving the performance of the semiconductor structure.

In this embodiment, the semiconductor structure further includes a sidewall spacer 422 on the sidewall of the second portion 432 of the gate structure. The sidewall spacers 422 are used for protecting the sidewalls of the second portion 432 of the gate structure, and the sidewall spacers 422 are also used for defining a formation region of the source-drain doping layer 440.

The material of the sidewall 422 may be selected from silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall 422 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacers 422 are single-layer structures, and the material of the sidewall spacers 422 is silicon nitride.

In this embodiment, the source-drain doping layer 440 includes a stress layer doped with ions. Specifically, when the all-around gate transistor is a PMOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the stress layer are P-type ions; when the all-around gate transistor is an NMOS transistor, the stress layer is made of Si or SiC, and the doped ions in the stress layer are N-type ions.

In this embodiment, the top of the source-drain doping layer 440 is higher than the top of the channel structure layer 425, and the source-drain doping layer 440 also covers a part of the sidewall 422. In other embodiments, the top of the source-drain doping layer may be flush with the top of the channel structure layer.

The inner wall layer 417 is used as an inner sidewall spacer and is positioned between the first part 431 of the gate structure and the source-drain doping layer 440, so that the distance between the first part 431 of the gate structure and the source-drain doping layer 440 is increased, the parasitic capacitance between the first part 431 of the gate structure and the source-drain doping layer 440 is favorably reduced, and the performance of the device is improved.

In this embodiment, the inner wall layer 417 is further disposed on the sidewall of the second portion 432 of the gate structure, which can correspondingly increase the distance between the second portion 432 of the gate structure and the source-drain doping layer 440, thereby reducing the parasitic capacitance between the gate structure 435 and the source-drain doping layer 440.

Therefore, the material of the inner wall layer 417 is a dielectric material. In this embodiment, the inner wall layer 417 is made of silicon oxide, which is a commonly used dielectric material in a semiconductor process, and is beneficial to reducing process cost and improving process compatibility. In other embodiments, the material of the inner wall layer may also be silicon nitride, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material.

The thickness of the inner wall layer 417 is not necessarily too small, nor too large. If the thickness of the inner wall layer 417 is too small, it is difficult to perform a corresponding isolation function; if the thickness of the inner wall layer 417 is too large, the volume of the first portion 431 of the gate structure is too small, which may easily affect the effective channel length of the device and thus the performance of the semiconductor device. For this reason, the thickness of the inner wall layer 417 in the present embodiment is 1nm to 10 nm.

In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 424 is disposed on the substrate exposed by the gate structure 435, and the interlayer dielectric layer 424 covers the source-drain doping layer 440 and exposes the top of the gate structure 435.

The interlevel dielectric layer 424 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the material of the interlayer dielectric layer 424 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

In this embodiment, the gate structure 435 is formed by a process of forming a high-k gate dielectric layer and then forming a metal gate (high-k metal gate) and the adopted dummy gate structure is a stacked structure before forming the gate structure 435, so the semiconductor structure further includes: a gate oxide layer 421 between the sidewall spacers 422 and the channel structure layer 425. In the process of removing the dummy gate structure to form the gate structure 435, the gate oxide 421 between the sidewall 422 and the channel structure layer 425 is retained under the protection of the sidewall 422.

In this embodiment, the gate oxide layer 421 is made of silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride. In other embodiments, when the adopted dummy gate structure is a single-layer structure, the semiconductor structure may not contain a gate oxide layer.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a plurality of channel lamination layers are sequentially formed on the substrate, and each channel lamination layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer;

forming a dummy gate structure crossing the channel lamination layer, wherein the dummy gate structure covers part of the top and part of the side wall of the channel lamination layer;

etching the channel lamination layers on two sides of the pseudo-gate structure to enable the channel lamination layers to be in the direction pointing to the substrate along the top of the pseudo-gate structure, enabling the end parts of the channel layers to be sequentially retracted, and enabling the residual channel lamination layers and the substrate to form a groove in a surrounding mode;

forming a source drain doping layer in the groove; removing the pseudo gate structure to form a gate opening exposing the channel lamination;

removing the sacrificial layer in the channel lamination to form a through groove, wherein the through groove is surrounded by the adjacent channel layer and the source-drain doping layer, or the through groove is surrounded by the substrate, the channel layer adjacent to the substrate and the source-drain doping layer, and the through groove is communicated with the grid opening;

forming an inner wall layer on the side wall of the source drain doping layer exposed out of the through groove;

and forming a gate structure in the gate opening and the through groove formed with the inner wall layer.

2. The method of forming a semiconductor structure according to claim 1, wherein in the step of providing a substrate, the number of the channel stacks is two, and the channel stacks include a first channel stack and a second channel stack located on the first channel stack;

the step of etching the channel lamination layers on the two sides of the pseudo gate structure comprises the following steps:

etching the second channel lamination layer exposed by the pseudo gate structure by taking the pseudo gate structure as a mask, wherein the second channel lamination layer is left after etching and is used as a top-layer channel lamination layer; forming a side wall on the side wall of the top-layer channel lamination; etching the first channel lamination layer exposed from the side wall, wherein the etched residual first channel lamination layer is used as a bottom layer channel lamination layer;

transversely etching the channel layer in the bottom channel lamination along the direction vertical to the side wall of the pseudo gate structure; removing the side wall and exposing the side wall of the top-layer channel lamination;

alternatively, the first and second electrodes may be,

the number of the channel lamination layers is more than or equal to three, and the step of etching the channel lamination layers on two sides of the pseudo gate structure comprises the following steps:

etching one exposed channel lamination layer of the pseudo gate structure by taking the pseudo gate structure as a mask, wherein the rest channel lamination layer after etching is taken as an upper channel lamination layer;

performing at least two pretreatments, the step of pretreating comprising: forming a side wall on the side wall of the upper-layer channel lamination; etching the side wall to expose a channel lamination which is adjacent to the upper channel lamination and is positioned below the upper channel lamination, and taking the etched residual channel lamination as a lower channel lamination; in the direction of pointing to the pseudo-gate structure along the substrate, the upper-layer channel lamination layer farthest from the substrate is a top-layer channel lamination layer, and the lower-layer channel lamination layer closest to the substrate is a bottom-layer channel lamination layer;

after at least two times of pretreatment, transversely etching the exposed channel layer in the bottom layer channel lamination along the direction vertical to the side wall of the pseudo gate structure;

after the exposed channel layer in the bottom channel lamination is transversely etched, transverse etching treatment is carried out at least once, and the transverse etching treatment comprises the following steps: removing one side wall to expose the side wall of the upper-layer channel lamination layer adjacent to the lower-layer channel lamination layer; transversely etching the exposed channel layer along a direction vertical to the side wall of the pseudo gate structure;

and after at least one time of transverse etching treatment, removing the side wall on the side wall of the top-layer channel lamination.

3. The method of forming a semiconductor structure of claim 2, wherein the number of the channel stacks is two;

after transversely etching the channel layer in the bottom channel lamination and before removing the side wall, the method further comprises the following steps: transversely etching the sacrificial layer in the bottom layer channel lamination layer along the direction vertical to the side wall of the pseudo gate structure;

after removing the side wall, before forming the source-drain doping layer, the method further comprises the following steps: transversely etching the sacrificial layer in the top-layer channel lamination layer along the direction vertical to the side wall of the pseudo gate structure;

alternatively, the first and second electrodes may be,

the number of the channel lamination layers is more than or equal to three, and after the channel layer in the bottom layer channel lamination layer exposed by transverse etching is carried out, the method also comprises the following steps of: transversely etching the exposed sacrificial layer in the bottom layer channel lamination layer along the direction vertical to the side wall of the pseudo gate structure;

in the step of performing the transverse etching treatment, after transversely etching the exposed channel layer along a direction perpendicular to the sidewall of the dummy gate structure, the method further includes: transversely etching the sacrificial layer in the upper channel lamination layer along the direction vertical to the side wall of the pseudo gate structure;

after removing the side wall on the side wall of the top-layer channel lamination, the method further comprises the following steps: and transversely etching the sacrificial layer in the top channel lamination layer along the direction vertical to the side wall of the pseudo gate structure.

4. The method of forming a semiconductor structure of claim 1, wherein the step of forming the inner wall layer comprises: forming a source drain doping layer which conformally covers the exposed through groove, and inner wall material layers of the channel layer and the substrate surface; and removing the channel layer and the inner wall material layer on the surface of the substrate, wherein the residual inner wall material layer on the side wall of the source drain doping layer exposed from the through groove is used as the inner wall layer.

5. The method of forming a semiconductor structure of claim 4, wherein forming the gate opening comprises: forming an interlayer dielectric layer on the substrate exposed out of the pseudo gate structure, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming the gate opening exposing the channel lamination in the interlayer dielectric layer;

in the step of forming the inner wall material layer, the inner wall material layer is further formed on the side wall of the gate opening and the side wall of the channel layer exposed from the gate opening;

and after the inner wall material layers on the surfaces of the channel layer and the substrate are removed, the inner wall layer is also formed on the side wall of the grid opening.

6. The method of claim 4, wherein the inner wall material layer is formed using an atomic layer deposition process.

7. The method of forming a semiconductor structure of claim 4, wherein the inner wall material layer of the channel layer and substrate surface is removed using a remote plasma etch process.

8. The method of forming a semiconductor structure of claim 7, wherein a process parameter of the remote plasma etch processThe number of the components comprises: the etching gas includes: CF (compact flash)₄、NF₃Or SF₆The bias voltage is 30V to 500V, and the process pressure is 0.1Torr to 760 Torr.

9. The method of claim 1, wherein the end of the channel layer is recessed by a distance greater than 0nm and less than or equal to 5 nm.

10. The method for forming the semiconductor structure according to claim 2, wherein in the step of forming the side wall, the thickness of the side wall is 3nm to 10 nm.

11. The method for forming the semiconductor structure according to claim 2, wherein the step of forming the side wall includes: forming a side wall material layer which conformally covers the top and the side wall of the pseudo gate structure and the substrate; and removing the side wall material layers on the top of the pseudo gate structure and the substrate, and taking the rest side wall material layers as the side walls.

12. The method of claim 2, wherein the material of the sidewall spacers comprises silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

13. The method for forming a semiconductor structure according to claim 2, wherein the sidewall spacers are removed by a wet etching process.

14. The method for forming a semiconductor structure according to claim 2, wherein the step of etching the second channel stack exposed by the dummy gate structure, the step of etching the first channel stack exposed by the sidewall, the step of etching the channel stack exposed by the dummy gate structure, and the step of etching the sidewall to expose a channel stack adjacent to and below the upper channel stack is an anisotropic dry etching process.

15. The method of forming a semiconductor structure of claim 2, wherein the process of laterally etching the channel layer in the bottom channel stack, the laterally etched exposed channel layer, is an isotropic dry etching process.

16. A semiconductor structure, comprising:

a substrate;

the channel structure layer is positioned on the substrate and is arranged at intervals with the substrate, the channel structure layer comprises a plurality of channel layers arranged at intervals, and the end parts of the channel layers are sequentially retracted along the direction in which the top of the channel structure layer points to the substrate;

the grid structure stretches across the channel structure layer, the grid structure covers the top of part of the substrate and surrounds the channel layer, the grid structure positioned between the substrate and the channel layer adjacent to the substrate and the grid structure positioned between the adjacent channel layers are first parts of the grid structure, and the rest of the grid structure is second parts of the grid structure;

the source-drain doping layer is positioned in the channel structure layers at two sides of the grid structure;

and the inner wall layer is positioned between the first part of the grid structure and the source-drain doping layer.

17. The semiconductor structure of claim 16, wherein ends of the first portion of the gate structure are sequentially tapered in a direction from a top of the gate structure toward the substrate, and wherein a width of the first portion of the gate structure is less than a width of a channel layer adjacent to and above the first portion of the gate structure.

18. The semiconductor structure of claim 16, wherein the inner wall layer is further located on sidewalls of the second portion of the gate structure.

19. The semiconductor structure of claim 16, wherein the material of the inner wall layer comprises silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material.

20. The semiconductor structure of claim 16, wherein the thickness of the inner wall layer is 1nm to 10 nm.

21. The semiconductor structure of claim 16, wherein an end portion of the channel layer is recessed a distance greater than 0nm and less than or equal to 5 nm.