CN110854194B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN110854194B CN110854194B CN201810947256.1A CN201810947256A CN110854194B CN 110854194 B CN110854194 B CN 110854194B CN 201810947256 A CN201810947256 A CN 201810947256A CN 110854194 B CN110854194 B CN 110854194B
- Authority
- CN
- China
- Prior art keywords
- gate structure
- isolation
- fin
- layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 88
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000002955 isolation Methods 0.000 claims abstract description 257
- 239000000463 material Substances 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 101
- 229910052751 metal Inorganic materials 0.000 claims abstract description 65
- 239000002184 metal Substances 0.000 claims abstract description 65
- 239000003989 dielectric material Substances 0.000 claims abstract description 51
- 230000008569 process Effects 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 239
- 239000011229 interlayer Substances 0.000 claims description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052710 silicon Inorganic materials 0.000 claims description 38
- 239000010703 silicon Substances 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 15
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 10
- 230000009286 beneficial effect Effects 0.000 description 9
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 230000001186 cumulative effect Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000005315 distribution function Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: forming a base including a substrate and a plurality of discrete fins on the substrate; forming a metal gate structure crossing the fin part, wherein the metal gate structure covers part of the top and part of the side wall of the fin part; and forming an isolation gate structure on the substrate between adjacent fin parts along the extending direction of the fin parts, wherein the isolation gate structure is made of dielectric materials. The invention forms an isolation gate structure on the substrate between adjacent fin parts, and the isolation gate structure is made of dielectric material; in the semiconductor process, the isolation gate structure and the metal gate structure crossing the fin parts are usually formed in the same process step, namely the material of the isolation gate structure usually comprises a metal material.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, with the improvement of the density and the integration level of the semiconductor device, the gate size of the planar transistor is also shorter and shorter, the control capability of the conventional planar transistor on the channel current is weakened, a short channel effect occurs, the leakage current is increased, and the electrical performance of the semiconductor device is finally affected.
To better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). The structure of a fin field effect transistor generally includes: the isolation structure (such as a shallow trench isolation structure) is protruded out of the fin portion of the substrate and is located on the substrate, the isolation structure covers part of the side wall of the fin portion, and the top of the isolation structure is lower than the top of the fin portion; a gate structure covering the top and part of the side wall of the fin part; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, as semiconductor device dimensions continue to shrink, the distance between adjacent finfet devices also shrinks. In order to prevent the adjacent fin field effect transistors from being connected (merge), the prior art introduces a manufacturing technology of a single diffusion barrier (single diffusion break, SDB) isolation structure. The single diffusion partition isolation structure is generally distributed in the extending direction along the fin portion, one or more grooves are formed in the fin portion by removing the fin portion of the partial region, and insulating materials are filled in the grooves, so that adjacent remaining fin portions are isolated, leakage current between the adjacent remaining fin portions is reduced, and the single diffusion partition isolation structure can also avoid the problem of bridging (source-drain bridge) between the source region and the drain region.
However, after the single diffusion barrier isolation structure is introduced into the semiconductor structure, the device still has the problem of poor performance.
Disclosure of Invention
The invention solves the problem of providing a semiconductor structure and a forming method thereof, which improve the performance of a device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: forming a base including a substrate and a plurality of discrete fins on the substrate; forming a metal gate structure crossing the fin part, wherein the metal gate structure covers part of the top and part of the side wall of the fin part; and forming an isolation gate structure on the substrate between the adjacent fin parts along the extending direction of the fin parts, wherein the isolation gate structure is made of dielectric materials.
Correspondingly, the invention also provides a semiconductor structure, which comprises: a base comprising a substrate and a plurality of discrete fins located on the substrate; a metal gate structure crossing the fin, the metal gate structure covering a portion of the top and a portion of the sidewall of the fin; and the isolation gate structure is positioned on the substrate between the adjacent fin parts along the extending direction of the fin parts, and the isolation gate structure is made of dielectric materials.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the method comprises the steps of forming an isolation gate structure on a substrate between adjacent fin parts along the extending direction of the fin parts, wherein the isolation gate structure is made of dielectric materials; in the semiconductor process, the isolation gate structure and the metal gate structure crossing the fin parts are usually formed in the same process step, namely the material of the isolation gate structure usually comprises a metal material, and the dielectric material is selected as the material of the isolation gate structure, so that the isolation gate structure has insulating property, the isolation gate structure is prevented from being electrically connected with the adjacent fin parts, the breakdown voltage of the isolation gate structure is further improved, and the electrical performance of a device is improved.
In an alternative, before forming the metal gate structure, the forming method further includes: forming a dummy gate structure on the substrate, wherein the dummy gate structure comprises a first dummy gate structure and a second dummy gate structure, the first dummy gate structure spans across the fin portion and covers part of the top and the side wall of the fin portion, the second dummy gate structure is positioned on the substrate between adjacent fin portions along the extending direction of the fin portion, and then a metal gate structure is formed at the position of the first dummy gate structure in a mode of removing the first dummy gate structure.
In an alternative, before forming the metal gate structure, the forming method further includes: forming a dummy gate structure on the substrate, wherein the dummy gate structure comprises a first dummy gate structure and a second dummy gate structure, the first dummy gate structure spans across the fin portion and covers part of the top and the side wall of the fin portion, and the second dummy gate structure is positioned on the substrate between the adjacent fin portions along the extending direction of the fin portion; the isolation gate structure is formed by removing the first dummy gate structure and refilling the dielectric material, so that the flexibility of material selection of the isolation gate structure is correspondingly improved, and proper materials can be selected according to actual process requirements, so that the device performance is further improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a graph of cumulative distribution of breakdown voltages for gate structures at different locations in the semiconductor structure of FIG. 1;
fig. 3 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 11 to 14 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 15-16 are schematic structural views of an embodiment of a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, after a single diffusion isolation structure is introduced into a semiconductor structure, the device still has the problem of poor performance. The reasons for the improvement in performance are now analyzed in connection with a semiconductor structure.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.
The semiconductor structure includes: a base (not labeled) including a substrate 10 and a plurality of discrete fins 20 located on the substrate 10, wherein a direction parallel to a surface of the substrate 10 and perpendicular to the first direction is a second direction (not labeled) along an extending direction of the fins 20 is a first direction (not labeled), and the fins 20 are arranged in a matrix in the first direction and the second direction; an isolation structure (not shown) on the substrate 10 exposed by the fins 20, wherein the isolation structure includes a first isolation layer (not shown) for isolating the fins 20 in the second direction, and a second isolation layer 11 for isolating the fins 20 in the first direction, the second isolation layer 11 penetrates through the first isolation layer in the second direction, and the second isolation layer is used as an SDB isolation structure; a metal gate structure 30 crossing the fin 20, the metal gate structure 30 covering a portion of the top and a portion of the sidewall of the fin 20; an isolation gate structure 40 located on the second isolation layer 11; a sidewall 35 covering the sidewall of the metal gate structure 30 and the sidewall of the isolation gate structure 40; and the interlayer dielectric layer 12 is positioned on the substrate 10 exposed by the metal gate structure 30 and the isolation gate structure 40, and the interlayer dielectric layer 12 exposes the top of the metal gate structure 30 and the top of the isolation gate structure 40.
The metal gate structure 30 is typically formed by post-forming a high-k gate dielectric layer followed by forming a metal gate (high klast metal gate last), and in a semiconductor process, the metal gate structure 30 is typically formed in the same process step as the isolation gate structure 40. Specifically, the step of forming the metal gate structure 30 and the isolation gate structure 40 includes: forming a dummy gate structure on the substrate 10, wherein the dummy gate structure spans across the fin portion 20 and covers part of the top and part of the side wall of the fin portion 20, and the dummy gate structure is further located on the second isolation layer 11 along the extending direction of the fin portion 20; forming an interlayer dielectric layer 12 on the substrate 10 with the exposed pseudo gate structure; removing the pseudo gate structure and forming a gate opening in the interlayer dielectric layer 12; forming a high-k gate dielectric layer 31 on the bottom and the side wall of the gate opening, and filling a metal material into the gate opening formed with the high-k gate dielectric layer 31 to form a gate electrode layer 32; the high-k gate dielectric layer 31 and the gate electrode layer 32 crossing the fin portion 20 form the metal gate structure 30, and the high-k gate dielectric layer 31 and the gate electrode layer 32 on the second isolation layer 11 form the isolation gate structure 40.
In addition, in order to improve carrier mobility, the semiconductor process generally employs a strained silicon technology (strained silicon), that is, after forming the dummy gate structure, the method further includes: and etching fin parts 20 on two sides of the pseudo gate structure, forming grooves in the fin parts 20, and forming a stress layer doped with ions in the grooves to serve as a source/drain doping layer. In order to improve the shape quality of the groove near the end of the fin 20 (at the position indicated by the dotted line circle a in fig. 1), the width of the dummy gate structure on the second isolation layer 11 along the first direction (not indicated) is generally increased, so that the side wall 35 can cover a portion of the top of the end of the fin 20, and the side wall 35 can further control the shape of the groove.
After increasing the width of the dummy gate structure on the second isolation layer 11 along the first direction, the distance from the dummy gate structure to the fin portion 20 along the first direction is correspondingly reduced, and when the dummy gate structure is shifted (shift) along the first direction, the dummy gate structure is easily contacted with the end surface of the fin portion 20 (at the position shown by the dashed line box b in fig. 1); accordingly, after the isolation gate structure 40 is formed, the isolation gate structure 40 is easily bridged with the end surface of the fin 20. And as the feature size of the device decreases, the probability of bridging between the isolation gate structure 40 and the end surface of the fin 20 increases.
Referring to fig. 2 in combination, fig. 2 is a graph of cumulative distribution functions (Cumulative Distribution Function, CDF) of breakdown voltages of gate structures at different positions in the semiconductor structure shown in fig. 1, the abscissa represents breakdown voltage (Vbd), the ordinate represents the sum of probabilities of occurrence of all the conditions less than or equal to a certain breakdown voltage value, curve 41 represents the cumulative distribution function of breakdown voltages of the metal gate structure 30, and curve 42 represents the cumulative distribution function of breakdown voltages of the isolation gate structure 40. The material of the isolation gate structure 40 includes a metal material, and if the isolation gate structure 40 bridges the end surface of the fin portion 20, the breakdown voltage of the isolation gate structure 40 is easily reduced. Specifically, as shown in fig. 2, the breakdown voltage of the isolation gate structure 40 is smaller than the breakdown voltage of the metal gate structure 30.
In order to solve the technical problem, the isolation gate structure is formed on the substrate between the adjacent fin parts along the extending direction of the fin parts, and the isolation gate structure is made of dielectric materials; in the semiconductor process, the isolation gate structure and the metal gate structure crossing the fin parts are usually formed in the same process step, namely the material of the isolation gate structure usually comprises a metal material, and the dielectric material is selected as the material of the isolation gate structure, so that the isolation gate structure has insulating property, the isolation gate structure is prevented from being electrically connected with the adjacent fin parts, the breakdown voltage of the isolation gate structure is further improved, and the electrical performance of a device is improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3 and 4 in combination, fig. 3 is a perspective view (only two initial fins are illustrated), and fig. 4 is a perspective view (only four fins are illustrated) based on fig. 3, forming a base (not labeled) including a substrate 110 and a plurality of discrete fins 120 (as illustrated in fig. 4) on the substrate 110.
In this embodiment, the substrate 110 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
In this embodiment, the fin 120 and the substrate 110 are integrally formed. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin 120 is the same as the material of the substrate 110, and the material of the fin 120 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.
Specifically, the step of forming the fin 120 and the substrate 110 includes: providing an initial substrate; forming a fin mask layer 150 on the initial substrate; etching the initial substrate by using the fin mask layer 150 as a mask, wherein the etched remaining initial substrate is used as a substrate 110, protrusions on the substrate 110 are used as initial fins 120a (as shown in fig. 3), the extending direction of the initial fins 120a is a first direction (as shown in A1A2 direction in fig. 3), the direction parallel to the surface of the substrate 110 and perpendicular to the first direction is a second direction (as shown in a B1B2 direction in fig. 3), and the initial fins 120a are arranged in a matrix in the first direction and the second direction; and sequentially etching the fin mask layer 150 and the initial fin 120a along the second direction, and forming an isolation groove 115 (as shown in fig. 4) in the initial fin 120a, wherein the isolation groove 115 divides the initial fin 120a into a plurality of fins 120.
Correspondingly, the first direction is parallel to the extending direction of the fin 120, the second direction is perpendicular to the extending direction of the fin, and the fin 120 is arranged in a matrix in the first direction and the second direction.
The isolation trenches 115 are single diffusion barrier isolation trenches (SDB isolation trench), and the isolation trenches 115 are used to provide spatial locations for subsequent formation of single diffusion barrier isolation structures. In this embodiment, the isolation trench 115 exposes the top of the substrate 110. In other embodiments, according to actual process requirements, in the step of forming the fin portions, a substrate with a partial thickness is further etched, that is, the bottom of the isolation trench may also be located in the substrate between adjacent fin portions.
In this embodiment, after the substrate 110 and the fin 120 are formed, the fin mask layer 150 located at the top of the fin 120 is remained. The fin mask layer 150 is made of silicon nitride, and when planarization is performed subsequently, the top surface of the fin mask layer 150 is used for defining a stop position of the planarization, and plays a role in protecting the top of the fin 120.
Referring to fig. 5 in combination, after forming the substrate 110 and the fin 120, the method further includes: an isolation structure (not labeled) is formed on the substrate exposed by the fin 120, the isolation structure covers a portion of the sidewall of the fin 120, the top of the isolation structure is lower than the top of the fin 120, the isolation structure includes a first isolation layer 101 for isolating the fin 120 in the second direction (as shown in the direction B1B2 in fig. 3), and a second isolation layer 102 for isolating the fin 120 in the first direction (as shown in the direction A1A2 in fig. 3), and the second isolation layer 102 penetrates through the first isolation layer 101 along the second direction.
The first isolation layer 101 is used as a shallow trench isolation structure (Shallow Trench Isolat n, STI) for isolating adjacent devices; the second isolation layer 102 serves as a single diffusion isolation structure for reducing leakage current between adjacent fin portions 120 and improving bridging between adjacent source-drain doped layers formed later.
Therefore, the materials of the first isolation layer 101 and the second isolation layer 102 are both insulating materials. In this embodiment, the materials of the first isolation layer 101 and the second isolation layer 102 are both silicon oxide. In other embodiments, the material of the first isolation layer may also be silicon nitride or silicon oxynitride, and the material of the second isolation layer may also be silicon nitride or silicon oxynitride.
Specifically, the step of forming the first isolation layer 101 and the second isolation layer 102 includes: forming an isolation material layer on the exposed substrate 110 of the fin 120, wherein the isolation material layer is further filled in the isolation trench 115 (as shown in fig. 4), and covers the top of the fin mask layer 150; flattening the isolation material layer, and removing the isolation material layer higher than the top of the fin mask layer 150; after the planarization treatment, carrying out back etching (etching back) treatment on the residual isolation material layer, and removing part of the residual isolation material layer with the thickness, wherein the residual isolation material layer after the back etching treatment is used as the isolation structure; the fin mask layer 150 is removed.
It should be noted that, in this embodiment, after the isolation trench 115 (as shown in fig. 4) is formed in the initial fin 120a (as shown in fig. 3), the first isolation layer 101 and the second isolation layer 102 are formed, and compared with the scheme that the first isolation layer is formed on the substrate exposed by the initial fin, then the initial fin and the first isolation layer are sequentially etched along the second direction, and then the second isolation layer is formed between the adjacent fins and between the remaining first isolation layers, the first isolation layer 101 and the second isolation layer 102 can be formed in the same process step, which is beneficial to reducing the difficulty of the etching process for forming the isolation trench, simplifying the process steps and reducing the process cost.
Referring to fig. 6 to 10 in combination, fig. 6 is a cross-sectional view taken along the fin extension direction and at the fin top position (as indicated by the C1C2 line in fig. 5) based on fig. 5, and fig. 7 to 10 are cross-sectional views taken along fig. 6, forming a metal gate structure 400 (as indicated in fig. 10) across the fin 120, the metal gate structure 400 covering a portion of the top and a portion of the sidewall of the fin 120; along the first direction (as shown in the direction A1A2 in fig. 3), an isolation gate structure 300 is formed on the substrate 110 between adjacent fins 120 (as shown in fig. 9), and the isolation gate structure 300 is made of dielectric (dielectric) material.
In semiconductor processes, the isolation gate structure is typically formed in the same process step as the metal gate structure, i.e., the material of the isolation gate structure typically comprises a metal material. In this embodiment, by selecting a dielectric material as the material of the isolation gate structure 300, the isolation gate structure 300 has an insulating property, so that the isolation gate structure 300 is prevented from being electrically connected to the end surface (the position shown by the dashed line frame D in fig. 9) of the adjacent fin portion 120, thereby being beneficial to improving the breakdown voltage of the isolation gate structure 300 and further improving the electrical performance of the device.
The steps of forming the metal gate structure 400 and the isolation gate structure 300 are described in detail below with reference to the accompanying drawings.
Referring to fig. 6, a dummy gate structure (not shown) is formed on the substrate (not shown), the dummy gate structure including a first dummy gate structure 210 and a second dummy gate structure 220, the first dummy gate structure 210 straddles the fin 120 and covers a portion of the top and sidewalls of the fin 120, and the second dummy gate structure 220 is located on the substrate 110 between adjacent fin 120 along the first direction (as shown in A1A2 direction in fig. 3).
In this embodiment, a metal gate structure of the fin field effect transistor is formed by forming a metal gate (high k last metal gate last) after forming a high-k gate dielectric layer, and the first dummy gate structure 210 is used to occupy a space for forming the metal gate structure; the second dummy gate structure 220 is used to provide a process basis for the subsequent formation of the isolation gate structure.
In this embodiment, in order to simplify the process steps of forming the first dummy gate structure 210 and the second dummy gate structure 220 and reduce the process cost, the first dummy gate structure 210 and the second dummy gate structure 220 are formed in the same process step, the materials and structures of the first dummy gate structure 210 and the second dummy gate structure 220 are the same, and the top of the first dummy gate structure 210 and the top of the second dummy gate structure 220 are flush.
In this embodiment, the dummy gate structure is a single-layer structure, and the dummy gate structure includes a dummy gate layer. Specifically, the material of the dummy gate layer is polysilicon, that is, the material of the first dummy gate structure 210 and the material of the second dummy gate structure 220 are polysilicon. In other embodiments, the material of the dummy gate layer may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, amorphous carbon, or other materials.
In other embodiments, the dummy gate structure may also be a stacked structure, where the dummy gate structure includes a dummy gate oxide layer and a dummy gate layer located on the dummy gate oxide layer, and a material of the dummy gate oxide layer may be silicon oxide or silicon oxynitride.
In this embodiment, a first dummy gate structure 210 is formed on one fin 120. In other embodiments, it may also be: a plurality of first dummy gate structures are spaced apart from each other and arranged in parallel across the same fin.
Specifically, the first dummy gate structure 210 spans across the plurality of fins 120 along the second direction (as shown in the direction B1B2 in fig. 3), and the lengths of the first dummy gate structure 210 and the second dummy gate structure 220 along the second direction are equal, so in the step of forming the second dummy gate structure 220 on the substrate 110 between adjacent fins 120, the second dummy gate structure 220 covers the second isolation layer 102 and spans across the plurality of isolation trenches 115 along the second direction (as shown in fig. 4). That is, the second dummy gate structure 220 covers not only the second isolation layer 102 between adjacent fin portions 120 but also the second isolation layer 102 between adjacent first isolation layers 101.
In this embodiment, a mask etching manner is used to form the dummy gate structure. Specifically, the step of forming the dummy gate structure includes: forming a pseudo gate material layer on the first isolation layer 101 (as shown in fig. 5) and the second isolation layer 102 exposed by the fin 120; forming a gate mask layer 250 on the dummy gate material layer; and etching the dummy gate material layer by taking the gate mask layer 250 as a mask, exposing part of the fin portion 120, the first isolation layer 101 and the second isolation layer 102, and taking the etched residual dummy gate material layer as the dummy gate structure.
After the dummy gate structure is formed, the gate mask layer 250 on top of the dummy gate structure is retained. The material of the gate mask layer 250 is silicon nitride, and the gate mask layer 250 is used for protecting the top of the dummy gate structure in the subsequent process.
It should be noted that after the dummy gate structure is formed, the method further includes: a sidewall 230 is formed on the sidewall of the dummy gate structure.
The side wall 230 may be used as an etching mask for a subsequent etching process, to define a formation region of a subsequent source/drain doped layer, and to protect the side wall of the dummy gate structure during the subsequent etching process.
In this embodiment, a gate mask layer 250 is formed on top of the dummy gate structure, so the sidewall 230 also covers the sidewall of the gate mask layer 250.
The material of the side wall 230 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride, and the side wall 230 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 230 has a single-layer structure, and the material of the side wall 230 is silicon nitride.
It should be further noted that the subsequent process further includes etching the fin portion 120 at two sides of the first dummy gate structure 210, forming a groove in the fin portion 120, and then forming a source-drain doped layer in the groove. Along the first direction (as shown in the direction A1A2 in fig. 3), in order to improve the quality of the groove morphology near one side of the end of the fin 120 (at the position indicated by the dashed circle K in fig. 5), the width of the first dummy gate structure 210 along the first direction is greater than the width of the second isolation layer 102 along the first direction, so that it is beneficial to ensure that the side wall 230 can cover part of the top and part of the side wall at the end of the fin 120, and further the side wall 230 plays a role in limiting the groove morphology.
In this embodiment, after forming the sidewall 230, the method further includes: etching fin portions 120 on two sides of the first dummy gate structure 210, and forming grooves (not shown) in the fin portions 120; a source-drain doped layer (not shown) is formed in the groove.
Specifically, when the formed semiconductor structure is an NMOS transistor, the source-drain doped layer includes a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC; when the semiconductor structure is a PMOS transistor, the source-drain doped layer includes a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.
Referring to fig. 7, an interlayer dielectric layer 103 is formed on the substrate 110 where the first and second dummy gate structures 210 and 220 are exposed, the interlayer dielectric layer 103 covers the source and drain doped layers (not shown), and the interlayer dielectric layer 103 exposes the tops of the first and second dummy gate structures 210 and 220.
The interlayer dielectric layer 103 is used for realizing electrical isolation between adjacent devices, and the interlayer dielectric layer 103 is also used for defining the size and the position of a subsequent metal gate structure.
The interlayer dielectric layer 103 is made of an insulating material. In this embodiment, the material of the interlayer dielectric layer 103 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be another dielectric material such as silicon nitride or silicon oxynitride.
Specifically, the step of forming the interlayer dielectric layer 103 includes: forming an interlayer dielectric film on the substrate 110 where the first and second dummy gate structures 210 and 220 are exposed, the interlayer dielectric film covering the top of the gate mask layer 250 (shown in fig. 6); flattening the interlayer dielectric film, removing the interlayer dielectric film higher than the tops of the first dummy gate structure 210 and the second dummy gate structure 220, and reserving the rest of the interlayer dielectric film as the interlayer dielectric layer 103; the gate mask layer 250 is removed.
In this embodiment, after the interlayer dielectric layer 103 is formed, the top of the interlayer dielectric layer 103 is flush with the tops of the first dummy gate structure 210 and the second dummy gate structure 220.
Referring to fig. 8 and 9 in combination, the first dummy gate structure 210 (shown in fig. 8) is removed, and a gate opening 104 (shown in fig. 9) is formed in the interlayer dielectric layer 103.
The gate opening 104 provides a spatial location for the formation of a subsequent metal gate structure.
In this embodiment, the first dummy gate structure 210 spans across the plurality of fins 120 and covers part of the top and part of the sidewalls of the fins 120, so that after the gate opening 104 is formed, the gate opening 104 exposes part of the top and part of the sidewalls of the fins 120, and the gate opening 104 also exposes part of the first isolation layer 101 (as shown in fig. 5).
Specifically, the step of removing the first dummy gate structure 210 includes: forming a first pattern layer 270 (as shown in fig. 8) on the interlayer dielectric layer 103, wherein the first pattern layer 270 covers the second dummy gate structure 220; etching to remove the first dummy gate structure 210 by using the first pattern layer 270 as a mask; after the first dummy gate structure 210 is etched away, the first pattern layer 270 is removed.
Since the first pattern layer 270 covers the second dummy gate structure 220, the second dummy gate structure 220 remains as the isolation gate structure 300 (shown in fig. 9) after the first dummy gate structure 210 is removed.
In this embodiment, the material of the second dummy gate structure 220 is polysilicon, and the material of the isolation gate structure 300 is polysilicon correspondingly. In other embodiments, the material of the isolation gate structure may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, amorphous carbon, or other dielectric materials according to the selection of the material of the second dummy gate structure.
It should be noted that, since the polysilicon is a dielectric material, the second dummy gate structure 220 is kept as the isolation gate structure 300, so that the isolation gate structure 300 and the end surface of the adjacent fin 120 (at the position indicated by the dashed box D in fig. 9) can be prevented from being electrically connected.
Moreover, the second dummy gate structure 220 not only covers the second isolation layer 102 between the adjacent fin portions 120, but also covers the second isolation layer 102 between the adjacent first isolation layers 101, so that the problem that the isolation gate structure 300 is electrically connected to the end surfaces of the adjacent fin portions 120 can be avoided even if the second dummy gate structure 220 is in contact with the end surfaces of the fin portions 120 in the second direction (as shown in the direction B1B2 in fig. 3).
In addition, by reserving the second dummy gate structure 220 as the isolation gate structure 300, no additional process for forming the isolation gate structure 300 is required, and accordingly, the process steps for forming the isolation gate structure 300 are simplified, and the process complexity and the process cost are reduced.
In this embodiment, the material of the first pattern layer 270 is photoresist. In other embodiments, the material of the first graphics layer may also be a Hard Mask (HM) material, for example: tiN, siN or SiO 2 。
Referring to fig. 10, the metal gate structure 400 is formed within the gate opening 104 (as shown in fig. 9).
Specifically, the step of forming the metal gate structure 400 includes: forming a gate dielectric layer 410 on the bottom and the side walls of the gate opening 104, wherein the gate dielectric layer 410 spans across the fin 120 and covers part of the top and part of the side walls of the fin 120, and the gate dielectric layer 410 also covers the first isolation layer 101 exposed by the gate opening 104 (as shown in fig. 5); a gate electrode layer 420 is formed on the gate dielectric layer 410, and the gate electrode layer 420 is filled in the gate opening 104.
Note that in this embodiment, the second dummy gate structure 220 is reserved as the isolation gate structure 300, and the metal gate structure 400 is formed at the position of the first dummy gate structure 210 (as shown in fig. 8), so that after the metal gate structure 400 is formed, the top of the metal gate structure 400 is level with the top of the isolation gate structure 300.
The gate dielectric layer 410 is made of a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the gate dielectric layer 410 is made of HfO 2 . In other embodiments, the gate dielectric layer material may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
In this embodiment, the material of the gate electrode layer 420 is W. In other embodiments, the material of the gate electrode layer may also be Al, cu, ag, au, pt, ni or Ti, etc.
Fig. 11 to 14 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that: by removing the second dummy gate structure 620 (as shown in fig. 11), an isolation gate structure 700 (as shown in fig. 13) is formed at the location of the second dummy gate structure 620.
Specifically, the forming method includes:
referring to fig. 11 and 12 in combination, after forming an interlayer dielectric layer 503 on a substrate 510 where a first dummy gate structure 610 and a second dummy gate structure 620 (shown in fig. 11) are exposed, the second dummy gate structure 620 is removed, and a trench 613 (shown in fig. 12) is formed in the interlayer dielectric layer 503.
The trenches 613 are used to provide spatial locations for the subsequent formation of isolation gate structures.
Specifically, the step of removing the second dummy gate structure 620 includes: forming a second pattern layer 660 on the interlayer dielectric layer 503, wherein the second pattern layer 660 covers the first dummy gate structure 610; etching to remove the second dummy gate structure 620 by using the second pattern layer 660 as a mask; after the second dummy gate structure 620 is etched away, the second pattern layer 660 is removed.
In this embodiment, after the second dummy gate structure 620 is formed, the second dummy gate structure 620 covers the second isolation layer 502, so that the trench 613 exposes the second isolation layer 502 after the trench 613 is formed.
In this embodiment, a dry etching process is used to etch and remove the second dummy gate structure 620. By adopting the dry etching process, the efficiency of removing the second dummy gate structure 620 by etching is improved, and the dry etching process has anisotropic etching characteristics, which is also beneficial to reducing the influence of the dry etching process on other film layers or structures, for example: a first dummy gate structure 610 or a fin 520 adjacent to the second dummy gate structure 620.
In this embodiment, the material of the second pattern layer 660 is photoresist. In other embodiments, the material of the second graphics layer may also be a hard mask material, for example: tiN, siN or SiO 2 。
Referring to fig. 13, after the second dummy gate structure 620 (shown in fig. 11) is removed, the trench 613 (shown in fig. 12) is filled with a dielectric material, and the dielectric material in the trench 613 is used as the isolation gate structure 700.
In this embodiment, the material of the isolation gate structure 700 is silicon nitride. The silicon nitride has better insulation property, and the etching selectivity of the polysilicon and the silicon nitride is higher, so that a maskless etching mode can be adopted when the first dummy gate structure 610 is removed later, which is beneficial to simplifying the process steps for removing the first dummy gate structure 610.
In other embodiments, the material of the isolation gate structure may be polysilicon, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon boron carbonitride, silicon oxycarbide, amorphous carbon, low-k dielectric materials, or ultra-low-k dielectric materials. Wherein, the low-k dielectric material refers to a dielectric material with a relative dielectric constant of more than or equal to 2.6 and less than or equal to 3.9, and the ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant of less than 2.6.
Specifically, the step of forming the isolation gate structure 700 includes: filling the trench 613 with a dielectric material which also covers the top of the interlayer dielectric layer 503; and flattening the dielectric material, removing the dielectric material higher than the top of the interlayer dielectric layer 503, and reserving the dielectric material in the groove 613 as the isolation gate structure 700, wherein the top of the isolation gate structure 700 is flush with the top of the first dummy gate structure 610.
After removing the dielectric material higher than the top of the interlayer dielectric layer 503, the remaining dielectric material is exposed at the top of the first dummy gate structure 610, thereby providing a process basis for the subsequent removal of the first dummy gate structure 610.
In this embodiment, the process of filling the trench 613 with the dielectric material is a chemical vapor deposition process, so that the dielectric material has a good filling effect in the trench 613.
It should be noted that, in this embodiment, the manner of removing the second dummy gate structure 620 (as shown in fig. 11) to form the trench 613 and then forming the isolation gate structure 700 in the trench 613 is beneficial to improving the flexibility of material selection of the isolation gate structure 700, i.e. selecting a suitable material according to the actual process requirement, so that the device performance is beneficial to meeting the actual process requirement.
Referring to fig. 14, after the isolation gate structure 700 is formed, the first dummy gate structure 610 (as shown in fig. 13) is removed, and a gate opening (not shown) is formed in the interlayer dielectric layer 503; a metal gate structure 800 is formed within the gate opening.
In this embodiment, the metal gate structure 800 includes a gate dielectric layer 810 and a gate electrode layer 820 on the gate dielectric layer 810.
For a specific description of the gate opening and the metal gate structure 800, reference may be made to the corresponding description in the foregoing embodiments, and a detailed description is omitted herein.
Note that, in this embodiment, the top of the isolation gate structure 700 is flush with the top of the first dummy gate structure 610, and the metal gate structure 800 is formed at the position of the first dummy gate structure 610, so that after the metal gate structure 800 is formed, the top of the metal gate structure 800 is flush with the top of the isolation gate structure 700.
It should be further noted that, in this embodiment, the material of the first dummy gate structure 610 and the material of the isolation gate structure 700 have a high etching selectivity, and the process of removing the first dummy gate structure 610 has little loss on the isolation gate structure 700, so that a mask layer (e.g., a photoresist layer) covering the isolation gate structure 700 does not need to be formed during the process of removing the first dummy gate structure 610, thereby avoiding waste of extra process cost and time.
In other embodiments, in order to further protect the isolation gate structure, a mask layer covering the isolation gate structure may also be formed before removing the first dummy gate structure.
For a specific description of the forming method in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 15 and 16 in combination, a schematic structural diagram of an embodiment of a semiconductor structure according to the present invention is shown, fig. 15 is a perspective view (only illustrating a substrate, a fin and an isolation structure), and fig. 16 is a cross-sectional view based on fig. 15 along the extending direction of the fin and along a line (E1E 2 line in fig. 15) at a position on top of the fin.
The semiconductor structure includes: a base (not shown) comprising a substrate 910 and a plurality of discrete fins 920 located on the substrate 910; a metal gate structure 930 (as shown in fig. 16) that spans the fin 920, the metal gate structure 930 covering a portion of the top and a portion of the sidewalls of the fin 920; an isolation gate structure 950 (as shown in fig. 16), along the extending direction of the fin 920, is located on the substrate 910 between adjacent fin 920, where the isolation gate structure 950 is made of a dielectric material.
In this embodiment, the substrate 910 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
In this embodiment, the fin 920 and the substrate 910 are integrally formed. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin 920 is the same as the material of the substrate 910, and the material of the fin 920 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.
In this embodiment, the extending direction of the fin 920 is a first direction (as shown in the direction F1F2 in fig. 15), and a second direction (as shown in the direction G1G2 in fig. 15) parallel to the surface of the substrate 910 and perpendicular to the first direction, and the fin 920 is arranged in a matrix in the first direction and the second direction.
The semiconductor structure includes: an isolation structure (not labeled) is located on the substrate 910 where the fin 920 is exposed, the isolation structure covers a portion of the sidewall of the fin 920, and the top of the isolation structure is lower than the top of the fin 920.
In this embodiment, the isolation structure includes a first isolation layer 901 (as shown in fig. 15) for isolating the second direction fins 920, and a second isolation layer 902 (as shown in fig. 15) for isolating the first direction fins 920, and the second isolation layer 902 penetrates the first isolation layer 901 along the second direction.
The first isolation layer 901 is used as a shallow trench isolation structure and is used for isolating adjacent devices; the second isolation layer 902 serves as a single diffusion isolation structure, which is used for reducing leakage current between adjacent fin portions 920 and improving bridging problem between adjacent source-drain doped layers.
Therefore, the materials of the first isolation layer 901 and the second isolation layer 902 are both insulating materials. In this embodiment, the materials of the first isolation layer 901 and the second isolation layer 902 are both silicon oxide. In other embodiments, the material of the first isolation layer may also be silicon nitride or silicon oxynitride, and the material of the second isolation layer may also be silicon nitride or silicon oxynitride.
In this embodiment, the metal gate structure 930 includes a gate dielectric layer 931 (as shown in fig. 16) and a gate electrode layer 932 (as shown in fig. 16) disposed on the gate dielectric layer 931.
In this embodiment, the metal gate structure 930 spans across the fins 920 along the second direction, and for convenience of illustration, one metal gate structure 930 is formed on one fin 920 for illustration. In other embodiments, it may also be: a plurality of spaced and parallel metal gate structures cross the same fin.
Correspondingly, the gate dielectric layer 931 spans across the fin 920 and covers a portion of the top and a portion of the sidewall of the fin 920, and the gate dielectric layer 931 also covers a portion of the first isolation layer 901.
The gate dielectric layer 931 is made of a high k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the gate dielectric layer 931 is made of HfO 2 . In other embodiments, the gate dielectric layer may also be made of a material selected from the group consisting ofZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
In this embodiment, the material of the gate electrode layer 932 is W. In other embodiments, the material of the gate electrode layer may also be Al, cu, ag, au, pt, ni or Ti, etc.
It should be noted that the semiconductor structure further includes: the side walls 940 are located on the side walls of the metal gate structure 930 and also located on the side walls of the isolation gate structure 950; a source-drain doped layer (not shown) is located in the fin 920 at two sides of the metal gate structure 930.
During the formation of the semiconductor structure, the side walls 940 are used to define the formation region of the source/drain doped layer, and also to protect the sidewalls of the metal gate structure 930 and the isolation gate structure 950.
The material of the side wall 940 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride, and the side wall 940 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 940 has a single-layer structure, and the material of the side wall 940 is silicon nitride.
When the formed semiconductor structure is an NMOS transistor, the source-drain doped layer comprises a stress layer doped with N-type ions, and the material of the stress layer can be Si or SiC; when the semiconductor structure is a PMOS transistor, the source-drain doped layer includes a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.
Along the first direction, the isolation gate structure 950 is located on the substrate 910 between adjacent fins 920, and the isolation gate structure 950 is made of a dielectric material.
In this embodiment, the isolation gate structure 950 covers the second isolation layer 902 and extends along the second direction. That is, the isolation gate structure 950 covers the second isolation layer 902 between adjacent fin portions 920 and also covers the second isolation layer 902 between adjacent first isolation layers 901.
It should be noted that, the source-drain doped layer is generally located in the groove in the fin 920, along the first direction, in order to improve the quality of the groove profile near one side of the end of the fin 920 (at the position indicated by the dashed circle L in fig. 15), the width of the isolation gate structure 950 along the first direction is greater than the width of the second isolation layer 902 along the first direction, so that it is beneficial to ensure that the side wall 940 can cover part of the top and part of the side wall at the end of the fin 920, and further the side wall 940 plays a role in limiting the groove profile.
In this embodiment, the dielectric material is selected as the material of the isolation gate structure 950, so that the isolation gate structure 950 has an insulating property, and thus the electrical connection between the isolation gate structure 950 and the end surface (the position indicated by the dashed line frame H in fig. 16) of the adjacent fin portion 920 is avoided, and the breakdown voltage of the isolation gate structure 950 is improved, which is beneficial to improving the electrical performance of the device.
It should be further noted that, the metal gate structure 930 is formed by forming the gate electrode layer (high k last metal gate last) after forming the high-k gate dielectric layer, so that during the formation of the semiconductor structure, a process of forming a dummy gate structure is generally included, and the dummy gate structure includes a first dummy gate structure and a second dummy gate structure, where the first dummy gate structure spans the fin 920 and covers part of the top and the sidewall of the fin 920, and the second dummy gate structure is located on the substrate 910 between adjacent fin 920 along the first direction, and the top of the first dummy gate structure and the top of the second dummy gate structure are flush. In this embodiment, during the formation of the semiconductor structure, the metal gate structure 930 is formed at the position of the first dummy gate structure, and the second dummy gate structure is reserved as the isolation gate structure 950, so that the top of the isolation gate structure 950 is flush with the top of the metal gate structure 930.
By reserving the second dummy gate structure as the isolation gate structure 950, no additional process for forming the isolation gate structure 950 is required, and accordingly, the process steps for forming the semiconductor structure are simplified, and the process complexity and the process cost are reduced.
Since the material of the dummy gate structure is usually polysilicon, in this embodiment, the material of the isolation gate structure 950 is polysilicon. Polysilicon is a dielectric material, and by selecting the polysilicon material, the electrical connection between the isolation gate structure 950 and the end surface of the adjacent fin 920 can be avoided.
In other embodiments, the material of the isolation gate structure may be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon boron carbonitride, silicon oxycarbide, or amorphous carbon, among other dielectric materials, depending on the choice of the material of the dummy gate structure.
In other embodiments, during the formation of the semiconductor structure, the isolation gate structure may be formed at the position of the second dummy gate structure by removing the second dummy gate structure, so as to improve the flexibility of material selection of the isolation gate structure. Correspondingly, the material of the isolation gate structure can also be a low-k dielectric material or an ultra-low-k dielectric material.
The semiconductor structure may be formed by the forming method described in the foregoing first embodiment, may be formed by the forming method described in the foregoing second embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (16)
1. A method of forming a semiconductor structure, comprising:
forming a base including a substrate and a plurality of discrete fins on the substrate;
after the substrate is formed and before the metal gate structure is formed, a dummy gate structure is formed on the substrate, the dummy gate structure comprises a first dummy gate structure and a second dummy gate structure, the first dummy gate structure spans across the fin portion and covers part of the top and the side wall of the fin portion, the second dummy gate structure is located on the substrate between adjacent fin portions along the extending direction of the fin portion, and the second dummy gate structure is used for providing a process foundation for forming the isolation gate structure;
forming an interlayer dielectric layer on the substrate exposed by the pseudo gate structure, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate structure;
forming a metal gate structure crossing the fin, wherein the metal gate structure covers part of the top and part of the side wall of the fin, and the metal gate structure comprises the following steps: removing the first dummy gate structure, and forming a gate opening in the interlayer dielectric layer; forming the metal gate structure in the gate opening;
And forming an isolation gate structure on the substrate between the adjacent fin parts along the extending direction of the fin parts, wherein the isolation gate structure is made of dielectric materials.
2. The method of forming a semiconductor structure of claim 1, wherein forming isolation gate structures on a substrate between adjacent fins comprises: and after the first dummy gate structure is removed, the second dummy gate structure is reserved as the isolation gate structure.
3. The method of forming a semiconductor structure of claim 2, wherein removing the first dummy gate structure comprises: forming a first graph layer on the interlayer dielectric layer, wherein the first graph layer covers the second pseudo gate structure;
etching to remove the first pseudo gate structure by taking the first graph layer as a mask;
and removing the first graph layer after etching to remove the first pseudo gate structure.
4. The method of claim 3, wherein the material of the first pattern layer is a photoresist or a hard mask material.
5. The method of forming a semiconductor structure of claim 1, further comprising, after forming an interlayer dielectric layer on the substrate on which the dummy gate structure is exposed, before removing the first dummy gate structure: removing the second pseudo gate structure and forming a groove in the interlayer dielectric layer;
The step of forming the isolation gate structure on the substrate between the adjacent fin parts comprises the following steps: and filling dielectric materials into the grooves before removing the first dummy gate structures, wherein the dielectric materials in the grooves are used as the isolation gate structures.
6. The method of forming a semiconductor structure of claim 5, wherein removing the second dummy gate structure comprises: forming a second graph layer on the interlayer dielectric layer, wherein the second graph layer covers the first pseudo gate structure;
etching to remove the second pseudo gate structure by taking the second graph layer as a mask;
and removing the second graph layer after etching to remove the second pseudo gate structure.
7. The method of forming a semiconductor structure of claim 5, wherein the process of filling the trench with a dielectric material is a chemical vapor deposition process.
8. The method of claim 6, wherein the material of the second pattern layer is a photoresist or a hard mask material.
9. The method of forming a semiconductor structure of claim 2, wherein the material of the isolation gate structure is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, or amorphous carbon.
10. The method of claim 5, wherein the isolation gate structure is formed of a material selected from the group consisting of polysilicon, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, silicon boron carbonitride, silicon oxycarbide, amorphous carbon, low k dielectric materials, and ultra low k dielectric materials.
11. The method of claim 1, wherein in the step of forming the base, a first direction is along an extending direction of the fin portion, a second direction is parallel to the substrate surface and perpendicular to the first direction, and the fin portion is arranged in a matrix in the first direction and the second direction;
after the substrate is formed, before the dummy gate structure is formed, the method further comprises: and forming an isolation structure on the substrate exposed by the fin parts, wherein the isolation structure covers part of the side walls of the fin parts, the top of the isolation structure is lower than the top of the fin parts, the isolation structure comprises a first isolation layer for realizing isolation between the fin parts in the second direction, and a second isolation layer for realizing isolation between the fin parts in the first direction, and the second isolation layer penetrates through the first isolation layer in the second direction.
12. The method of claim 11, wherein in forming a second dummy gate structure on the substrate between adjacent fins, the second dummy gate structure covers a second isolation layer between the fins and also covers a second isolation layer between the first isolation layer.
13. A semiconductor structure, comprising:
a base comprising a substrate and a plurality of discrete fins located on the substrate;
an interlayer dielectric layer which is positioned on the substrate and covers part of the side wall of the fin part; the metal gate structure spans the fin, covers part of the top and part of the side wall of the fin and is positioned in a gate opening formed in the interlayer dielectric layer, and the gate opening is formed by removing a first dummy gate structure which spans the fin and covers part of the top and the side wall of the fin;
the isolation gate structure is a second pseudo gate structure, is positioned on the substrate between the adjacent fin parts along the extending direction of the fin parts, is made of dielectric materials, and is positioned on the substrate between the adjacent fin parts, and the second pseudo gate structure is used for providing a process foundation for forming the isolation gate structure.
14. The semiconductor structure of claim 13, wherein the isolation gate structure is of a material selected from the group consisting of polysilicon, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon boron carbonitride, silicon oxycarbide, amorphous carbon, low k dielectric materials, and ultra low k dielectric materials.
15. The semiconductor structure of claim 13, wherein an extension direction along the fin is a first direction, and a second direction parallel to the substrate surface and perpendicular to the first direction, the fin being arranged in a matrix in the first direction and the second direction;
the semiconductor structure further includes: the isolation structure is located on the substrate with the fin portions exposed, the isolation structure covers part of the side walls of the fin portions, the top of the isolation structure is lower than the top of the fin portions, the isolation structure comprises a first isolation layer used for achieving isolation between the fin portions in the second direction, a second isolation layer used for achieving isolation between the fin portions in the first direction, and the second isolation layer penetrates through the first isolation layer in the second direction.
16. The semiconductor structure of claim 15, wherein the isolation gate structure covers a second isolation layer between the fins and also covers a second isolation layer between the first isolation layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810947256.1A CN110854194B (en) | 2018-08-20 | 2018-08-20 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810947256.1A CN110854194B (en) | 2018-08-20 | 2018-08-20 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110854194A CN110854194A (en) | 2020-02-28 |
| CN110854194B true CN110854194B (en) | 2023-12-12 |
Family
ID=69595148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810947256.1A Active CN110854194B (en) | 2018-08-20 | 2018-08-20 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110854194B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113539958A (en) * | 2020-04-17 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113394109A (en) * | 2021-05-31 | 2021-09-14 | 上海华力集成电路制造有限公司 | Manufacturing method of first-cut SDB FinFET |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206687A (en) * | 2015-05-29 | 2016-12-07 | 台湾积体电路制造股份有限公司 | The structure of semiconductor device structure and forming method |
| CN108010884A (en) * | 2016-11-01 | 2018-05-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9130023B2 (en) * | 2012-06-05 | 2015-09-08 | Kabushiki Kaisha Toshiba | Isolated insulating gate structure |
-
2018
- 2018-08-20 CN CN201810947256.1A patent/CN110854194B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206687A (en) * | 2015-05-29 | 2016-12-07 | 台湾积体电路制造股份有限公司 | The structure of semiconductor device structure and forming method |
| CN108010884A (en) * | 2016-11-01 | 2018-05-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110854194A (en) | 2020-02-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10734519B2 (en) | Structure and method for FinFET device with asymmetric contact | |
| CN110277316B (en) | Semiconductor structure and forming method thereof | |
| CN110828541B (en) | Semiconductor structure and forming method thereof | |
| CN110767549B (en) | Semiconductor structure and forming method thereof | |
| CN112309861B (en) | Semiconductor structure, forming method thereof and transistor | |
| CN108461544B (en) | Semiconductor structure and forming method thereof | |
| CN108538724B (en) | Semiconductor structure and forming method thereof | |
| CN110581173A (en) | Semiconductor structure and forming method thereof | |
| CN110718465B (en) | Semiconductor structure and forming method thereof | |
| CN110854194B (en) | Semiconductor structure and forming method thereof | |
| CN110634798A (en) | Semiconductor structure and forming method thereof | |
| US11349027B2 (en) | Structure and method for FinFET device with asymmetric contact | |
| CN117652014A (en) | Semiconductor structure and forming method thereof | |
| CN109003976B (en) | Semiconductor structure and forming method thereof | |
| CN110875390B (en) | Semiconductor structure and forming method thereof | |
| CN112951725B (en) | Semiconductor structure and forming method thereof | |
| US12009426B2 (en) | Structure and method for FinFET device with asymmetric contact | |
| CN112151378B (en) | Semiconductor structure and forming method thereof | |
| US20230387261A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN111554636B (en) | Semiconductor structure and forming method thereof | |
| US11011608B2 (en) | Semiconductor structure and method for forming the same | |
| CN110120415B (en) | Semiconductor structure and forming method thereof | |
| CN117410333A (en) | Semiconductor structure and forming method thereof | |
| CN114765131A (en) | Method for forming semiconductor structure | |
| CN117810226A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |