CN115332244B - ESD structure of small-size groove Mosfet and manufacturing method thereof - Google Patents

ESD structure of small-size groove Mosfet and manufacturing method thereof Download PDF

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CN115332244B
CN115332244B CN202211005764.0A CN202211005764A CN115332244B CN 115332244 B CN115332244 B CN 115332244B CN 202211005764 A CN202211005764 A CN 202211005764A CN 115332244 B CN115332244 B CN 115332244B
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esd
region
gate
groove
layer
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CN115332244A (en
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陈铭阳
杨超
丁浩宸
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Wuxi Huixin Semiconductor Co ltd
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Wuxi Huixin Semiconductor Co ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The invention discloses an ESD structure of a small-size groove Mosfet and a manufacturing method thereof, which belong to the technical field of semiconductor integrated circuit manufacturing. The ESD area is arranged in the terminal area in a ring shape or a loop shape, so that the total length of the ESD is increased, the protection capability of the ESD is improved, the damage of the ESD to the power Mosfet is fundamentally reduced, the Gate resistor is arranged in the Gate area, the Gate oscillation is eliminated through the Gate resistor, and the power of the driver is transferred.

Description

ESD structure of small-size groove Mosfet and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to an ESD structure of a small-size groove Mosfet and a manufacturing method thereof.
Background
Electrostatic discharge (ESD) is the transfer of electrostatic charge between two different electrostatic objects caused by direct contact or electrostatic field induction. Static electricity is a very common phenomenon, and when people carry static electricity voltages on and around the body, such as chemical fiber clothes, walking, friction of people and the like, strong static electricity is generated, and the voltage of the static electricity is thousands of volts, which is fatal to most semiconductors and integrated circuits. It is well known that most substances are composed of atoms and protons. When a substance gains or loses electrons, its electrical balance changes, becoming a positively/negatively charged object. Contact pressure, coefficient of friction, separation rate, etc. are important factors that affect charge accumulation. The static charge continues to build up until the effect of the charge is lost, the charge is released, or a sufficient strength is reached to break down the surrounding material. When the dielectric breaks down, the electrostatic charge rapidly goes into an equilibrium state, and this rapid neutralization of the charge is known as electrostatic discharge. The bleed current may be large, possibly exceeding 20 amps, due to the rapid bleed voltage across a small resistor, which would cause serious damage to the device or circuit if such discharge were to be done by a power Mosfet or other integrated circuit. The invention provides a method for realizing protection function on ESD damage on a small die groove type MOSFET.
The protection method for ESD damage mainly comprises two methods: on the one hand, external factors improve the manufacturing, working, transportation, storage environment and technical requirements of equipment and circuits; on the other hand, the internal factors are used for improving the performance of the internal ESD protection circuit of the chip. Initially, one would try to avoid the occurrence of ESD and minimize its transmission in the transportation, storage and operating environment of the device. However, the application environment of the power Mosfet device is complex, the gate source pin is exposed, the antistatic performance of the power Mosfet device is poor, and the ESD protection cannot achieve the expected effect. Compared with the protection of ESD from the outside, the method radically reduces the damage of ESD to the power Mosfet, namely improves the ESD resistance of the device, and achieves the expected ESD resistance on the premise of controlling the cost.
Disclosure of Invention
The invention aims to: an ESD structure of a small-sized trench Mosfet and a manufacturing method thereof are provided to solve the above problems in the prior art.
The technical scheme is as follows: an ESD structure of a small-size trench Mosfet comprises a terminal region, an ESD region arranged on the inner side of the terminal region, and a cell region arranged on the inner side of the ESD region;
the cell region comprises a substrate, an epitaxial layer arranged on the substrate and a groove part arranged on the epitaxial layer;
a gate oxide layer provided on an upper surface of the epitaxial layer and an inner wall surface of the trench portion,
gate polysilicon deposited inside the trench portion;
the body region is arranged in the epitaxial layer and is implanted with P-type ions;
an ESD isolation layer disposed on the gate oxide layer, the ESD isolation layer further contacting the gate polysilicon deposited in the trench portion;
forming a gate resistance region and an ESD region by photoetching and etching the ESD polysilicon and the ESD isolation layer, wherein the gate resistance region and the ESD region are respectively arranged on the ESD isolation layer;
forming an ESD-P type region and an ESD-N doped region by implanting ions into the ESD region;
a source region arranged in the epitaxial layer and implanted with N ions;
the isolation oxide layer is arranged on the grid oxide layer;
a metal layer; the isolation oxide layer is arranged on the silicon substrate;
after the metal layer is deposited, forming source metal and gate metal through photoetching and etching;
the terminal area is designed to be annular.
In a further embodiment, the isolation oxide layer is provided with a source contact hole and a gate contact hole.
In a further embodiment, the source contact hole extends into the body region through the isolation oxide layer, gate oxide layer and source region;
four groups of grid contact holes are formed;
the four groups of gate contact holes are respectively extended to the upper surfaces of the gate resistance region and the ESD-N doped region to be communicated.
In a further embodiment, the ESD region comprises a first horizontal portion, a first vertical portion connected to the first horizontal portion, a second horizontal portion connected to the first vertical portion, and a second vertical portion connected to the second horizontal portion;
the second vertical part is also connected with the first horizontal part.
In a further embodiment, the first horizontal portion, the first vertical portion, the second horizontal portion, and the second vertical portion are equal in length;
the first horizontal part is parallel to the second horizontal part;
the first vertical part and the second vertical part are mutually parallel;
the first vertical part and the second vertical part are provided with a first end and a second end;
the first vertical part and the second vertical part are perpendicular to the first horizontal part through a first end;
the first vertical portion and the second vertical portion are perpendicular to the second horizontal portion through the second end.
In a further embodiment, a gate resistor is disposed within the gate resistor region.
In a further embodiment, the groove portion is provided in a U-shape;
the groove part comprises a first groove, a second groove, a third groove and a fourth groove;
the first groove, the second groove and the third groove have the same structure;
the depth of the fourth groove is the same as that of the first groove;
the fourth grooves have a width greater than the width of the first grooves.
In a further embodiment, the fourth trench is a conductive region of the gate lead-out.
In a further embodiment, the ESD region is implanted with ions, P-type ions and N-type ions, respectively;
injecting P-type ions into the ESD-P-type region;
the ESD-N type region is implanted with N type ions.
In a further embodiment, a method for manufacturing an ESD structure of a small-sized trench Mosfet includes the steps of;
step 1, forming an epitaxial layer on the surface of a substrate;
step 2, photoetching and etching are carried out on the epitaxial layer to form a groove part;
step 3, forming a gate oxide layer on the surface of the epitaxial layer and in the groove, depositing gate polysilicon on the surface of the chip and in the groove, and etching away the surface polysilicon, wherein only the polysilicon in the groove is reserved;
step 4, performing P-type ion implantation in the body region;
step 5, depositing an ESD isolating layer on the surface of the whole chip and then depositing ESD polysilicon;
step 6, forming a grid resistance region and an ESD region by photoetching and etching the ESD polysilicon and the ESD isolation layer, then carrying out P-type ion implantation, and annealing at 980-1350 ℃ after the P-type ion implantation is completed, wherein the annealing time is 60-80 min, so as to form a grid resistance 203 and an ESD-P type region 205;
step 7; performing N-type ion implantation, and then annealing at 850-1050 ℃ for 25-45 min to form a source region 106 and an ESD-N-type region 206, thereby obtaining an ESD diode (a plurality of groups of back-to-back structures, the number of groups can be increased according to the ESD requirement);
step 8, depositing an isolation oxide layer, and forming a source electrode contact hole and a grid electrode contact hole after photoetching and etching;
and 9, depositing a metal layer on the isolation oxide layer, and forming source electrode metal and gate electrode metal after photoetching and etching.
The beneficial effects are that: the invention discloses an ESD structure of a small-size groove Mosfet and a manufacturing method thereof, wherein an ESD area is arranged outside a cellular area in a ring shape or a loop shape, so that the total length of the ESD is increased, the protection capability of the ESD is improved, the damage of the ESD to the power Mosfet is fundamentally reduced, a grid resistor is arranged in a Gate area, grid oscillation is eliminated through the grid resistor, and the power of a driver is transferred.
Drawings
FIG. 1 is a process flow diagram of the present invention;
FIG. 2 is a plan view of the structure of the present invention;
FIG. 3 is a cross-sectional view of a termination area of the present invention;
FIG. 4 is a plan view of a conventional structure of the present invention;
FIG. 5 is a cross-sectional view of a trench portion of the present invention;
fig. 6 is a cross-sectional view of a cellular region of the present invention.
Description of the drawings: 1. a terminal area; 3. a cell region; 11. a first horizontal portion; 12. a second horizontal portion; 13. a first vertical portion; 14. a second vertical portion; 15. a first trench; 16. a second trench; 17. a third trench; 18. a fourth trench; 101. a substrate; 102. an epitaxial layer; 103. a gate oxide layer; 104. gate polysilicon; 105. implanting a body region; 200. an ESD isolation layer; 201. ESD polysilicon; 203. a gate resistance region; 204. an ESD area; 205. an ESD-P type region; 206. an ESD-N type region; 106. a source region; 107. an isolation oxide layer; 108. a source contact hole; 109. a gate contact hole; 110. a source metal; 111. and (3) gate metal.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that embodiments of the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the embodiments of the invention.
In the description of the present invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The present invention will be described in more detail with reference to the following examples and the accompanying drawings.
An ESD structure of a small-size trench Mosfet consists of a terminal area, an ESD area and a cell area 3, wherein the terminal area is arranged at the periphery of the ESD area, the ESD area is arranged at the periphery of the cell area, the cell area 3 comprises a substrate 101, an epitaxial layer 102 is arranged on the substrate 101, a trench is arranged on the epitaxial layer 102, a gate oxide layer 103 is arranged on the inner wall of the trench and the surface of the epitaxial layer 102, and gate polysilicon 104 is deposited inside the trench; in the epitaxial layer 102, P-type ions are implanted to form a body region. An ESD isolation layer 200 is disposed on the gate oxide layer 103; the ESD isolation layer 200 is formed on the gate oxide layer 103 by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition, the substrate 101 with the oxide layer is placed in a reaction chamber filled with dichlorosilane and ammonia gas to react under proper pressure and temperature, and the ESD isolation layer 200 is deposited, and the thickness of the ESD isolation layer 200 can be adjusted by controlling the high temperature reaction time, in this embodiment, the thickness of the ESD isolation layer 200 is 1500-2250 angstroms, specifically 2000 angstroms.
Specifically, in order to improve the ESD performance, ESD polysilicon 201 is disposed on the ESD isolation layer 200; forming a gate resistance region 203 and an ESD region 204 by photoetching and etching of ESD polysilicon 201 deposited on the surface of the ESD isolation layer 200, performing ESD-P type ion doping to form the ESD-P type doping 205, and then performing high-temperature annealing at 980-1350 ℃ for 60-80 min, wherein the high-temperature annealing time is controlled to be 60 mm-80 min, and simultaneously repairing implantation damage of a body region and implantation damage of the ESD-P type region and uniformly distributing ions; source region 106 and ESD-N region 206 are formed simultaneously by N-type ion implantation and annealing; an isolation oxide layer 107 provided on the entire chip surface; a metal layer is disposed on the isolation oxide layer 107; after deposition, the metal layers are subjected to photolithography and etching to form source metal 110 and gate metal 111. Specifically, the ESD region 204 is designed to annularly surround the inside of the termination region (as shown in fig. 1).
Specifically, the isolation oxide layer 107 is provided with a source contact hole 108 and a gate contact hole 109; the source contact hole 108 extends to a surface layer position in the body region implantation region 105 through the isolation oxide layer 107 and the source region 106; the gate contact hole 109 extends to the polysilicon, the gate resistance region 203, and the ESD-N type region inside the trench.
As a preferable case, in order to further increase the ESD capability of the device, i.e., increase the total length of the ESD region, the ESD region 204 includes a first horizontal portion 11, a first vertical portion 13 connected to the first horizontal portion 11, a second horizontal portion 12 connected to the first vertical portion 13, and a second vertical portion 14 connected to the second horizontal portion; the second vertical part 14 is also connected with the first horizontal part 11, and the lengths of the first horizontal part 11, the first vertical part 13, the second horizontal part 12 and the second vertical part 14 are equal; the first horizontal portion 11 is parallel to the second horizontal portion 12; the first vertical part 13 and the second vertical part 14 are parallel to each other; the first and second vertical portions 13 and 14 have first and second ends; the first vertical part 13 and the second vertical part 14 are perpendicular to the first horizontal part 11 through a first end; the first vertical portion 13 and the second vertical portion 14 are perpendicular to the second horizontal portion 12 through a second end. The terminal area is formed through photoetching and etching; the ESD region is located inside the termination region, and the cellular region 3 is located inside the ESD region. As shown in fig. 4, the layout of the conventional ESD region 204 is shown in fig. 4, the conventional ESD region 204 covers the inner side of the terminal region, the overall length performance is poor, the improved ESD region 204 is shown in fig. 1, the ESD region 204 is arranged on the inner side of the whole terminal region, and the whole cell region 3 circumferentially surrounds the ESD region 204, so that the ESD performance is improved.
Specifically, in order to further improve the application stability of the ESD Mosfet, a gate resistor is disposed in the gate resistor region 203. As shown in fig. 5, the gate resistor eliminates the gate oscillation, and because the gate source of the trench Mosfet is capacitive, the parasitic inductance of the gate loop is unavoidable, and if there is no gate resistor, the gate loop is strongly oscillated under the excitation of the driver driving pulse, and therefore a resistor must be connected in series to quickly attenuate. Meanwhile, the grid resistance can also transfer the power loss of the driver, and as the capacitance and the inductance are all reactive elements, if the grid resistance is not provided, most of driving power is consumed on an output pipe inside the driver, so that the temperature of the driver is increased greatly. Meanwhile, the grid resistance is small, the switching device is fast in switching on and off, and the switching loss is small; otherwise, the switching loss is large. However, the too high driving speed greatly increases the voltage and current change rate of the switching device, so that larger interference is generated, and the whole device cannot work seriously, so that the overall consideration is necessary. The on-off speed of the power switch device is conveniently adjusted. Further improving the stability of the ESD structure, and arranging the groove part in a U shape; the groove portion includes a first groove 15, a second groove 16, a third groove 17, and a fourth groove 18; the first groove 15, the second groove 16 and the third groove 17 have the same structure, and the fourth groove 18 has the same depth as the first groove 15; the width of the fourth groove 18 is larger than that of the first groove 15, the fourth groove 18 is a conductive area led out from a gate area, and polysilicon is filled in the grooves.
Specifically, preferably, body implantation may be followed by no annealing. After the ESD-P type doping, the same type examples are annealed together, so that a primary thermal process is reduced; the ESD-N type doping works together during the implantation of the source region, and one mask is reduced. The energy is 30-60 Kev, and the dosage is 1E 15-1E 16.
As a preferred case, a method for manufacturing an ESD structure of a small-sized trench Mosfet includes the steps of;
step 1, forming an epitaxial layer 102 on the surface of a substrate 101;
step 2, forming a groove part after photoetching and etching on the epitaxial layer 102; specifically, the terminal areas are formed synchronously, and the terminal areas are shown in fig. 3.
Step 3, forming a gate oxide layer on the surface of the epitaxial layer 102 and in the trench, and depositing gate polysilicon on the surface of the chip and in the trench, wherein the surface polysilicon is etched later, and only the polysilicon in the trench is reserved;
step 4, implanting P-type ions into the body region 105;
step 5, depositing an ESD isolating layer 200 on the surface of the whole chip and then depositing ESD polysilicon 201;
step 6, forming a gate resistance region 203 and an ESD region 204 by photoetching and etching the ESD polysilicon and the ESD isolation layer, wherein the ESD region 204 is designed into a ring shape or a loop shape, performing P-type ion implantation and annealing, wherein the annealing temperature is 980-1350 ℃, and the annealing time is 60-80 min, so as to form the gate resistance region 203 and the ESD-P-type region 205;
step 7; performing N-type ion implantation, and then annealing at 850-1050 ℃ for 25-45 min to form a source region 106 and an ESD-N-type region 206, thereby obtaining an ESD diode (a plurality of groups of back-to-back structures, the number of groups can be increased according to the ESD requirement);
step 8, depositing an isolation oxide layer 107, and forming a source contact hole 108 and a gate contact hole 109 after photoetching and etching;
and 9, depositing a metal layer, and forming a source metal 110 and a gate metal 111 after photoetching and etching.
The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the specific details of the above embodiments, and various equivalent changes can be made to the technical solutions of the present invention within the scope of the technical concept of the present invention, and these equivalent changes all fall within the scope of the present invention.

Claims (10)

1. An ESD structure of a small-sized trench Mosfet, characterized in that: comprises a terminal region (1), an ESD region (204) arranged inside the terminal region (1), and a cell region (3) arranged inside the ESD region (204);
the cell region (3) comprises a substrate (101), an epitaxial layer (102) arranged on the substrate (101), and a groove part arranged on the epitaxial layer (102);
a gate oxide layer (103) provided on the upper surface of the epitaxial layer (102) and the inner wall surface of the trench portion, and gate polysilicon (104) deposited inside the trench portion;
a body implant region (105) disposed in the epitaxial layer (102) for P-type ion implantation;
an ESD isolation layer (200) disposed on the gate oxide layer (103), the ESD isolation layer (200) also being in contact with the gate polysilicon (104) deposited in the trench portion;
forming a gate resistance region (203) and an ESD region (204) by photolithography and etching of an ESD polysilicon (201) and an ESD isolation layer (200), the gate resistance region (203) and the ESD region (204) being disposed on the ESD isolation layer (200), respectively;
forming an ESD-P-type region and an ESD-N doped region by implanting ions into the ESD region (204);
a source region (106) disposed in the epitaxial layer (102) and implanted with N-type ions;
an isolation oxide layer (107) provided on the gate oxide layer (103);
a metal layer; is arranged on the isolation oxide layer (107);
after depositing the metal layer, forming source metal (110) and gate metal (111) through photoetching and etching;
the terminal region (1) is designed to be annular.
2. The ESD structure of a small-scale trench Mosfet according to claim 1, wherein: the isolation oxide layer (107) is provided with a source contact hole (108) and a gate contact hole (109).
3. An ESD structure for a small-scale trench Mosfet according to claim 2, wherein: the source contact hole (108) extends to the body region injection region (105) through the isolation oxide layer (107), the gate oxide layer (103) and the source region (106);
four groups of grid contact holes (109) are formed;
four groups of gate contact holes (109) are respectively extended to the upper surfaces of the gate resistance region (203) and the ESD-N doped region to be communicated.
4. The ESD structure of a small-scale trench Mosfet according to claim 1, wherein: the ESD area (204) comprises a first horizontal part (11), a first vertical part (13) connected with the first horizontal part (11), a second horizontal part (12) connected with the first vertical part (13), and a second vertical part (14) connected with the two horizontal parts (12);
the second vertical part (14) is also connected with the first horizontal part (11).
5. The ESD structure of a small-scale trench Mosfet according to claim 4, wherein: the lengths of the first horizontal part (11), the first vertical part (13), the second horizontal part (12) and the second vertical part (14) are equal;
the first horizontal part (11) is parallel to the second horizontal part (12);
the first vertical part (13) and the second vertical part (14) are parallel to each other;
the first vertical part (13) and the second vertical part (14) are provided with a first end and a second end;
the first vertical part (13) and the second vertical part (14) are perpendicular to the first horizontal part (11) through a first end;
the first vertical part (13) and the second vertical part (14) are perpendicular to the second horizontal part (12) through the second end.
6. The ESD structure of a small-scale trench Mosfet according to claim 1, wherein: a gate resistor is arranged in the gate resistor region (203).
7. The ESD structure of a small-scale trench Mosfet according to claim 1, wherein: the groove part is arranged in a U shape;
the groove part comprises a first groove (15), a second groove (16), a third groove (17) and a fourth groove (18); the first groove (15), the second groove (16) and the third groove (17) have the same structure;
the fourth groove (18) has the same depth as the first groove (15);
the fourth grooves (18) have a width greater than the width of the first grooves (15).
8. The ESD structure of a small-scale trench Mosfet of claim 7, wherein: the fourth groove (18) is a conductive region led out by the grid electrode.
9. The ESD structure of a small-scale trench Mosfet according to claim 1, wherein: the ESD area (204) is implanted with ions, and P-type ions and N-type ions are respectively implanted;
implanting P-type ions into the ESD-P-type region 205;
the ESD-N type region (206) is implanted with N type ions.
10. The method for manufacturing the ESD structure of the small-sized trench Mosfet according to claim 1, wherein: comprises the following steps of;
step 1, forming an epitaxial layer (102) on the surface of a substrate (101);
step 2, photoetching and etching are carried out on the epitaxial layer (102) to form a groove part;
step 3, forming a gate oxide layer (103) on the surface of the epitaxial layer (102) and in the groove, depositing gate polysilicon on the surface of the chip and in the groove, and etching away the surface polysilicon later, wherein only the polysilicon in the groove is reserved;
step 4, P-type ion implantation is carried out in the body region implantation region (105);
step 5, depositing an ESD isolation layer (200) on the surface of the whole chip and then depositing ESD polysilicon (201);
step 6, forming a gate resistance region (203) and an ESD region (204) by photoetching and etching the ESD polysilicon (201) and the ESD isolation layer (200), then carrying out P-type ion implantation, and carrying out annealing at 980-1350 ℃ after the P-type ion implantation is completed, wherein the annealing time is 60-80 min, and forming the gate resistance region (203) and the ESD-P-type region (205);
step 7; performing N-type ion implantation, and then annealing at 850-1050 ℃ for 25-45 min to form a source region (106) and an ESD-N-type region (206), thereby obtaining an ESD diode (a plurality of groups of back-to-back structures, wherein the number of groups can be increased according to the ESD requirement);
step 8, depositing an isolation oxide layer (107), and forming a source electrode contact hole (108) and a gate electrode contact hole (109) after photoetching and etching;
and 9, depositing a metal layer on the isolation oxide layer (107), and forming source metal (110) and gate metal (111) after photoetching and etching.
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