CN112117999A

CN112117999A - Drive circuit and household appliance

Info

Publication number: CN112117999A
Application number: CN202010865074.7A
Authority: CN
Inventors: 刘利书
Original assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd
Current assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd
Priority date: 2020-08-25
Filing date: 2020-08-25
Publication date: 2020-12-22
Also published as: WO2022041625A1

Abstract

The application discloses a driving circuit and a household appliance, wherein the driving circuit comprises a signal processing circuit, a signal processing circuit and a signal processing circuit, wherein the signal processing circuit is configured to process an input signal to obtain an intermediate signal; a first output circuit; a second output circuit; and the selection circuit is connected with the signal processor and is configured to control the signal processing circuit to select to be connected with the first output circuit or the second output circuit according to the input signal so that the first output circuit or the second output circuit processes the intermediate signal to obtain an output signal. Through the mode, the high-low voltage control signal matching degree of the driving circuit can be improved, and meanwhile, the phenomenon of short circuit penetration in the driving circuit is avoided.

Description

Drive circuit and household appliance

Technical Field

The application relates to the technical field of circuits, in particular to a driving circuit and a household appliance.

Background

With the rapid development of electronic technology, especially the application of high-frequency self-turn-off devices such as IGBTs and MOSFETs becomes increasingly wide, the design of the driving circuit becomes more important. The drive circuit with good performance can enable the electronic device to work in a relatively ideal switching state, shorten the switching time, reduce the switching loss, realize the over-current protection of the electronic device and have important significance on the efficiency, the reliability and the safety of the power converter.

However, in the conventional driving circuit, the high-voltage and low-voltage control signals are respectively processed by the respective processing circuits and then output, so that the problem of unmatched high-voltage and low-voltage control signals exists, the switch matching of the upper bridge power device and the lower bridge power device is influenced, and the reliability of the system is reduced.

Disclosure of Invention

The application provides drive circuit and domestic appliance to solve the unmatched problem of prior art high-low voltage control signal.

In order to solve the above technical problem, the present application provides a driving circuit, including a signal processing circuit configured to process an input signal to obtain an intermediate signal; a first output circuit; a second output circuit; and the selection circuit is connected with the signal processing circuit and is configured to control the signal processing circuit to select to be connected with the first output circuit or the second output circuit according to the input signal so that the first output circuit or the second output circuit processes the intermediate signal to obtain an output signal.

In order to solve the above technical problem, the present application provides a household appliance, including the above driving circuit.

The application discloses a driving circuit, which comprises a signal processing circuit, a signal processing circuit and a control circuit, wherein the signal processing circuit is configured to process an input signal to obtain an intermediate signal; a first output circuit; a second output circuit; and the selection circuit is connected with the signal processing circuit and is configured to control the signal processing circuit to select to be connected with the first output circuit or the second output circuit according to the input signal so that the first output circuit or the second output circuit processes the intermediate signal to obtain an output signal. Through the mode, the driving circuit can process input signals through the same signal processing circuit, and high-low voltage control signals are obtained through processing through different output circuits, so that the problem that the high-low voltage control signals are not matched due to different signal processing circuits is solved; meanwhile, the safety of the driving circuit can be improved, and the problem of penetration of high-voltage and low-voltage control signals is prevented.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an embodiment of a driving circuit of the present application;

FIG. 2 is a schematic circuit diagram of an embodiment of the rectifying and filtering circuit in FIG. 1;

FIG. 3 is a circuit diagram of an embodiment of the level shift circuit of FIG. 1;

FIG. 4 is a schematic circuit diagram of an embodiment of the edge triggered circuit of FIG. 1;

FIG. 5 is a circuit diagram of an embodiment of the pulse generating circuit of FIG. 1;

FIG. 6 is a circuit diagram of an embodiment of the high voltage output circuit of FIG. 1;

FIG. 7 is a circuit diagram of one embodiment of the low voltage output circuit of FIG. 1;

fig. 8 is a schematic structural diagram of an embodiment of the household appliance of the present application.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present application, the driving circuit and the household appliance provided by the present invention are further described in detail below with reference to the accompanying drawings and the detailed description.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present application. The driving circuit 100 may include a signal processing circuit 110, a first output circuit 120, a second output circuit 130, a selection circuit 140, a first input terminal 150, and a second input terminal 160.

Wherein the signal processing circuit 110 may be configured to process the input signal, thereby obtaining an intermediate signal. The selection circuit 140 may be connected to the signal processing circuit, and the selection circuit 140 may be configured to control the signal processing circuit 110 to alternatively connect to the first output circuit 120 or the second output circuit 130 according to the input signal, so that the first output circuit 120 or the second output circuit 130 processes the intermediate signal to obtain an output signal, thereby implementing circuit driving.

Wherein the first output circuit 120 and the second output circuit 130 may perform different circuit processes on the intermediate signal; the input signal may include a first signal or a second signal, wherein a voltage value of the first signal may be higher than a voltage value of the second signal. The first signal may be a high voltage signal of a relatively high voltage in the driving circuit 100, and the second signal may be a low voltage signal of a relatively low voltage in the driving circuit 100.

The first input terminal 150 may be configured to input a first signal and the second input terminal 160 may be configured to input a second signal. The selection circuit 140 may be connected to the first input terminal 150 and the second input terminal 160, respectively.

Specifically, the signal processing circuit 110 may include a rectifying-filtering circuit 111 and a level-shifting circuit 112. The rectifying and filtering circuit 111 may be respectively connected to the first input terminal 150 and the second input terminal 160, and may be configured to receive an input signal from the first input terminal or the second input terminal, perform rectifying and filtering processing on the input signal, and output a rectifying and filtering signal. The level shift circuit 112 may be connected to the output terminal of the rectifying and filtering circuit, and receive the rectifying and filtering signal, perform a level shift process on the rectifying and filtering signal, and output an intermediate signal.

Referring to fig. 2, fig. 2 is a schematic circuit diagram of an embodiment of the rectifying and filtering circuit in fig. 1. In the present embodiment, the rectifying and filtering circuit 111 may include thirteen transistors. Specifically, the control terminal of the first transistor Q1 may be configured to receive an input signal, the first terminal of the first transistor Q1 may be configured to be connected to the power source VCC, and the first terminal of the first transistor Q1 may be connected to the third terminal of the first transistor Q1.

A control terminal of the second transistor Q2 may be connected to a control terminal of the first transistor Q1, a control terminal of the second transistor Q2 may be used to receive an input signal, a first terminal of the second transistor Q2 may be used to connect a second terminal of the first transistor Q1, a second terminal of the second transistor Q2 may be connected to VSS, and a second terminal of the second transistor Q2 may be connected to a third terminal of the second transistor Q2.

A first terminal of the first capacitor C1 may be connected between the first terminal of the second transistor Q2 and the second terminal of the first transistor Q1 through a first resistor R1, and a second terminal of the first capacitor C1 may be connected to ground VSS.

A first terminal of the third transistor Q3 may be connected to a power supply VCC, and a first terminal of the third transistor Q3 may be connected to a third terminal of the third transistor Q3. A first terminal of the fourth transistor Q4 may be connected to the second terminal of the third transistor Q3, and a third terminal of the fourth transistor Q4 may be connected to the third terminal of the third transistor Q3.

A first terminal of the fifth transistor Q5 may be connected to a second terminal of the fourth transistor Q4. A first terminal of the sixth transistor Q6 may be connected to the second terminal of the fifth transistor Q5, a second terminal of the sixth transistor Q6 may be connected to the ground VSS, a second terminal of the sixth transistor Q6 may be connected to the third terminal of the sixth transistor Q6, and a third terminal of the sixth transistor Q6 may be connected to the third terminal of the fifth transistor Q5.

Among them, a control terminal of the third transistor Q3, a control terminal of the fourth transistor Q4, a control terminal of the fifth transistor Q5, and a control terminal of the sixth transistor Q6 may be connected, and a node thereof may be connected between the first resistor R1 and the first terminal of the first capacitor C1.

A first terminal of the seventh transistor Q7 may be connected between the second terminal of the third transistor Q3 and the first terminal of the fourth transistor Q4, and a third terminal of the seventh transistor Q7 may be connected to the power supply VCC. A second terminal of the eighth transistor Q8 may be connected between the second terminal of the fifth transistor Q5 and the first terminal of the sixth transistor Q6, and a third terminal of the eighth transistor Q8 may be connected to the ground VSS.

Wherein a control terminal of the seventh transistor Q7 and a control terminal of the eighth transistor Q8 may be connected, and a node thereof may be connected between the first terminal of the fifth transistor Q5 and the second terminal of the fourth transistor Q4.

A control terminal of the ninth transistor Q9 and the second terminal of the seventh transistor Q7 may be connected to ground VSS, a first terminal of the ninth transistor Q9 may be connected to the power VCC, a first terminal of the ninth transistor Q9 may be connected to the third terminal of the ninth transistor Q9, and a second terminal of the ninth transistor Q9 may be connected to the first terminal of the eighth transistor Q8.

A first terminal of the tenth transistor Q10 may be connected to the power VCC, and a first terminal of the tenth transistor Q10 may be connected to the third terminal of the tenth transistor Q10. A first terminal of the eleventh transistor Q11 may be connected to the second terminal of the tenth transistor Q10, a second terminal of the eleventh transistor Q11 may be connected to the ground VSS, and a first terminal of the eleventh transistor Q11 may be connected to the third terminal of the eleventh transistor Q11.

Wherein a control terminal of the tenth transistor Q10 and a control terminal of the eleventh transistor Q11 may be connected, and a node thereof may be connected between the control terminal of the seventh transistor Q7 and the control terminal of the eighth transistor Q8.

A first terminal of the twelfth transistor Q12 may be connected to the power VCC, and a first terminal of the twelfth transistor Q12 may be connected to the third terminal of the twelfth transistor Q12. A first terminal of the thirteenth transistor Q3578 may be connected to the second terminal of the twelfth transistor Q12, a node thereof may serve as an output terminal of the rectifying-smoothing circuit 111 to output the rectifying-smoothing signal, a second terminal of the thirteenth transistor Q13 may be connected to the ground VSS, and a second terminal of the thirteenth transistor Q13 is connected to the third terminal of the thirteenth transistor Q13.

Wherein a control terminal of the twelfth transistor Q12 may be connected with a control terminal of the thirteenth transistor Q13, and a node thereof may be connected between the second terminal of the tenth transistor Q10 and the first terminal of the eleventh transistor Q11.

In the present embodiment, the first, third, fourth, and seventh transistors Q1, Q3, Q4, Q7, Q9, Q10, and Q12 may be PMOS transistors.

The second, fifth, sixth, eighth, eleventh, and thirteenth transistors Q2, Q5, Q6, Q8, Q11, and Q13 may be NMOS transistors. In the first to thirteenth transistors Q1 to Q13, the control terminal may be a gate of the MOS transistor, the first terminal may be a source/drain of the MOS transistor, the second terminal may be a source/drain of the MOS transistor, and the third terminal may be a substrate electrode of the MOS transistor.

The rectifying and filtering circuit 111 can realize a hysteresis control function, and avoid the generation of false operation. Meanwhile, the noise signal in the waveform shaping and filtering circuit is realized, and the interference is reduced.

Optionally, the rectifying and filtering circuit 111 may further include a protection circuit 1111, and the protection circuit 1111 may be formed by five logic gates, which are: a first not gate G5, a first and gate G6, a second not gate G7, a second and gate G8, and a first or gate G9.

An input terminal of the first not gate G5 may receive the first signal HIN; a first input of the first and gate G6 may be connected to the output of the first not gate G5, and a second input of the first and gate G6 may receive the second signal LIN; an input of the second not gate G7 may receive the second signal LIN; a first input terminal of the second and gate G8 may be connected to an output terminal of the second not gate G7, and a second input terminal of the second and gate G8 may receive the first signal HIN; a first input terminal of the first or gate G9 may be connected to an output terminal of the first and gate G6, a second input terminal of the first or gate G9 may be connected to an output terminal of the second and gate G8, and an output terminal of the first or gate G9 is connected between the control terminal of the first transistor and the control terminal of the second transistor.

When the protection circuit 1111 works, only one signal can pass through at the same time, for example, when the protection circuit 1111 receives the first signal, it is equivalent to that the first not gate G5 receives a high voltage and outputs a low voltage; the first input terminal of the first and gate G6 receives a low voltage, the second input terminal of the first and gate G6 receives a low voltage, and the first and gate G6 outputs a low voltage; the second not gate G7 receives a low voltage and outputs a high voltage, the first terminal of the second and gate G8 receives a high voltage, the second terminal of the second and gate G8 receives a high voltage, and the second terminal of the second and gate G8 outputs a high voltage; the first input terminal of the first or gate G9 receives a low voltage, the second output terminal of the first or gate G9 receives a high voltage, and the first or gate G9 outputs the high voltage to the control terminals of the first transistor Q1 and the second transistor Q2, so that the first signal can be rectified and filtered.

When the protection circuit 1111 receives the second signal, the operation principle is similar to that when the protection circuit receives the first signal, and the description thereof is omitted.

When a special condition occurs, for example, when the protection circuit 1111 receives the first signal and the second signal at the same time, it is equivalent that the first not gate G5 receives a high voltage and outputs a low voltage; the first input terminal of the first and gate G6 receives a low voltage, the second input terminal of the first and gate G6 receives a low voltage, and the first and gate G6 outputs a low voltage; the second not gate G7 receives the high voltage and outputs a low voltage; a first input terminal of the second and gate G8 receives a low voltage, a second input terminal of the second and gate G8 receives a low voltage, and the second and gate G8 outputs a low voltage; the first input end of the first or gate G9 receives a low voltage, the second output end of the first or gate G9 receives a low voltage, the first or gate G9 outputs a low voltage to the control ends of the first transistor Q1 and the second transistor Q2, and at this time, the first transistor Q1 and the second transistor Q2 cannot normally operate, so that a protection function is realized, and circuit abnormality caused by the fact that the first signal and the second signal exist in the rectifying and filtering circuit 111 at the same time is avoided.

Referring to fig. 3, fig. 3 is a circuit structure diagram of an embodiment of the level shift circuit in fig. 1. In the present embodiment, the level shift circuit 112 may include transistors Q14 to Q25.

Specifically, a control terminal of the fourteenth transistor Q14, a control terminal of the fifteenth transistor Q15, a control terminal of the sixteenth transistor Q16, and a control terminal of the seventeenth transistor Q17 are connected to receive the rectified and filtered signal.

A first terminal of the fourteenth transistor Q14 may be connected to the reference power source VREG, and a first terminal of the fourteenth transistor Q14 may be connected to the third terminal of the fourteenth transistor Q14.

A first terminal of the fifteenth transistor Q15 may be connected to a first terminal of the fourteenth transistor Q14, and a third terminal of the fifteenth transistor Q15 may be connected to a third terminal of the fourteenth transistor Q14.

A first terminal of the sixteenth transistor Q16 may be connected to a second terminal of the fifteenth transistor Q15. A first terminal of the seventeenth transistor Q17 may be connected to the second terminal of the sixteenth transistor Q16, and a third terminal of the seventeenth transistor Q17 may be connected to the third terminal of the sixteenth transistor Q16.

A first terminal of the eighteenth transistor Q18 may be connected between the second terminal of the fourteenth transistor Q14 and the first terminal of the fifteenth transistor Q15, a second terminal of the eighteenth transistor Q18 may be connected to the ground VSS, and a third terminal of the eighteenth transistor Q18 may be connected to the reference power source VREG.

A control terminal of the nineteenth transistor Q19 may be connected to a control terminal of the eighteenth transistor Q18, a first terminal of the nineteenth transistor Q19 may be connected to the reference power source VREG, and a second terminal of the nineteenth transistor Q19 may be connected between a second terminal of the sixteenth transistor Q16 and a first terminal of the seventeenth transistor Q17.

A first terminal of the twentieth transistor Q20 may be connected to the reference power source VREG, and a third terminal of the twentieth transistor Q20 may be connected to a first terminal of the twentieth transistor Q20. A first terminal of the twenty-first transistor Q21 may be connected to a second terminal of the twentieth transistor Q20, a second terminal of the twenty-first transistor Q21 may be connected to a third terminal of the twenty-first transistor Q21, and a control terminal of the twenty-first transistor Q21 may be connected to a control terminal of the twentieth transistor Q20.

Wherein the second terminal of the seventeenth transistor Q17, the third terminal of the nineteenth transistor Q19, and the second terminal of the twenty-first transistor Q21 may be connected.

A first terminal of the twentieth transistor Q22 may be connected to the power VCC, and a third terminal of the twentieth transistor Q22 may be connected to a first terminal of the twentieth transistor Q22. A first terminal of the twenty-third transistor Q23 may be connected to the second terminal of the twenty-second transistor Q22, a second terminal of the twenty-third transistor Q23 may be connected to the ground VSS, and a third terminal of the twenty-third transistor Q23 may be connected to the second terminal of the twenty-third transistor Q23.

Among them, a connection node of the second terminal of the fifteenth transistor Q15 and the first terminal of the sixteenth transistor Q16, a connection node of the control terminal of the eighteenth transistor Q18 and the control terminal of the nineteenth transistor Q19, a connection node of the control terminal of the twentieth transistor Q20 and the control terminal of the twenty-first transistor Q21, and a control terminal of the twenty-third transistor Q23 may be connected.

A first terminal of the twenty-fourth transistor Q24 may be connected to the power supply VCC, a third terminal of the twenty-fourth transistor Q24 may be connected to a first terminal of the twenty-fourth transistor Q24, and a control terminal of the twenty-fourth transistor Q24 may be connected between a second terminal of the twenty-second transistor Q22 and a first terminal of the twenty-third transistor Q23.

A first terminal of the twenty-fifth transistor Q25 may be connected to a second terminal of the twenty-fourth transistor Q24, a node of which is an output terminal of the level shift circuit 112 to output an intermediate signal; a second terminal of the twenty-fifth transistor Q25 may be connected to the ground VSS, and a second terminal of the twenty-fifth transistor Q25 may be connected to the third terminal of the twenty-fifth transistor Q25. A control terminal of the twenty-fifth transistor Q25 may be connected between the second terminal of the twentieth transistor Q20 and the first terminal of the twenty-first transistor Q21.

In the present embodiment, the fourteenth transistor Q14, the fifteenth transistor Q15, the eighteenth transistor Q18, the twentieth transistor Q20, the twentieth transistor Q22 and the twenty-fourth transistor Q24 may be PMOS transistors.

The sixteenth transistor Q16, the seventeenth transistor Q17, the nineteenth transistor Q19, the twenty-first transistor Q21, the twenty-third transistor Q23, and the twenty-fifth transistor Q25 may be NMOS transistors. In addition, in the fourteenth to twenty-fifth transistors Q14 to Q25, the control terminal may be a gate of the MOS transistor, the first terminal may be a source/drain of the MOS transistor, the second terminal may be a source/drain of the MOS transistor, and the third terminal may be a substrate electrode of the MOS transistor.

The level shift circuit 112 can adjust the amplitude range of the rectified and filtered signal to a voltage value corresponding to VSS-VCC according to the design requirement of the user.

With continued reference to fig. 1, the selection circuit 140 may be configured to control the signal processing circuit 110 to connect to the first output circuit 120 in response to receiving the first signal; or in response to the second signal, the signal processing circuit 110 is controlled to be connected to the second output circuit 130.

The selection circuit 140 may include an edge trigger circuit 141 and a switching circuit 142. The edge trigger circuit 141 may be connected to the first input terminal and the second input terminal, and may be configured to generate a trigger signal according to the first signal or the second signal.

The switch circuit 142 may include a first connection terminal, a second connection terminal, and a control terminal, and the first connection terminal may be connected to the signal processing circuit 110 to receive the intermediate signal; the control terminal may be used to connect the edge trigger circuit 141 to input a trigger signal; the second connection terminal may be a mobile connection terminal, and may alternatively connect to the first output circuit 120 or the second output circuit 130 according to the trigger signal.

Referring to fig. 4, fig. 4 is a schematic circuit diagram of an embodiment of the edge triggered circuit in fig. 1. In this embodiment, the edge trigger circuit 141 may include a JK flip-flop. The JK flip-flop may include a J signal input terminal, a K signal input terminal, and a signal output terminal.

The J signal input may be connected to the first input 150 to receive a first signal, the K signal input may be connected to the second input 160 to receive a second signal, and the signal outputs may include Q and

the control terminal of the switch circuit 142 may be connected, and the second connection terminal of the switch circuit 142 is used to select to connect the first output circuit or the second output circuit according to the trigger signal output by the JK flip-flop.

Specifically, as shown in fig. 2, the JK flip-flop may include four nand gates, a first nand gate G1, a second nand gate G2, a third nand gate G3, and a fourth nand gate G4.

The first input terminal of the first nand gate G1 is used as a J signal input terminal, the first input terminal of the second nand gate G2 is not used as a K signal input terminal, and the second input terminal of the first nand gate G1 is connected to the second input terminal of the second nand gate G2 and receives the clock signal CP. The output end of the first nand gate G1 is connected to the first input end of the third nand gate G3, and the output end of the second nand gate G2 is connected to the first input end of the fourth nand gate G4.

The third input end of the second nand gate G2 and the second input end of the fourth nand gate G4 are connected with the output end of the third nand gate G3, and the node thereof outputs Q; the third input terminal of the first NAND gate G1 and the second input terminal of the third NAND gate G3 are connected to the output terminal of the fourth NAND gate G4, and the node outputs

The JK flip-flop has 0, 1, hold and flip functions as shown in the following figures:

in this embodiment, when the JK flip-flop receives the first signal, Q outputs a high level; when the JK flip-flop receives the second signal, Q outputs a low level. When the switch circuit 142 can use the high level or the low level of the Q output of the JK flip-flop as the trigger signal, one of the two signals is selected to connect the first output circuit 120 or the second output circuit 130: when the Q output is high, the first output circuit 120 may be selectively connected; when the Q output level is high, the second output circuit 130 may be selectively connected.

With continued reference to fig. 1, the first output circuit 120 may include a pulse generation circuit 121 and a high voltage output circuit 122. The pulse generating circuit 121 may be configured to receive the intermediate signal and generate a pulse signal according to the intermediate signal; the high voltage output circuit 122 may be configured to receive the pulse signal and generate a high voltage output signal based on the pulse signal.

Referring to fig. 5, fig. 5 is a circuit structure diagram of an embodiment of the pulse generating circuit in fig. 1. In this embodiment, the pulse generating circuit 121 may include the following:

a first terminal of the twenty-sixth transistor Q26 may be connected to the power supply VCC, and a third terminal of the twenty-sixth transistor Q26 may be connected to a first terminal of the twenty-sixth transistor Q26. A first terminal of the twenty-seventh transistor Q27 is connected to a second terminal of the twenty-sixth transistor Q26, a second terminal of the twenty-seventh transistor may be connected to the ground VSS, a control terminal of the twenty-sixth transistor Q26 may be connected to a control terminal of the twenty-seventh transistor Q27, and a node thereof serves as an input terminal of the pulse generating circuit 1221 to receive the intermediate signal.

A first terminal of the twenty-eighth transistor Q28 may be connected to the power supply VCC, and a third terminal of the twenty-eighth transistor Q28 may be connected to a first terminal of the twenty-eighth transistor Q28. A first terminal of the twenty-ninth transistor Q29 may be connected to the second terminal of the twenty-eighth transistor Q28 through a second resistor R2, a second terminal of the twenty-ninth transistor Q29 may be connected to the ground VSS, and a third terminal of the twenty-ninth transistor Q29 may be connected to the second terminal of the twenty-ninth transistor Q29.

Wherein a control terminal of the twenty-eighth transistor Q28 may be connected to a control terminal of the twenty-ninth transistor Q29, and a node thereof may be connected between a control terminal of the twenty-sixth transistor Q26 and a control terminal of the twenty-seventh transistor Q27.

A first terminal of the thirtieth transistor Q30 may be connected to the power VCC, and a third terminal of the thirtieth transistor Q30 may be connected to a first terminal of the thirtieth transistor Q30. A first terminal of the thirty-first transistor Q31 may be connected to the second terminal of the thirtieth transistor Q30, and a third terminal of the thirty-first transistor Q31 may be connected to the third terminal of the thirtieth transistor Q30.

A first terminal of the thirty-second transistor Q32 may be connected to a first terminal of a thirty-first transistor Q31. A first terminal of the thirty-third transistor Q33 may be connected to the second terminal of the thirty-second transistor Q32, a second terminal of the thirty-third transistor Q33 may be grounded VSS, a third terminal of the thirty-third transistor Q33 may be connected to the second terminal of the thirty-third transistor Q33, and a third terminal of the thirty-third transistor Q33 may be connected to the third terminal of the thirty-second transistor Q32.

A control terminal of the thirtieth transistor Q30, a control terminal of the thirty-first transistor Q31, a control terminal of the thirty-second transistor Q32, and a control terminal of the thirty-third transistor Q33 may be connected, and a node thereof is connected to the second terminals of the second resistor R2 and the twenty-eighth transistor Q28. A first terminal of the second capacitor C2 may be connected between the second terminal of the twenty-eighth transistor Q28 and the control terminal of the thirty-first transistor Q31.

A first terminal of the thirty-fourth transistor Q34 may be connected between the second terminal of the thirty-fourth transistor Q30 and the first terminal of the thirty-first transistor Q31. A second terminal of the thirty-fifth transistor Q35 may be connected between the second terminal of the thirty-second transistor Q32 and the first terminal of the thirty-third transistor Q33, and a third terminal of the thirty-fifth transistor Q35 may be connected to the ground VSS.

Wherein, a control terminal of the thirty-fourth transistor Q34 may be connected to a control terminal of the thirty-fifth transistor Q35, and a node thereof may be connected to the second terminal of the thirty-fourth transistor Q30 and the first terminal of the thirty-second transistor Q32.

A first terminal of the thirty-sixth transistor Q36 may be connected to the power VCC, a second terminal of the thirty-sixth transistor Q36 may be connected to a first terminal of the thirty-fifth transistor Q35, a third terminal of the thirty-sixth transistor Q36 may be connected to a first terminal of the thirty-sixth transistor Q36, and a control terminal of the thirty-sixth transistor Q36 may be connected to a second terminal of the thirty-fourth transistor Q34.

A first terminal of the thirty-seventh transistor Q37 may be connected to the power VCC, and a third terminal of the thirty-seventh transistor Q37 may be connected to a first terminal of the thirty-seventh transistor Q37. A first terminal of the thirty-eighth transistor Q38 may be connected to the second terminal of the thirty-seventh transistor Q37, a second terminal of the thirty-eighth transistor Q38 may be grounded, and a third terminal of the thirty-eighth transistor Q38 may be connected to the second terminal of the thirty-eighth transistor Q38.

Wherein a control terminal of the thirty-seventh transistor Q37 and a control terminal of the thirty-eighth transistor Q38 may be connected, and a node thereof may be connected between a control terminal of the thirty-fourth transistor Q34 and a control terminal of the thirty-fifth transistor Q35.

A first terminal of the thirty-ninth transistor Q39 may be connected to the power VCC, and a third terminal of the thirty-ninth transistor Q39 may be connected to a first terminal of the thirty-ninth transistor Q39. A first terminal of the forty-th transistor Q40 may be connected to a second terminal of the thirty-ninth transistor Q39. A second terminal of the fortieth transistor Q40 may be connected to the ground VSS, and a third terminal of the fortieth transistor Q40 may be connected to the second terminal of the fortieth transistor Q40.

Wherein a control terminal of the thirty-ninth transistor Q39 may be connected with a control terminal of the thirty-ninth transistor Q39, a node of which is connected between the second terminal of the thirty-seventh transistor Q37 and the first terminal of the thirty-eighth transistor Q38.

The second terminal of the forty-first transistor Q41 may be connected to the ground VSS, and the third terminal of the forty-first transistor Q41 may be connected to the second terminal of the forty-first transistor Q41.

A first terminal of the forty-second transistor Q42 may be connected to the power VCC, and a third terminal of the forty-second transistor Q42 may be connected to a first terminal of the forty-second transistor Q42. A first terminal of the forty-third transistor Q43 may be connected to a second terminal of the forty-second transistor Q42.

A first terminal of the forty-fourth transistor Q44 may be connected to the second terminal of the forty-third transistor Q43, a second terminal of the forty-fourth transistor Q44 may be connected to the ground VSS, a control terminal of the forty-third transistor Q43 may be connected to the control terminal of the forty-fourth transistor Q44, and a node thereof may be connected between the second terminal of the thirty-ninth transistor Q39 and the first terminal of the forty-fourth transistor Q40.

Wherein a first terminal of the forty-first transistor Q41 may be connected between a second terminal of the forty-third transistor Q43 and a first terminal of the forty-fourth transistor Q44. A control terminal of the forty-first transistor Q41 may be connected to a control terminal of the forty-second transistor Q42, and a node thereof may be connected to a second terminal of the twenty-sixth transistor Q26 and a first terminal of the twenty-seventh transistor Q27.

A first terminal of the forty-fifth transistor Q45 may be connected to the power supply VCC, and a third terminal of the forty-fifth transistor Q45 may be connected to a first terminal of the forty-fifth transistor Q45. A first terminal of the forty-sixth transistor Q46 may be connected to a second terminal of the forty-fifth transistor Q45. A second terminal of the forty-sixth transistor Q46 may be connected to the ground VSS, and a third terminal of the forty-sixth transistor Q46 may be connected to the second terminal of the forty-sixth transistor Q46.

Wherein a control terminal of the forty-fifth transistor Q45 may be connected to a control terminal of the forty-fifth transistor Q45, and a node thereof is connected between the second terminal of the forty-third transistor Q43 and the first terminal of the forty-fourth transistor Q44.

A first terminal of the forty-seventh transistor Q47 may be connected to the power VCC, and a third terminal of the forty-seventh transistor Q47 may be connected to a first terminal of the forty-seventh transistor Q47. A first terminal of the forty-eighth transistor Q48 may be connected to a second terminal of the forty-seventh transistor Q47, and a node thereof may serve as a first output terminal of the pulse generating circuit 121 to output the first pulse signal. A second terminal of the forty-eighth transistor Q48 may be connected to the ground VSS, and a third terminal of the forty-eighth transistor Q48 may be connected to the second terminal of the forty-eighth transistor Q48.

Wherein a control terminal of the forty-seventh transistor Q47 may be connected to a control terminal of the forty-seventh transistor Q47, and a node thereof is connected between the second terminal of the forty-fifth transistor Q45 and the second terminal of the forty-sixth transistor Q46.

A first terminal of the forty-ninth transistor Q49 may be connected to the power VCC, and a third terminal of the forty-ninth transistor Q49 may be connected to a first terminal of the forty-ninth transistor Q49. A first terminal of the fifty-fifth transistor Q50 may be connected to the second terminal of the forty-ninth transistor Q49, a second terminal of the twenty-seventh transistor Q27 may be connected to the ground VSS, a control terminal of the forty-ninth transistor Q49 may be connected to the control terminal of the fifty-fifth transistor Q50, and a node thereof may be connected between the second terminal of the twenty-sixth transistor Q26 and the first terminal of the twenty-seventh transistor Q27.

A first terminal of the fifty-first transistor Q51 may be connected to the power supply VCC, and a third terminal of the fifty-first transistor Q51 may be connected to a first terminal of the fifty-first transistor Q51. A first terminal of the fifty-second transistor Q52 may be connected to the second terminal of the fifty-first transistor Q51 through a third resistor R3, a second terminal of the fifty-second transistor Q52 may be connected to VSS, and a third terminal of the fifty-second transistor Q52 may be connected to the second terminal of the fifty-second transistor Q52.

Wherein a control terminal of the fifty-first transistor Q51 may be connected to a control terminal of the fifty-second transistor Q52, and a node thereof may be connected between the control terminal of the forty-ninth transistor Q49 and the control terminal of the fifty-second transistor Q50.

A first terminal of the fifty-third transistor Q53 may be connected to the power supply VCC, and a third terminal of the fifty-third transistor Q53 may be connected to a first terminal of the fifty-third transistor Q53. A first terminal of a fifty-fourth transistor Q54 may be connected to the second terminal of the fifty-third transistor Q53, and a third terminal of the fifty-fourth transistor Q54 may be connected to the third terminal of the fifty-third transistor Q53.

A first terminal of a fifty-fifth transistor Q55 may be connected to a first terminal of a fifty-fourth transistor Q54. A first terminal of the fifty-sixth transistor Q56 may be connected to the second terminal of the fifty-fifth transistor Q55, a second terminal of the fifty-sixth transistor Q56 may be connected to the ground VSS, a third terminal of the fifty-sixth transistor Q56 may be connected to the second terminal of the fifty-sixth transistor Q56, and a third terminal of the fifty-sixth transistor Q56 may be connected to the third terminal of the fifty-fifth transistor Q55.

Wherein, a control terminal of the fifty-third transistor Q53, a control terminal of the fifty-fourth transistor Q54, a control terminal of the fifty-fifth transistor Q55, and a control terminal of the fifty-sixth transistor Q56 may be connected, and a node thereof is connected to the third resistor R3 and the second terminal of the fifty-first transistor Q51. A first terminal of the third capacitor C3 may be connected between the second terminal of the fifty-first transistor Q51 and the control terminal of the fifty-fourth transistor Q54.

A first terminal of a thirty-fourth transistor Q34 may be connected between the second terminal of the fifty-third transistor Q53 and the first terminal of the fifty-fourth transistor Q54. A second terminal of the fifty-eighth transistor Q58 may be connected between a second terminal of the fifty-fifth transistor Q55 and a first terminal of the fifty-sixth transistor Q56, and a third terminal of the fifty-eighth transistor Q58 may be connected to ground VSS.

Wherein a control terminal of the fifty-seventh transistor Q57 may be connected to a control terminal of the fifty-eighth transistor Q58, and a node thereof may be connected to the second terminal of the fifty-third transistor Q53 and the first terminal of the fifty-fifth transistor Q55.

A first terminal of the fifty-ninth transistor Q59 may be connected to the power supply VCC, a second terminal of the fifty-ninth transistor Q59 may be connected to a first terminal of the fifty-eighth transistor Q58, a third terminal of the fifty-ninth transistor Q59 may be connected to a first terminal of the fifty-ninth transistor Q59, and a control terminal of the fifty-ninth transistor Q59 may be connected to a second terminal of the fifty-seventh transistor Q57.

A first terminal of the sixteenth transistor Q60 may be connected to the power supply VCC, and a third terminal of the sixteenth transistor Q60 may be connected to a first terminal of the sixteenth transistor Q60. A first terminal of the sixty-first transistor Q61 may be connected to the second terminal of the sixty-first transistor Q60, a second terminal of the sixty-first transistor Q61 may be grounded, and a third terminal of the sixty-first transistor Q61 may be connected to the second transistor of the sixty-first transistor Q61.

Wherein a control terminal of the sixty-fourth transistor Q60 and a control terminal of the sixty-first transistor Q61 may be connected, and a node thereof may be connected between the control terminal of the fifty-seventh transistor Q57 and the control terminal of the fifty-eighth transistor Q58.

A first terminal of the sixty-second transistor Q62 may be connected to the power VCC, and a third terminal of the sixty-second transistor Q62 may be connected to a first terminal of the sixty-second transistor Q62. A first terminal of the sixty-third transistor Q63 may be connected to a second terminal of the sixty-second transistor Q62. A second terminal of the sixty-third transistor Q63 may be coupled to ground VSS and a third terminal of the sixty-third transistor Q63 may be coupled to the second terminal of the sixty-third transistor Q63.

Wherein a control terminal of the sixty-second transistor Q62 may be connected to a control terminal of the sixty-second transistor Q62, a node of which is connected between the second terminal of the sixty-transistor Q60 and the first terminal of the sixty-first transistor Q61.

A second terminal of the sixty-fourth transistor Q64 may be connected to ground VSS, and a third terminal of the sixty-fourth transistor Q64 may be connected to the second terminal of the sixty-fourth transistor Q64.

A first terminal of the sixty-fifth transistor Q65 may be connected to the power supply VCC, and a third terminal of the sixty-fifth transistor Q65 may be connected to a first terminal of the sixty-fifth transistor Q65. A first terminal of a sixty-sixth transistor Q66 may be connected to a second terminal of a sixty-fifth transistor Q65.

A first terminal of the sixty-seventh transistor Q67 may be connected to the second terminal of the sixty-sixth transistor Q66, a second terminal of the sixty-seventh transistor Q67 may be connected to the ground VSS, a control terminal of the sixty-sixth transistor Q66 may be connected to the control terminal of the sixty-seventh transistor Q67, and a node thereof may be connected between the second terminal of the sixty-second transistor Q62 and the first terminal of the forty-fourth transistor Q40.

Wherein the first terminal of the sixty-fourth transistor Q64 may be connected between the second terminal of the sixty-sixth transistor Q66 and the first terminal of the sixty-seventh transistor Q67. A control terminal of the sixty-fourth transistor Q64 may be connected to a control terminal of the sixty-fifth transistor Q65, and a node thereof may be connected to the second terminal of the forty-ninth transistor Q49 and the first terminal of the fifty-fifth transistor Q50.

A first terminal of the sixty-eight transistor Q68 may be connected to the power supply VCC, and a third terminal of the sixty-eight transistor Q68 may be connected to a first terminal of the sixty-eight transistor Q68. A first terminal of the sixty-ninth transistor Q69 may be connected to a second terminal of the sixty-eighth transistor Q68. A second terminal of the sixty-ninth transistor Q69 may be connected to ground VSS, and a third terminal of the sixty-ninth transistor Q69 may be connected to the second terminal of the sixty-ninth transistor Q69.

Wherein a control terminal of the sixty-eight transistor Q68 may be connected to a control terminal of the sixty-nine transistor Q69, 9, with a node connected between the second terminal of the sixty-six transistor Q66 and the first terminal of the sixty-seven transistor Q67.

A first terminal of the seventy transistor Q70 may be connected to the power supply VCC, and a third terminal of the seventy transistor Q70 may be connected to a first terminal of the seventy transistor Q70. A first terminal of the seventy-first transistor Q71 may be connected to a second terminal of the seventy-first transistor Q70, and a node thereof may serve as a second output terminal of the pulse generating circuit 121 to output the second pulse signal. A second terminal of the seventy-first transistor Q71 may be connected to the ground VSS, and a third terminal of the seventy-first transistor Q71 may be connected to the second terminal of the seventy-first transistor Q71.

Wherein a control terminal of the seventy-seventh transistor Q70 may be connected to a control terminal of the seventy-first transistor Q71, a node of which is connected between the second terminal of the sixty-eight transistor Q68 and the second terminal of the sixty-nine transistor Q69.

In the present embodiment, the twenty-sixth transistor Q26, the twenty-eighth transistor Q28, the thirty-seventh transistor Q37, the thirty-ninth transistor Q39, the forty-second transistor Q42, the forty-third transistor Q43, the forty-fifth transistor Q45, the forty-seventh transistor Q47, the forty-ninth transistor Q49, the fifty-first transistor Q51, the fifty-third transistor Q53, the fifty-fourth transistor Q54, the fifty-seventh transistor Q57, the fifty-ninth transistor Q59, the sixteenth transistor Q60, the sixteenth transistor Q62, the sixteenth transistor Q65, the sixteenth transistor Q66, the sixty-eighth transistor Q68, and the seventeenth transistor Q70 may be PMOS transistors.

The twenty-seventh transistor Q27, the twenty-ninth transistor Q29, the thirty-second transistor Q32, the thirty-third transistor Q33, the thirty-fifth transistor Q35, the thirty-eighth transistor Q38, the forty-fourth transistor Q40, the forty-first transistor Q41, the forty-fourth transistor Q44, the forty-sixth transistor Q46, the forty-eighth transistor Q48, the fifty-fifth transistor Q50, the second fifty transistor Q52, the fifty-fifth transistor Q55, the fifty-sixth transistor Q56, the fifty-eighth transistor Q58, the sixty-first transistor Q61, the sixty-third transistor Q63, the sixty-fourth transistor Q64, the sixty-seventh transistor Q67, the sixty-ninth transistor Q69, and the seventy-first transistor Q71 may be NMOS transistors.

In the twenty-sixth to seventy-first transistors Q26 to Q71, the control terminal may be a gate of the MOS transistor, the first terminal may be a source/drain of the MOS transistor, the second terminal may be a source/drain of the MOS transistor, and the third terminal may be a substrate electrode of the MOS transistor.

The pulse generating circuit 121 may be used in conjunction with the high voltage output circuit 122. The pulse generating circuit 121 generates two paths of pulses with pulse widths of 300 ns-600 ns, respectively and rapidly switches on and off two LDMOS (not shown), transmits a control signal to a high basin region, and then restores the pulse signal to one path of signal through an RS flip-flop circuit (not shown), thereby controlling the high-voltage output of the high-voltage output circuit 122.

Referring to fig. 6, fig. 6 is a schematic circuit diagram of an embodiment of the high voltage output circuit in fig. 1. In the present embodiment, the high voltage output circuit 122 may include the following:

a first terminal of the seventy-second transistor Q72 may be connected to a high voltage power supply, and a third terminal of the seventy-second transistor Q72 may be connected to a first terminal of the seventy-second transistor Q72. A first terminal of the seventy-third transistor Q73 may be connected to the second terminal of the seventy-second transistor Q72, a second terminal of the seventy-third transistor Q73 may be grounded VS, and a third terminal of the seventy-third transistor Q73 may be connected to the second terminal of the seventy-third transistor Q73. Wherein a control terminal of the seventy-second transistor Q72 may be connected with a control terminal of the seventy-third transistor Q73.

A first terminal of the seventy-fourth transistor Q74 may be connected to a high voltage power supply, and a third terminal of the seventy-fourth transistor Q74 may be connected to a first terminal of the seventy-fourth transistor Q74. A first terminal of the seventy-fifth transistor Q75 may be connected to the second terminal of the seventy-fourth transistor Q74, a second terminal of the seventy-fifth transistor Q75 may be connected to the ground VS, and a third terminal of the seventy-fifth transistor Q75 may be connected to the second terminal of the seventy-fifth transistor Q75. Wherein a control terminal of the seventy-fourth transistor Q74 may be connected with a control terminal of the seventy-fifth transistor Q75, and a node thereof may be connected between the first terminal of the seventy-third transistor Q73 and the second terminal of the seventy-second transistor Q72.

A first terminal of the seventy-sixth transistor Q76 may be connected to a high voltage power supply, and a third terminal of the seventy-sixth transistor Q76 may be connected to a first terminal of the seventy-sixth transistor Q76. A first terminal of the seventy-seventh transistor Q77 may be connected to the second terminal of the seventy-sixth transistor Q76, a second terminal of the seventy-seventh transistor Q77 may be connected to the ground VS, and a third terminal of the seventy-seventh transistor Q77 may be connected to the second terminal of the seventy-seventh transistor Q77. Wherein a control terminal of the seventy-sixth transistor Q76 may be connected with a control terminal of the seventy-seventh transistor Q77, and a node thereof may be connected between the first terminal of the seventy-fifth transistor Q75 and the second terminal of the seventy-fourth transistor Q74.

The third terminal of the seventy-eighth transistor Q78 may be connected to the first terminal of the seventy-eighth transistor Q78. A first terminal of the seventy-ninth transistor Q79 may be connected to the second terminal of the seventy-eighth transistor Q78, a second terminal of the seventy-ninth transistor Q79 may be connected to the ground VS, and a third terminal of the seventy-ninth transistor Q79 may be connected to the second terminal of the seventy-ninth transistor Q79. Wherein a control terminal of the seventy-eighth transistor Q78 may be connected with a control terminal of the seventy-ninth transistor Q79.

The third terminal of the eighty-th transistor Q80 may be connected to the first terminal of the eighty-th transistor Q80. A first terminal of the eighty-first transistor Q81 may be connected to the second terminal of the eighty-first transistor Q80, a second terminal of the eighty-first transistor Q81 may be connected to the ground VS, and a third terminal of the eighty-first transistor Q81 may be connected to the second terminal of the eighty-first transistor Q81. Wherein a control terminal of the eighty-th transistor Q80 may be connected with a control terminal of the eighty-first transistor Q81, and a node thereof may be connected between the first terminal of the seventy-ninth transistor Q79 and the second terminal of the seventy-eighth transistor Q78.

The third terminal of the eighty-second transistor Q82 may be connected to the first terminal of the eighty-second transistor Q82. A first terminal of the eighty-third transistor Q83 may be connected to the second terminal of the eighty-second transistor Q82, a second terminal of the eighty-third transistor Q83 may be grounded VS, and a third terminal of the eighty-third transistor Q83 may be connected to the second terminal of the eighty-third transistor Q83. Wherein a control terminal of the eighty-second transistor Q82 may be connected with a control terminal of the eighty-third transistor Q83, and a node thereof may be connected between the first terminal of the eighty-first transistor Q81 and the second terminal of the eighty-third transistor Q80.

Wherein, a first terminal of the seventy-eight transistor Q78, a first terminal of the eighty transistor Q80, and a first terminal of the eighty-two transistor Q82 may be connected, a node thereof may be connected to a first terminal of the fourth resistor R4, and a connection node therebetween may be connected to the high voltage power supply.

A first terminal of the eighty-fourth transistor Q84 may be connected to a high voltage power supply, a third terminal of the eighty-fourth transistor Q84 may be connected to a first terminal of the eighty-fourth transistor Q84, and a control terminal of the eighty-fourth transistor Q84 may be connected between a first terminal of the seventy-seventh transistor Q77 and a second terminal of the seventy-sixth transistor Q76.

A first terminal of the eighty-fifth transistor Q85 may be connected to the second terminal of the eighty-fourth transistor Q84, a second terminal of the eighty-fifth transistor Q85 may be connected to the ground VS, and a third terminal of the eighty-fifth transistor Q85 may be connected to the second terminal of the eighty-fifth transistor Q85. A control terminal of the eighty-fifth transistor Q85 may be connected between a connection node between the second terminal of the eighty-fifth transistor Q82 and the first terminal of the eighty-third transistor Q83 and the second terminal of the fourth resistor.

An anode of the first diode D1 may be connected between the second terminal of the eighty-fourth transistor Q84 and the first terminal of the eighty-fifth transistor Q85, and a cathode of the first diode D1 may be connected to a high voltage power supply. The cathode of the second diode D2 may be connected to the anode of the first diode D1, and the anode of the second diode D2 may be grounded. The cathode of the third diode D3 may be connected to a high voltage source and the anode of the third diode D3 may be connected to ground VS. The first diode D1, the second diode D2, and the third diode D3 can limit the voltage direction in the high voltage output circuit 122 to prevent reverse current.

A connection node between the control terminal of the seventy-second transistor Q72 and the control terminal of the seventy-third transistor Q73 may be connected to a connection node between the control terminal of the seventy-eighth transistor Q78 and the control terminal of the seventy-ninth transistor Q79, and the connection node may serve as an input terminal of the high voltage output circuit 122 to receive the pulse signal. A connection node between the second terminal of the eighty-fourth transistor Q84 and the first terminal of the eighty-fifth transistor Q85 may serve as an output terminal of the high voltage output circuit 122 to output a high voltage output signal.

In the present embodiment, the seventy-second transistor Q72, the seventy-fourth transistor Q74, the seventy-sixth transistor Q76, the seventy-eighth transistor Q78, the eighty-fourth transistor Q80, the eighty-second transistor Q82, and the eighty-fourth transistor Q84 may be PMOS transistors.

The seventy-third transistor Q73, the seventy-fifth transistor Q75, the seventy-seventh transistor Q77, the seventy-ninth transistor Q79, the eighty-first transistor Q81, the eighty-third transistor Q83, and the eighty-fifth transistor Q85 may be NMOS transistors.

In the seventy-second to eighty-fifth transistors Q72 to Q85, the control terminal may be a gate of the MOS transistor, the first terminal may be a source/drain of the MOS transistor, the second terminal may be a source/drain of the MOS transistor, and the third terminal may be a substrate electrode of the MOS transistor.

When the control terminal of the eighty-fourth transistor Q84 receives a low level during the operation of the high voltage output circuit 122, the eighty-fourth transistor Q84 is turned on, and the high voltage power flows from the first terminal to the second terminal of the eighty-fourth transistor Q84, and is output from the output terminal of the high voltage output circuit 122.

With continued reference to fig. 1, the second output circuit 130 may be a low voltage output circuit 130. The low voltage output circuit 130 may be configured to receive the intermediate signal and generate a low voltage output signal based on the intermediate signal.

Referring to fig. 7, fig. 7 is a circuit structure diagram of an embodiment of the low voltage output circuit in fig. 1. In this embodiment, the low voltage output circuit 130 may include the following:

a first terminal of the eighty-sixth transistor Q86 may be connected to the power supply VCC, and a third terminal of the eighty-sixth transistor Q86 may be connected to a first terminal of the eighty-sixth transistor Q86. A first terminal of the eighty-seventh transistor Q87 may be connected to the second terminal of the eighty-sixth transistor Q86, a second terminal of the eighty-seventh transistor Q87 may be connected to the common terminal COM, and a third terminal of the eighty-seventh transistor Q87 may be connected to the second terminal of the eighty-seventh transistor Q87. Wherein a control terminal of the eighty-sixth transistor Q86 may be connected with a control terminal of the eighty-seventh transistor Q87.

A first terminal of the eighty-eight transistor Q88 may be connected to the power supply VCC, and a third terminal of the eighty-eight transistor Q88 may be connected to a first terminal of the eighty-eight transistor Q88. A first terminal of the eighty-ninth transistor Q89 may be connected to the second terminal of the eighty-eighth transistor Q88, a second terminal of the eighty-ninth transistor Q89 may be connected to the common terminal COM, and a third terminal of the eighty-ninth transistor Q89 may be connected to the second terminal of the eighty-ninth transistor Q89. Wherein a control terminal of the eighty-eight transistor Q88 may be connected with a control terminal of the eighty-nine transistor Q89, and a node thereof may be connected between the first terminal of the eighty-seven transistor Q87 and the second terminal of the eighty-six transistor Q86.

A first terminal of the ninety-high transistor Q90 may be connected to a power supply VCC, and a third terminal of the ninety-high transistor Q90 may be connected to a first terminal of the ninety-high transistor Q90. A first terminal of the ninety-first transistor Q91 may be connected to a second terminal of the ninety-first transistor Q90, a second terminal of the ninety-first transistor Q91 may be connected to the common terminal COM, and a third terminal of the ninety-first transistor Q91 may be connected to a second terminal of the ninety-first transistor Q91. Wherein a control terminal of the ninety-th transistor Q90 may be connected with a control terminal of the ninety-first transistor Q91, and a node thereof may be connected between a first terminal of the eighty-ninth transistor Q89 and a second terminal of the eighty-eighth transistor Q88.

A first terminal of the ninety second transistor Q92 may be connected to a power supply VCC, and a third terminal of the ninety second transistor Q92 may be connected to a first terminal of the ninety second transistor Q92. A first terminal of the ninety-third transistor Q93 may be connected to a second terminal of the ninety-second transistor Q92, a second terminal of the ninety-third transistor Q93 may be coupled to the common terminal COM, and a third terminal of the ninety-third transistor Q93 may be connected to a second terminal of the ninety-third transistor Q93. Wherein a control terminal of the ninety-second transistor Q92 may be connected with a control terminal of the ninety-third transistor Q93.

A first terminal of the ninety-fourth transistor Q94 may be connected to a power supply VCC and a third terminal of the ninety-fourth transistor Q94 may be connected to a first terminal of the ninety-fourth transistor Q94. A first terminal of the ninety-fifth transistor Q95 may be connected to a second terminal of the ninety-fourth transistor Q94, a second terminal of the ninety-fifth transistor Q95 may be coupled to the common terminal COM, and a third terminal of the ninety-fifth transistor Q95 may be connected to a second terminal of the ninety-fifth transistor Q95. Wherein a control terminal of the ninety-fourth transistor Q94 may be connected with a control terminal of the ninety-fifth transistor Q95, and a node thereof may be connected between a first terminal of the ninety-third transistor Q93 and a second terminal of the ninety-second transistor Q92.

A first terminal of the ninety-sixth transistor Q96 may be connected to a power supply VCC, and a third terminal of the ninety-sixth transistor Q96 may be connected to a first terminal of the ninety-sixth transistor Q96. A first terminal of the ninety-seventh transistor Q97 may be connected to a second terminal of the ninety-sixth transistor Q96, a second terminal of the ninety-seventh transistor Q97 may be coupled to the common terminal COM, and a third terminal of the ninety-seventh transistor Q97 may be connected to a second terminal of the ninety-seventh transistor Q97. Wherein a control terminal of the ninety-sixth transistor Q96 may be connected with a control terminal of the ninety-seventh transistor Q97, and a node thereof may be connected between a first terminal of the ninety-fifth transistor Q95 and a second terminal of the ninety-fourth transistor Q94.

A first terminal of the ninety-eight transistor Q98 may be connected to a power supply VCC, a third terminal of the ninety-eight transistor Q98 may be connected to a first terminal of the ninety-eight transistor Q98, and a control terminal of the ninety-eight transistor Q98 may be connected between the first terminal of the ninety-first transistor Q91 and the second terminal of the ninety-transistor Q90.

A first terminal of the ninety-ninth transistor Q99 may be connected to a second terminal of the ninety-eighth transistor Q98, a second terminal of the ninety-ninth transistor Q99 may be coupled to the common terminal COM, and a third terminal of the ninety-ninth transistor Q99 may be connected to a second terminal of the ninety-ninth transistor Q99. The control terminal of the ninety-ninth transistor Q99 may be connected between the second terminal of the ninety-sixth transistor Q96 and the first terminal of the ninety-seventh transistor Q97.

Wherein a first terminal of the fifth resistor R5 may be the power supply VCC, and a second terminal of the fifth resistor R5 may be connected between a node between the second terminal of the ninety-sixth transistor Q96 and the first terminal of the ninety-seventh transistor Q97 and the control terminal of the ninety-ninth transistor Q99.

A cathode of the fourth diode D4 may be connected to the power source VCC, an anode of the fourth diode D4 may be connected to a cathode of the fifth diode D5, and an anode of the fifth diode D5 may be connected to the common terminal COM. Alternatively, the common terminal COM may be a ground terminal. Among them, the fourth diode D4 and the fifth diode D5 can limit the voltage direction in the low voltage output circuit 130 and prevent reverse current.

The connection node between the control terminal of the eighty-sixth transistor Q86 and the control terminal of the eighty-seventh transistor Q87 may be connected to the connection node between the control terminal of the ninety-second transistor Q92 and the control terminal of the ninety-third transistor Q93, and the connection node may serve as an input terminal of the low voltage output circuit 130 to receive the pulse signal. A connection node between the second terminal of the ninety-eight transistor Q98 and the first terminal of the ninety-nine transistor Q99 may serve as an output terminal of the low voltage output circuit 130 to output a low voltage output signal.

In the present embodiment, the eighty-sixth transistor Q86, the eighty-eighth transistor Q88, the ninety-th transistor Q90, the ninety-second transistor Q92, the ninety-fourth transistor Q94, the ninety-sixth transistor Q96, and the ninety-eighth transistor Q98 may be PMOS transistors.

The eighty-seventh transistor Q87, the eighty-ninth transistor Q89, the ninety-first transistor Q91, the ninety-third transistor Q93, the ninety-fifth transistor Q95, the ninety-seventh transistor Q97, and the ninety-ninth transistor Q99 may be NMOS transistors.

In the eighty-sixth to ninety-ninth transistors Q86 to Q99, the control terminal may be a gate of the MOS transistor, the first terminal may be a source/drain of the MOS transistor, the second terminal may be a source/drain of the MOS transistor, and the third terminal may be a substrate electrode of the MOS transistor.

When the control terminal of the ninety-eight transistor Q98 receives a low level during the operation of the low voltage output circuit 130, the ninety-eight transistor Q98 is turned on, and the power VCC flows from the first terminal to the second terminal of the ninety-eight transistor Q98 and is output from the output terminal of the low voltage output circuit 130.

In addition, the driving circuit of the present embodiment includes a total of three ground points, which are a VSS input ground, a VS high voltage output ground and a COM low voltage output ground. The three are obviously different.

In the present application, the Transistor may be not only a MOS Transistor in the above embodiments, but also a BJT (Bipolar Junction Transistor), and the type of the Transistor is not limited herein.

In the related art driving circuit, the high-voltage and low-voltage control signals are passed through the respective rectifying and filtering circuits and the level shifting circuit, so that there is a problem of matching the high-voltage and low-voltage control signals. In addition, in such a driving circuit, a penetration preventing protection circuit needs to be additionally provided to improve safety and reliability of the entire system. Compared with the related technology, the high-voltage and low-voltage control circuit has the advantages that the same rectifying and filtering circuit and the same level shifting circuit can be adopted, the matching problem of high-voltage and low-voltage control signals is solved, and the matching performance of the high-voltage and low-voltage control signals is better; meanwhile, the problem of penetration of an upper bridge and a lower bridge is solved by utilizing an edge trigger circuit, a selection switch, a rectification filter circuit and the like, so that the safety is greatly improved; in addition, the circuit structure is simple, the area of a chip bearing the driving circuit is small, and the cost is low.

Based on the above-mentioned drive circuit 100, this application also proposes a household appliance. Referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of a household appliance according to the present application. The household appliance 200 may include the driving circuit 200 described above. The household appliance 200 may include, but is not limited to, a refrigerator, a television, a washing machine, etc., which are not described in detail herein.

It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. In addition, for convenience of description, only a part of structures related to the present application, not all of the structures, are shown in the drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A driver circuit, characterized in that the driver circuit comprises:

a signal processing circuit configured to process an input signal to obtain an intermediate signal;

a first output circuit;

a second output circuit;

and the selection circuit is connected with the signal processing circuit and is configured to control the signal processing circuit to select to be connected with the first output circuit or the second output circuit according to the input signal so that the first output circuit or the second output circuit processes the intermediate signal to obtain an output signal.

2. The driving circuit according to claim 1, further comprising:

a first input terminal configured to input a first signal;

a second input terminal configured to input a second signal;

the selection circuit is connected to the first input terminal and the second input terminal, and the selection circuit is configured to control the signal processing circuit to be connected to the first output circuit in response to receiving the first signal or to control the signal processing circuit to be connected to the second output circuit in response to receiving the second signal.

3. The drive circuit according to claim 2,

the selection circuit includes:

the edge trigger circuit is connected with the first input end and the second input end and used for generating a trigger signal according to the first signal or the second signal;

the switch circuit comprises a first connecting end, a second connecting end and a control end, wherein the first connecting end is connected with the signal processing circuit, the control end is used for inputting the trigger signal, and the second connecting end is used for selecting and connecting the first output circuit or the second output circuit according to the trigger signal.

4. The driving circuit of claim 3, wherein the edge triggered circuit comprises a JK flip-flop comprising:

a J signal input end connected with the first input end;

the K signal input end is connected with the second input end;

and the second connecting end of the switch circuit is used for selecting one of the first output circuit and the second output circuit according to the trigger signal output by the JK trigger.

5. The drive circuit according to claim 1, wherein the signal processing circuit comprises:

the rectification filter circuit is connected with the first input end and the second input end, and is used for receiving the input signal from the first input end or the second input end, rectifying and filtering the input signal and outputting a rectification filter signal;

and the level shift circuit is connected with the output end of the rectification filter circuit, receives the rectification filter signal, carries out level shift processing on the rectification filter signal and outputs the intermediate signal.

6. The driving circuit according to claim 5, wherein the rectifying and filtering circuit comprises:

a first transistor, a control terminal of the first transistor is used for receiving the input signal, and a first terminal of the first transistor is used for connecting a power supply;

a control end of the second transistor is connected with a control end of the first transistor, the control end of the second transistor is used for receiving the input signal, a first end of the second transistor is used for being connected with a second end of the first transistor, and a second end of the second transistor is grounded;

a first capacitor, a first end of the first capacitor is connected between a first end of the second transistor and a second end of the first transistor through a first resistor, and a second end of the first capacitor is grounded;

a third transistor, a first end of the third transistor being connected to the power supply;

a first end of the fourth transistor is connected with the second end of the third transistor, and a third end of the fourth transistor is connected with the third end of the third transistor;

a fifth transistor, a first terminal of the fifth transistor being connected to a second terminal of the fourth transistor;

a first end of the sixth transistor is connected with the second end of the fifth transistor, the second end of the sixth transistor is grounded, and a third end of the sixth transistor is connected with the third end of the fifth transistor;

the control end of the third transistor, the control end of the fourth transistor, the control end of the fifth transistor and the control end of the sixth transistor are connected, and nodes of the control ends are connected between the first resistor and the first end of the first capacitor;

a seventh transistor, a first terminal of which is connected between a second terminal of the third transistor and a first terminal of the fourth transistor, and a third terminal of which is connected to the power supply;

a second terminal of the eighth transistor is connected between the second terminal of the fifth transistor and the first terminal of the sixth transistor, and a third terminal of the eighth transistor is grounded;

wherein a control terminal of the seventh transistor is connected to a control terminal of the eighth transistor, and a node thereof is connected between a first terminal of the fifth transistor and a second terminal of the fourth transistor;

a ninth transistor, a control terminal of which is connected to the second terminal of the seventh transistor and to ground, a first terminal of which is connected to the power supply, and a second terminal of which is connected to the first terminal of the eighth transistor;

a tenth transistor, a first terminal of which is connected to the power supply;

a tenth transistor, a first terminal of which is connected to the second terminal of the sixth transistor, and a second terminal of which is grounded;

wherein a control terminal of the tenth transistor is connected to a control terminal of the eleventh transistor, and a node thereof is connected between a control terminal of the seventh transistor and a control terminal of the eighth transistor;

a twelfth transistor, a first end of the twelfth transistor being connected to the power supply;

a thirteenth transistor, a first end of the thirteenth transistor is connected to the second end of the twelfth transistor, a node of the thirteenth transistor is used as an output end of the rectifying and filtering circuit, and a second end of the thirteenth transistor is grounded;

wherein a control terminal of the twelfth transistor is connected to a control terminal of the thirteenth transistor, and a node thereof is connected between the second terminal of the tenth transistor and the first terminal of the eleventh transistor.

7. The drive circuit according to claim 6,

the rectification filter circuit further comprises a protection circuit, and the protection circuit comprises:

a first not gate, an input of the first not gate receiving the first signal;

a first input end of the first AND gate is connected with an output end of the first NOT gate, and a second input end of the first AND gate receives the second signal;

a second not gate having an input receiving the second signal;

a first input end of the second AND gate is connected with an output end of the second NOT gate, and a second input end of the second AND gate receives the first signal;

the first input end of the first OR gate is connected with the output end of the first AND gate, the second input end of the first OR gate is connected with the output end of the second AND gate, and the output end of the first OR gate is connected between the control end of the first transistor and the control end of the second transistor.

8. The driving circuit according to claim 2, wherein a voltage value of the first signal is greater than a voltage value of the second signal, the first signal is a high voltage signal, and the second signal is a low voltage signal;

the first output circuit includes:

the pulse generating circuit is used for receiving the intermediate signal and generating a pulse signal according to the intermediate signal;

and the high-voltage output circuit is used for receiving the pulse signal and generating a high-voltage output signal according to the pulse signal.

9. The driving circuit according to claim 8, wherein the second output circuit comprises:

and the low-voltage output circuit is used for receiving the intermediate signal and generating a low-voltage output signal according to the intermediate signal.

10. A domestic appliance comprising a drive circuit as claimed in any one of the preceding claims 1 to 9.