CN112117192A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN112117192A
CN112117192A CN201910545011.0A CN201910545011A CN112117192A CN 112117192 A CN112117192 A CN 112117192A CN 201910545011 A CN201910545011 A CN 201910545011A CN 112117192 A CN112117192 A CN 112117192A
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CN
China
Prior art keywords
etching
fin
layer
fin portion
isolation layer
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CN201910545011.0A
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Chinese (zh)
Inventor
张海洋
郑二虎
洪中山
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910545011.0A priority Critical patent/CN112117192A/en
Publication of CN112117192A publication Critical patent/CN112117192A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a first fin part and a second fin part which are separately arranged; forming an isolation layer on the substrate, wherein the isolation layer fills a gap between the first fin portion and the second fin portion, and the top of the isolation layer is flush with the top of the first fin portion and the top of the second fin portion; forming a mask layer on the first fin portion, wherein the mask layer covers part of the surface of the top of the isolation layer; and etching the isolation layer by using the mask layer as a mask and adopting an atomic layer etching process, so that the isolation layer is not deviated when being etched, and the first fin part is not damaged. Furthermore, the second fin portion can be completely removed, so that the finally formed fin portion is uniform, and the performance of the semiconductor device is improved.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are developed towards higher element density and higher integration level, and the size of the gate of a planar transistor is smaller and smaller, so that the control capability of the gate on channel current is weakened, a short channel effect is easily generated, the problem of leakage current is caused, and the electrical performance of the semiconductor devices is further influenced.
In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and a dielectric layer, wherein the fin part and the dielectric layer are positioned on the surface of a semiconductor substrate, the dielectric layer covers a part of the side wall of the fin part, and the surface of the dielectric layer is lower than the top of the fin part; the grid electrode structures are positioned on the surface of the dielectric layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, as the density and size of semiconductor devices increase, the electrical performance and yield of semiconductor devices formed by finfet devices still need to be improved.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which can improve the performance of a semiconductor device and the yield.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a first fin part and a second fin part which are separately arranged; forming an isolation layer on the substrate, wherein the isolation layer fills a gap between the first fin portion and the second fin portion, and the top of the isolation layer is flush with the top of the first fin portion and the top of the second fin portion; forming a mask layer on the first fin portion, wherein the mask layer covers part of the surface of the top of the isolation layer; etching the isolation layer by using the mask layer as a mask through an atomic layer etching process until the substrate is exposed; and removing the second fin part.
Optionally, the parameters of the atomic layer etching process are as follows: the etching gas comprises He and NH3And NF3Etching chamberThe chamber pressure is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
Optionally, the isolation layer is made of silicon oxide, silicon oxycarbide, silicon oxycarbonitride, or silicon oxynitride.
Optionally, the process of forming the isolation layer on the substrate includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Optionally, the mask layer is made of silicon nitride or silicon oxycarbide, silicon oxycarbonitride or silicon oxynitride.
Optionally, before forming the isolation layer, the method further includes: and forming a protective layer on the top surfaces of the first fin portion and the second fin portion.
Optionally, the protective layer is made of silicon nitride.
Optionally, removing the second fin portion and etching the isolation layer are performed simultaneously.
Optionally, the second fin portion is removed by using an atomic layer etching process.
Optionally, the second fin portion removing process is performed after the isolation layer is etched.
Optionally, the process of removing the second fin portion is a fin portion cutting process.
Optionally, after removing the second fin portion, the method further includes: removing the mask layer, and etching the substrate by taking the first fin part and the residual isolating layer as masks to form a groove; and continuously etching the substrate along the groove by using the first fin part and the rest of the isolation layer as masks to widen the groove.
Optionally, the process for forming the groove is dry etching, and the process parameters are as follows: the etching gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
OptionalThe groove is transversely widened by adopting a back etching method, and the technological parameters are as follows: the gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the top of the isolation layer is flush with the top of the first fin portion and the top of the second fin portion, and the mask layer is prevented from being formed in a deviating mode. The mask layer covers part of the surface of the top of the isolation layer; the mask layer is used as a mask, the isolation layer is etched by adopting an atomic layer etching process, and the directionality of the atomic layer etching process is good, so that the isolation layer cannot deviate during etching, the first fin part cannot be damaged, and the second fin part can be completely removed; and further, the finally formed fin part is uniform, and the performance of the semiconductor device is improved.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 11 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention;
fig. 12 to 15 are schematic structural views illustrating a process of forming a semiconductor structure according to another embodiment of the present invention.
Detailed Description
As described in the background, as the density of semiconductor devices increases and the size decreases, the performance of the resulting finfet is poor and the reliability is low. The following description will be made with reference to the accompanying drawings.
Fig. 1 to 3 are schematic cross-sectional views illustrating a process of forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, and the substrate 100 has a first fin 101 and a second fin 102 separately arranged thereon. The first fin 101 is located around the second fin 102.
Referring to fig. 2, a dielectric layer 103 is formed on the substrate 100, the dielectric layer 103 is made of spin-on carbon (SoC), the dielectric layer 103 covers the first fin portion 101 and the second fin portion 102, and the dielectric layer 103 fills a gap between the first fin portion 101 and the second fin portion 102.
Forming an anti-reflection layer (Si-ARC)104 on the upper surface of the dielectric layer 103, wherein the anti-reflection layer 104 covers a part of the surface of the top of the dielectric layer 103; a photoresist layer 105 is formed on the upper surface of the anti-reflection layer 104.
Referring to fig. 3, the dielectric layer 103 is etched by using the photoresist layer 105 and the anti-reflection layer 104 as masks, and the second fin portion 102 is removed.
It should be noted that the first fin 101 is an effective fin required for forming a device, and the second fin 102 is a dummy fin additionally formed to overcome a loading effect. The dummy fins need to be removed, i.e., the second fins 102 need to be removed.
Research shows that in the process of removing the second fin portion 102, the dielectric layer 103 is etched by using the photoresist layer 105 and the anti-reflection layer 104 as masks, and since the dielectric layer 103 completely covers the tops of the first fin portion 101 and the second fin portion 102 before the photoresist layer 105 and the anti-reflection layer 104 are formed, there is a possibility that light sensing deviation occurs and deviation occurs when the photoresist layer 105 and the anti-reflection layer 104 are formed; meanwhile, when the conventional etching process is used for etching downwards and deeper, the electrode in the etching equipment excites the plasma to perform directional bombardment at high temperature and high pressure to etch the dielectric layer 103, however, deviation is difficult to avoid in the process, and finally, part of the material of the first fin portion 101 is etched after etching, the appearance of the first fin portion 101 is damaged, and part of the material of the second fin portion 102 which needs to be etched is remained, so that the final fin portion width is different, and the performance of the fin field effect transistor is further influenced.
In order to solve the technical problem, an isolation layer is formed on the substrate, the isolation layer fills a gap between the first fin portion and the second fin portion, and the top of the isolation layer is flush with the top of the first fin portion and the top of the second fin portion; forming a mask layer on the first fin portion, wherein the mask layer covers part of the surface of the top of the isolation layer; the top of the isolation layer is flush with the top of the first fin portion and the top of the second fin portion, and the mask layer is prevented from being formed in a deviating mode. Etching the isolation layer by using the mask layer as a mask through an atomic layer etching process until the substrate is exposed; the etching rate of the atomic layer etching process in the vertical direction is far greater than the etching rate in the transverse direction, so that the isolation layer is not deviated during etching, the first fin portion is not damaged, and further, the second fin portion can be completely removed. The finally formed fin part is uniform, and the performance of the device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
First embodiment
Fig. 4 to 11 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided, wherein the substrate 200 has a first fin 201 and a second fin 202 which are separately arranged; a protection layer 300 is formed on the top surfaces of the first fin 201 and the second fin 202.
The forming steps of the substrate 200, the first fin portion 201, the second fin portion 202 and the protection layer 300 include: providing a semiconductor substrate (not shown); a first patterned mask layer (not shown) is formed on the semiconductor substrate. The first patterned mask layer defines positions and shapes of the first fin portion 201 and the second fin portion 202; and etching the semiconductor substrate by using the first patterned mask layer as a mask to form the substrate 200, the first fin portion 201, the second fin portion 202 and the protection layer 300 on the tops of the first fin portion 201 and the second fin portion 202.
The semiconductor substrate is made of semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide and the like, wherein the silicon materials comprise monocrystalline silicon, polycrystalline silicon or amorphous silicon. The semiconductor substrate can also be a semiconductor-on-insulator structure, the semiconductor-on-insulator structure comprises an insulator and a semiconductor material layer positioned on the insulator, and the material of the semiconductor material layer comprises semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide and the like.
In this embodiment, the material of the semiconductor substrate is monocrystalline silicon. Namely, the material of the substrate 200, the first fin portion 201, and the second fin portion 202 is monocrystalline silicon.
In this embodiment, the protection layer 300 is used to protect the tops of the first fin portion 201 and the second fin portion 202 from being damaged when the isolation layer is subsequently planarized, and also serves as a stop layer when the isolation layer is subsequently planarized.
In this embodiment, the forming process of the first patterned mask layer is a chemical vapor deposition process. In other embodiments, the forming process of the first patterned mask layer may also be a physical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the protection layer 300 is silicon nitride. In other embodiments, the material of the protective layer 300 includes silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In other embodiments, the forming steps of the substrate 200, the first fin 201, and the second fin 211 further include: providing a semiconductor substrate (not shown), forming an initial protection layer on the semiconductor substrate, forming a patterned layer on the initial protection layer, and etching the initial protection layer and the semiconductor substrate by using the patterned layer as a mask to form the first fin portion 201, the second fin portion 211, and the protection layer 300 on the top of the first fin portion 201 and the second fin portion 211.
Referring to fig. 5, an isolation layer 400 is formed on the substrate 200. The isolation layer 400 fills the gap between the first fin 201 and the second fin 202. Specifically, the isolation layer 400 covers sidewalls of the first fin portion 201 and the second fin portion 202, and exposes top surfaces of the first fin portion 201 and the second fin portion 202.
The formation of the isolation layer 400 includes: forming an isolation layer 400 on the substrate 200, wherein the isolation layer 400 covers top surfaces of the first fin portion 201 and the second fin portion 211; the isolation layer 400 is planarized.
In this embodiment, the isolation layer 400 is made of silicon oxide; in other embodiments, the material of the isolation layer 400 may also be silicon oxycarbide, silicon oxycarbonitride, or silicon oxynitride.
The formation process of the isolation layer 400 is a Fluid Chemical Vapor Deposition (FCVD). The fluid chemical vapor deposition process comprises the following steps: forming a silicon-containing precursor on the substrate 200, wherein the silicon-containing precursor covers the first fin 201 and the second fin 202; subjecting the silicon-containing precursor to an oxidation process to form an initial isolation layer (not shown); the initial isolation layer is annealed to form an isolation layer 400.
In other embodiments, the isolation layer 400 can also employ a plasma enhanced chemical vapor deposition Process (PECVD) or a high aspect ratio chemical vapor deposition process (HARP).
The planarization process is a chemical mechanical polishing process (CMP); in the present embodiment, the chemical mechanical polishing process is performed until the protection layer 300 on top of the first fin 201 and the second fin 202 is exposed.
Referring to fig. 6, a mask layer 500 is formed on the first fin 201, and the mask layer 500 covers a portion of the surface of the top of the isolation layer 400.
The forming step of the mask layer 500 includes: an initial mask layer (not shown) is formed on the top surfaces of the protection layer 300 and the isolation layer 400, a patterned photoresist is formed on the upper surface of the initial mask layer, the patterned photoresist defines the position and the shape of the second fin portion 202, and the initial mask layer is etched by taking the patterned photoresist as a mask to form the mask layer 500.
In this embodiment, the forming process of the mask layer 500 is a chemical vapor deposition process; in other embodiments, the forming process of the mask layer 500 may also be a physical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the mask layer 500 is silicon nitride or silicon oxycarbide, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the mask layer 500 is made of silicon nitride, and the thickness of the mask layer 500 is 3nm to 5 nm.
Referring to fig. 7, the isolation layer 400 is etched by using the mask layer 500 as a mask through an Atomic Layer Etching (ALE) process until the substrate 200 and the sidewall surfaces of the second fin 202 are exposed.
When the isolation layer 400 is etched by adopting an atomic layer etching process, materials are removed layer by layer in an atomic scale in an ordered mode, directional etching and high selection ratio can be realized, even if the depth-to-width ratio is different, equivalent etching can be realized, and accurate control can be realized.
In this embodiment, the atomic layer etching process parameters are controlled so that when the isolation layer 400 is etched by using the mask layer 500 as a mask, the isolation layer to be etched is vertically removed.
In this embodiment, the atomic layer etching process parameters include: the etching gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
Referring to fig. 8, the mask layer 500 (refer to fig. 7) is removed.
In this embodiment, the process of removing the mask layer 500 is a wet etching method. The etching solution of the wet etching process is a diluted hydrofluoric acid solution; wherein, HF and H2The volume ratio of O is 1/1000-1/100.
Referring to fig. 9, the second fin 202 (see fig. 8) is removed, forming an opening 401.
In this embodiment, the process of removing the second fin portion 202 and forming the opening 401 is a fin portion cutting process, which includes: one or more combinations of dry etching processes or wet etching processes.
In this embodiment, the fin cutting process is a dry etching process, and the dry etching process parameters include: the adopted etching gas comprises HBr and Ar, wherein the flow rate of HBr is 10 sccm-1000 sccm, and the flow rate of Ar is 10 sccm-1000 sccm.
In other embodiments, the process parameters for the etch removal include: the etching gas is HBr and O2And Cl2Introducing He into the etching chamber, wherein the pressure of the etching chamber is 2 mTorr to 50 mTorr, the source power of the etching is 200W to 2000W, the bias power of the etching is 10W to 100W, the HBr flow is 50sccm to 500sccm, and O2Flow rate of 2sccm to 20sccm, Cl2The flow rate is 10sccm to 300sccm, and the He flow rate is 50sccm to 500 sccm.
In other embodiments, a wet etching process may be used to remove the second fin portion 202. The etching solution adopted by the wet etching process can be a tetramethylammonium hydroxide (TMAH) solution or a KOH solution.
The wet etching solution is a tetramethylammonium hydroxide solution, the tetramethylammonium hydroxide solution has a good etching selectivity ratio to silicon and silicon oxide, the silicon oxide on the sidewall is not affected under the condition of removing the second fin portion 202, and the shape integrity of the opening 401 can be ensured.
It is noted that, in other embodiments, the mask layer 500 may be removed after the second fins 202 are removed.
Referring to fig. 10, the substrate 200 is etched using the opening 401 as a mask to form a groove 402.
The opening 401 is surrounded by the first fin 201 and the remaining isolation layer 400. The purpose of etching the substrate 200 along the substrate 401 is to increase the insulation between the first fin portions 201 and improve the device performance of a semiconductor.
The process for forming the groove 402 is dry etching, and the process parameters are as follows: the etching gas comprises He, NH3 and NF3, the pressure of the etching chamber is 2to 10torr, the flow rate of NH3 is 200 to 500sccm, the flow rate of NF3 is 20 to 200sccm, the flow rate of He is 600 to 2000sccm, and the etching time is 20 to 100 seconds.
Referring to fig. 11, the substrate is etched along the groove 402 by using the opening 401 as a mask, and the groove 402 is widened.
And transversely widening the groove by adopting a back etching method, wherein the process parameters are as follows: the etching gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
The purpose of widening the groove 402 is to further isolate the first fin portions 201, improve the insulation between the first fin portions 201, and further improve the performance of the semiconductor device.
Second embodiment
The present embodiment is different from the first embodiment in the process of forming the opening 401, and the difference will be described in detail as follows.
Fig. 12 to 15 are schematic structural views illustrating a process of forming a semiconductor structure according to another embodiment of the present invention.
Referring to fig. 12, providing the substrate 200, wherein the substrate 200 has a first fin 201 and a second fin 202 separately arranged thereon; forming a protection layer 300 on the top surfaces of the first fin portion 201 and the second fin portion 202; forming an isolation layer 400 on the substrate 200, wherein the isolation layer 400 fills a gap between the first fin 201 and the second fin 202, and a top surface of the isolation layer 400 is flush with top surfaces of the first fin 201 and the second fin 202; a mask layer 500 is formed on the first fin 201, and the mask layer 500 covers a portion of the surface of the top of the isolation layer 400.
In this embodiment, the thickness of the mask layer 500 is 3nm to 5 nm.
The forming process of the above steps in this embodiment is the same as that in the first embodiment, and is not described herein again.
Referring to fig. 13, the mask layer 500 is used as a mask to etch a portion of the isolation layer 400 to expose a portion of the sidewall surface of the second fin 202.
In this embodiment, the etching process is an Atomic Layer Etching (ALE) process. The parameters of the atomic layer etching process are as follows: the etching gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
When the atomic layer etching process is used for etching the isolation layer 400, due to the high selectivity, the good directional etching performance and the equal etching property of the atomic layer etching process, the exposed second fin portions 202 have the same height, and cannot shift in the vertical downward etching process.
Referring to fig. 14, the mask layer 500 (see fig. 13) and the protection layer 300 on the top surface of the second fin 202 are removed, and the second fin 202 is further etched by a portion of the thickness.
In this embodiment, the process of removing the mask layer 500 (refer to fig. 13) and the protective layer 300 on the top surface of the second fin portion 202 with a partial thickness is an atomic layer etching process.
In other embodiments, the protection layer 300 on the top surface of the second fin 202 is removed by a wet or dry etching process, and since the material of the protection layer 300 on the top surface of the second fin 202 and the material of the mask layer 500 are silicon nitride in this embodiment, the thickness of the mask layer 500 is reduced when the protection layer 300 on the top surface of the second fin 202 is etched away. The second fin 202 is then etched using the high selective etchability of the atomic layer etch process.
It should be noted that the mask layer 500 is finally removed completely, and may be selected before the opening 401 is formed or may be selected after the opening 401 is formed.
Referring to fig. 15, the above steps are repeated, the atomic layer etching process is used to selectively etch silicon oxide to etch the isolation layer 400 with a partial thickness, and the atomic layer etching process is used to selectively etch silicon to etch the second fin portion 202 with a partial thickness; the steps are repeated, that is, the atomic layer etching process is adopted to remove the second fin portion 202 and etch the isolation layer 400 simultaneously, and the second fin portion 202 is removed, so that the opening 401 is formed.
In this embodiment, the isolation layer 400 with a partial thickness is etched, so that the etching orientation effect is better, the situation of offset generated in the case of etching with a high aspect ratio is further avoided, and the etching direction is better ensured; similarly, after the isolation layer 400 is etched to a partial thickness, the second fin portion 202 is etched to a partial thickness, and the direction of etching the second fin portion 202 can be ensured; repeating the above steps, the situation that the high aspect ratio etching is shifted is avoided every time, so that the second fin portion 202 is finally and completely removed without damaging the first fin portion 201; and the shape of the formed opening 401 is more perfect, which is beneficial for the subsequent process.
In this embodiment, the atomic layer etching process etches the isolation layer 400 according to the following process parameters: the etching gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
In this embodiment, the atomic layer etching process etches the second fin portion 202 with the following process parameters: the etching gas is HBr and O2And Cl2Introducing He into the etching chamber, wherein the pressure of the etching chamber is 2 mTorr to 50 mTorr, the source power of the etching is 200W to 2000W, the bias power of the etching is 10W to 100W, the HBr flow is 50sccm to 500sccm, and O2Flow rate of 2sccm to 20sccm, Cl2The flow rate is 10sccm to 300sccm, and the He flow rate is 50sccm to 500 sccm.
With reference to fig. 10, the substrate 200 is etched using the opening 401 as a mask to form a recess 402.
The opening 401 is surrounded by the first fin 201 and the remaining isolation layer 400. The purpose of etching the substrate 200 along the substrate 401 is to increase the insulation between the first fin portions 201 and improve the device performance of a semiconductor.
The process for forming the groove 402 is dry etching, and the process parameters areComprises the following steps: the etching gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
With reference to fig. 11, the substrate is etched along the groove 402 by using the opening 401 as a mask, so as to widen the groove 402.
And transversely widening the groove by adopting a back etching method, wherein the process parameters are as follows: the etching gas comprises He, NH3 and NF3, the pressure of the etching chamber is 2to 10torr, the flow rate of NH3 is 200 to 500sccm, the flow rate of NF3 is 20 to 200sccm, the flow rate of He is 600 to 2000sccm, and the etching time is 20 to 100 seconds.
The purpose of widening the groove 402 is to further isolate the first fin portions 201, improve the insulation between the first fin portions 201, and further improve the performance of the semiconductor device.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a first fin part and a second fin part which are separately arranged;
forming an isolation layer on the substrate, wherein the isolation layer fills a gap between the first fin portion and the second fin portion, and the top of the isolation layer is flush with the top of the first fin portion and the top of the second fin portion;
forming a mask layer on the first fin portion, wherein the mask layer covers part of the surface of the top of the isolation layer;
etching the isolation layer by using the mask layer as a mask through an atomic layer etching process until the substrate is exposed;
and removing the second fin part.
2. The method of forming of claim 1, wherein the atomic layer etch process parameters are: the etching gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
3. The method of claim 1, wherein the isolation layer is formed of a material selected from the group consisting of silicon oxide, silicon oxycarbide, silicon oxycarbonitride, and silicon oxynitride.
4. The method of forming of claim 3, wherein forming an isolation layer on the substrate comprises: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
5. The method of claim 1, wherein the mask layer is made of silicon nitride or silicon oxycarbide, silicon oxycarbonitride, or silicon oxynitride.
6. The method of forming as claimed in claim 1, further comprising, prior to forming the isolation layer: and forming a protective layer on the top surfaces of the first fin portion and the second fin portion.
7. The method of claim 6, wherein the protective layer is formed of silicon nitride.
8. The method of claim 1, wherein removing the second fin is performed simultaneously with etching the isolation layer.
9. The method of claim 8, wherein the second fin portion is removed using an atomic layer etch process.
10. The method of claim 1, wherein the removing the second fin process is performed after etching the isolation layer.
11. The method of claim 10, wherein the process of removing the second fin is a fin cut process.
12. The method of claim 1, further comprising, after removing the second fin portion: removing the mask layer, and etching the substrate by taking the first fin part and the residual isolating layer as masks to form a groove;
and continuously etching the substrate along the groove by using the first fin part and the rest of the isolation layer as masks to widen the groove.
13. The method of claim 12, wherein the recess is formed by dry etching, and the process parameters are as follows: the etching gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
14. The method of claim 12, wherein the trench is laterally widened by etching back, and the process parameters are as follows: the gas comprises He and NH3And NF3The pressure of the etching chamber is 2to 10torr, NH3The flow rate is 200sccm to 500sccm, NF3The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.
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