CN112104343B

CN112104343B - Current type level jump monitoring unit

Info

Publication number: CN112104343B
Application number: CN202010982845.0A
Authority: CN
Inventors: 单伟伟; 程博扬
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2020-09-17
Filing date: 2020-09-17
Publication date: 2022-11-01
Anticipated expiration: 2040-09-17
Also published as: CN112104343A

Abstract

The invention discloses a current type level jump monitoring unit, which is used for monitoring late data jump in the self-adaptive voltage frequency regulation and adjustment technology and is characterized by comprising the following steps: charging path unit 1, charging path unit 2, controllable switch M9, inverter U1 and high threshold buffer U2. The jump monitoring unit has obvious advantages in both response time and lowest working voltage, and can stably work in a low-to-near threshold region, so that the voltage regulation range is expanded to the near-threshold region, and the whole power consumption benefit is larger; in addition, the response time is short, and the data jump situation during the high level of the clock can be monitored in a very short time.

Description

Current type level jump monitoring unit

Technical Field

The invention relates to a current-based level jump monitoring unit applied to a self-adaptive voltage technology, which can be used for the self-adaptive voltage regulation technology and used for monitoring circuit timing errors so as to give out early warning on timing violation and avoid the generation of the timing errors. The whole circuit is realized by pure digital logic, and belongs to the field of integrated circuit design.

Background

With the continuous increase of the scale and the computing power of the integrated circuit and the application scenes of the internet of things, embedded equipment, mobile terminals, supercomputers, data centers and the like, higher and higher requirements are put forward on the energy consumption of devices. In the application of the internet of things, terminal equipment often needs longer endurance time, so that energy consumption plays a vital role in the survival capability and the functional integrity of the internet of things equipment. For a mobile terminal, a high demand is made for its standby time, but since the development of battery technology is slow in recent years, the power consumption of the device becomes an important factor affecting the user experience in the mobile internet era. For supercomputers and data centers, the upward expansion of computer performance is also severely constrained by energy consumption.

The development of an energy-efficient integrated circuit is an important means for solving the problem of energy consumption of a computing system, and reducing the working voltage of a chip can greatly reduce the power consumption of the chip, so that how to further reduce the working voltage of the chip to realize the leap-type promotion of energy efficiency becomes one of the problems to be solved urgently.

Near-threshold integrated circuit designs are considered one of the most promising techniques for improving computational performance in the future by reducing the supply voltage of the chip or circuit to a level close to the threshold voltage of the transistor.

The near-threshold technique also presents a challenge to designers while bringing a large increase in chip energy efficiency. In the application of the near threshold technology, the performance of the integrated circuit is affected by Process (Process), voltage (Voltage), and Temperature (Temperature) deviations, i.e., PVT deviations. The delay distribution of the circuit is larger, and further the deviation of the path delay is multiplied. To ensure that a chip can operate stably under various conditions, conventional designers typically need to reserve a large amount of timing margin to meet worst-case timing constraints. Meanwhile, in order to prevent the influence of circuit aging, random noise, 1/f noise, and the like, the designer also needs to leave some margin in the design process. This results in significant waste of performance and power consumption, greatly impairing the energy efficiency improvement brought by near-threshold design.

In order to reduce the excessive design margin of the circuit, better release the potential of wide Voltage design, overcome the problem of severe PVT deviation under low Voltage, and produce Adaptive Voltage Frequency Scaling (AVFS) technology. In the actual operation condition of the chip, the probability of extreme environments is extremely low, and the self-adaptive voltage design scheme can self-adaptively adjust the working voltage and frequency of the chip according to different working environments, so that the correctness of the functions of the chip can be ensured, and the design margin reserved by the chip can be reduced as much as possible, thereby achieving the purpose of saving power consumption.

The core of the self-adaptive voltage frequency regulation technology is that the time sequence condition of a circuit is monitored on line, the working voltage/frequency of a control chip is regulated in real time according to the time sequence tightness condition, the current self-adaptive voltage design is researched, and particularly the self-adaptive voltage technology under wide voltage is mainly based on a direct monitoring method. The most typical representative of direct monitoring is the Razor series of michigan university studies, however this approach typically replaces the critical path end flip-flops with timing monitoring units and latches.

Timing monitoring may be implemented by a jump monitor that monitors whether there is a late data jump. A qualified hop unit should have the following characteristics: firstly, the circuit time sequence is effectively monitored, because the most core function of the monitoring unit module is the monitoring circuit time sequence; secondly, the influence on the original design time sequence is as small as possible, because the original design needs to be modified because the monitoring unit module needs to be inserted into the original design in the error prediction-based in-situ monitoring method, the time sequence of the inserted path can be influenced; thirdly, the area overhead is as small as possible. The invention fully meets the requirements of the three points.

Disclosure of Invention

The purpose of the invention is as follows:

the invention aims to provide a stable and quick time sequence monitoring unit with small area cost, which is used for monitoring the late data jump condition and providing information whether the time sequence is violated or not for self-adaptive voltage frequency regulation.

The technical scheme is as follows:

in order to achieve the purpose, the technical scheme of the invention is a jump monitoring unit which is suitable for stable work under wide voltage, small in area cost and high in response speed and is used for monitoring whether the time sequence of a digital integrated circuit is illegal, namely whether late data jump occurs or not, and if yes, a pulse signal is generated.

A current mode level jump monitoring unit, comprising: a charging path unit 1, a charging path unit 2, a controllable switch M9, an inverter U1 and a buffer U2; the input end of the phase inverter U1 is connected with an input data signal D, the input end of the buffer U2 is connected with the output end of the phase inverter U1, and the output end of the buffer U2 outputs an inverted input data signal DN; the charging path unit 1 comprises three control input ends which are respectively connected with inverted clock signals

An input data signal D and an inverted input data signal DN; the charging path unit 2 comprises three control input ends which are respectively connected with a clock signal Pck, an input data signal D and an inverted input data signal DN; the output ends of the charging path unit 1 and the charging path unit 2 are connected to one end of a controllable switch M9 to form a node Error, the other end of the controllable switch M9 is grounded, and the control end of the controllable switch is connected with an inverted clock signal

When the clock signal Pck is at an effective level, the jump monitoring unit is enabled, the controllable switch M9 is turned off, the charging path unit 1 or the charging path unit 2 charges the node Error in response to the level jump of the input data signal D, and the node Error outputs a timing early warning signal.

The transition monitoring unit monitors whether a data signal has a transition when the clock signal is at an active level (designed as a high level in the embodiment of the present invention), and generates a timing early warning signal, and does not respond to the transition of the data signal when the clock signal is at an inactive level (designed as a low level in the embodiment of the present invention). The invention divides the jump of the data signal into two conditions, which are respectively: 1) The data signal jumps from low to high; 2) The data signal transitions from high to low. Two charging paths are adopted to respectively respond to the two types of jump and complete the charging of the output node Error.

In the embodiment of the invention, the buffer is realized by adopting a high-threshold transistor, so that the buffer has larger time delay, and the charging path has enough time to charge the node Error to the potential same as VDD under two conditions, thereby ensuring that the jump monitoring unit can stably work in a region from a low threshold value to a near threshold value.

When the jump monitoring unit is used in a detected main circuit to perform time sequence monitoring, a group of jump monitoring units are usually arranged in a plurality of key paths from the main circuit, all output Error signals can be collected by a dynamic OR gate to generate a total early warning signal, and then the voltage and frequency are adaptively adjusted by combining with a downstream control logic, so that possible time sequence errors can be effectively avoided. The jump monitoring unit can monitor the data jump condition of the clock in a high level period in a very short time, thereby gaining more voltage frequency regulation time for the whole system.

Has the advantages that:

the jump monitoring unit provided by the invention can monitor the time sequence error in the path of the digital integrated circuit, and can effectively reduce the allowance reserved for avoiding the influence of factors such as PVT deviation and the like in the design process in the application of the self-adaptive voltage frequency Adjustment (AVS) technology, thereby greatly exciting the potential of the integrated circuit and improving the energy efficiency. Compared with the international similar time sequence monitoring unit, the jump monitoring unit has obvious advantages in both response time and lowest working voltage, and can stably work in a low-to-near-threshold region, so that the voltage regulation range is expanded to the near-threshold region, and the overall power consumption benefit is larger; in addition, the response time is short, and the data jumping condition during the high level period of the clock can be monitored in a very short time.

Drawings

FIG. 1 is a schematic diagram of an application of a jump monitoring unit;

FIG. 2 is a diagram of a transistor structure of a transition monitor unit;

FIG. 3 is a timing diagram of the operation of the transition monitor unit;

FIG. 4 is a simulation diagram of a hopping monitoring unit HSPICE;

fig. 5 is a frequency gain of adaptive voltage frequency adjustment using a hop monitoring unit.

Detailed Description

The application mode of the monitoring circuit in the main circuit is shown in figure 1, belongs to a direct monitoring method, and replaces a critical path tail end trigger with a time sequence monitoring unit and a latch. The timing monitoring unit is realized by the jump monitoring unit of the invention.

The invention is further illustrated with reference to the following figures and specific examples.

The main structure of this embodiment is shown in fig. 2. The jump monitoring unit consists of 3 NMOS transistors M5, M6 and M9,6 PMOS transistors M1, M2, M3, M4, M7 and M8,1 inverter U1 and 1 buffer U2, and the total number of the transistors is 15. The transistors M1, M2, and M3 form a charging path unit 1, and the transistors M4, M5, M6, M7, and M8 form a charging path unit 2, respectively completing charging of the node Error. And the output of the Error early warning signal Error of the jump monitoring unit is directly connected with the grid input of the NMOS tube of the dynamic OR gate. The input of the buffer U2 is connected to the output of the inverter U1 for generating an inverted signal DN of the input data signal D. It should be noted that under different PVT conditions, the delay of D and DN must be kept large enough to guarantee a proper timing advance function, therefore, the buffer unit U2 of the present invention uses high threshold (HVT) transistors to increase the delay of D and DN, and other units use low threshold (LVT) transistors.

The source of the NMOS transistor M9 is grounded, the drain is the virtual ground node Error, and the gate is connected to the inverted signal of the clock. M9 plays a role of a switch, is always conducted when the clock signal Pck is at a low level, discharges the node Error to the low level, does not work at the moment, and has zero output all the time; when the clock signal is at a high level, M9 is turned off, and the jump monitoring unit performs its function, and generates a high-level pulse through the node Error, indicating that the timing violation is monitored.

The source electrode of the PMOS tube M1 is connected with a power supply VDD, the drain electrode is connected with the source electrode of the PMOS tube M2, and the grid electrode input is an inverted clock signal

The source electrode of the PMOS tube M2 is connected with the drain electrode of the PMOS tube M1, the drain electrode of the PMOS tube M2 is connected with the source electrode of the PMOS tube M3, and the grid electrode input of the PMOS tube M2 is an inverted input data signal DN. The source electrode of the PMOS tube M3 is connected with the drain electrode of the PMOS tube M2, the drain electrode of the PMOS tube M3 is connected with the node Error, and the grid electrode of the PMOS tube M3 is connected with the input data signal D. The 3 transistors M1, M2, M3 form a charging path unit 1, and monitor whether a transition from high to low occurs in the data D during the high level period of the clock.

The source electrode of the PMOS tube M4 is connected with a power supply VDD, the drain electrode is connected with a node M, and the grid electrode is connected with a clock signal. The drain electrode of the NMOS tube M5 is connected with the node M, the source electrode is connected with the drain electrode of the NMOS tube M6, and the grid electrode input is an inverted data signal DN. The drain electrode of the NMOS tube M6 is connected with the drain electrode of the NMOS tube M5, the source electrode is grounded, and the data signal D is used as the grid electrode input. Node M is the input to PMOS transistors M7, M8, M7 and M8 being connected in series. The drain electrode of the PMOS tube M8 is connected with the node Error. The 5 transistors M7 and M8, and M4, M5 and M6 together form a charging path unit 2, which monitors whether a transition of data D from low to high occurs during a high level period of the clock. The transistors M7 and M8 form a charging path, and the transistors M4, M5 and M6 form a control unit for providing a charging control signal to the charging paths M7 and M8. The node Error is used as the output end of the circuit time sequence Error early warning signal and is connected with the downstream dynamic OR gate.

The working principle of the jump monitoring unit is as follows:

when the data D changes from low to high, the data DN changes from high to low, but because of the large delay of the buffer U2 with high threshold, the data DN also has a certain delay with respect to the change of the data D, and both the data D and the data DN maintain high level during this time. The transistors M5 and M6 are kept on, and at this time, the charge of the node M is discharged through the transistors M5 and M6, and the level of the node M is discharged to a low level. And the node M is used as the input of the PMOS transistors M7 and M8, so that M7 and M8 are turned on, thereby charging the node Error and generating a high-level early warning signal.

When the data D changes from high to low, the data DN changes from low to high, but also due to the delay of the inverter U1 and the buffer U2, the data DN has a certain delay with respect to the change of the data D. During the period, the data D and DN are both kept at low level, the transistors M2 and M3 are kept on, the node Error is charged to the same potential as VDD, and an early warning signal is sent out.

The timing diagram of the transition monitoring unit is shown in fig. 3, and is mainly divided into the following 4 cases:

case1, case2: when the clock signal is at a low level, no matter the data D changes from low to high or from high to low, the transistor M9 remains on at this time, the node Error remains at "0", and the early warning signal remains at a low level at this time.

Case3: when the data D changes from low to high during the period that the clock signal is at high level, an early warning signal is sent out at the moment. When the clock is at high level, the transistor M9 is turned off, the transistor M4 is turned off, when the data D changes from low to high, the data DN changes from high to low, but due to the delay of the units U1 and U2, the data DN has a certain delay relative to the change of the data D, during this time, the data D and DN both keep at high level, the transistors M5 and M6 keep on, at this time, the electric charge of the node M is discharged through the transistors M5 and M6, the level of the node M is discharged to low level, and at this time, the transistors M7 and M8 keep on. The node Error will be charged to the same potential as VDD for the time when both data D and DN remain high, i.e., the early warning signal Error goes high. Under different PVT conditions, the delay of D and DN must be kept large enough to guarantee normal timing warning function, therefore, in the present invention, unit U2 employs a high threshold (HVT) unit to increase the delay of D and DN, and the other units employ a low threshold (LVT).

Case4: when the data D changes from high to low during the period that the clock signal is at high level, an early warning signal is sent out at the moment. When the clock is high level, the transistor M9 is turned off, the MOS transistor M1 is turned on, when the data D changes from high to low, the data DN changes from low to high, but due to the time delay of the units U1 and U2, the data DN has a certain delay with respect to the change of the data D, the data D and DN both keep low level at this time, the transistors M2 and M3 keep on, the node Error is charged to the same potential as VDD, that is, the early warning signal Error changes to high level.

Other cases: during the high level or the low level of the clock, the data D does not turn over, and no time sequence early warning exists at the moment. When the data D is not flipped, there is no charging path to the node Error, and the node Error is kept at a low level.

Under normal operation, when no error occurs, data arrives before the rising edge of the clock, and the error warning signal remains low. When a timing error is generated due to delayed arrival of a signal, a positive pulse is generated as an error warning signal. To reduce the propagation delay of the false early warning signals, dynamic or gates are used to aggregate all early warning signals from different paths. One dynamic or gate may collect error warning signals from up to 10 transition monitoring units. The output signal of the dynamic OR gate is OR-operated by the traditional OR gate to generate a global error early warning signal which is used for controlling the clock gating circuit and is reset to 0 by the reset signal.

When a timing error signal is detected, data can still be transmitted correctly through Time-clocking of the latch, so as to avoid real timing error.

Fig. 4 shows the simulation results of the present invention. In order to verify the functional correctness of the jump monitoring unit in the invention, the design is carried out under a 28nm CMOS process, monte Carlo simulation is carried out on the jump monitoring unit, the simulation working conditions are 0.46V and 25 ℃, monte Carlo simulation (5000 times), the clock working frequency is 50MHz, and the specific simulation result is shown in FIG. 4, wherein a signal Pck is a clock signal, D is a data input signal, and Error is an early warning signal. As can be seen from the figure, when data D makes a transition during a high level of the clock signal, the early warning signal Error changes to a high level; in other cases, the level of the node Error is always kept low.

As shown in fig. 5, the effect of the application of the jump monitoring unit to the adaptive voltage frequency adjustment design. The adopted verification platform is an 8-bit AES (Advanced Encryption Standard, AES) circuit. The number of the chips tested at this time is 24, and 8 chips are respectively selected from FF, TT and SS wafers for testing. The reference frequency refers to the highest working frequency after the reserved time sequence allowance of the chip is considered, and the worst process corner is replaced by the chip with the worst performance in consideration of the actual test condition when the test temperature range is 0-85 ℃. And according to the screening standard, carrying out actual test on the batch of chips to find out the reference frequency. According to the reference frequency searching method, the reference frequency under different voltages is tested, a chip with a process corner of Typical is selected at the same time, the highest frequency under 0.55V-1.1V is measured, and the tested highest working frequency and the reference frequency distribution diagram are shown in the figure. Under the voltage of 0.55V, the highest working frequency of the chip is 3 times of the reference frequency of the chip, so that the performance is improved by 3 times under the adaptive voltage design designed by the self-adaptive voltage control circuit under the voltage of 0.55V. It should be noted that the worst operating temperature of the chip is 85 ℃ at 0.8V-1.1V and 0 ℃ at 0.5V-0.7V due to the temperature inversion effect.

If the system is modified to adjust the voltage to eliminate the margin, the adaptive voltage design of the jump monitoring unit can obtain a power consumption benefit compared with the traditional margin design.

Table 1 shows the comparison between the parameters of the jump monitoring unit of the present invention and the international similar timing monitoring unit, wherein the number of transistors of the standard Latch (Latch) used as the reference for comparison in the table is 19 (with the reset terminal), and the number of transistors, area cost, power consumption cost and response time added in the table are all compared with the standard Latch. Compared with the design of a foreign excellent time sequence monitoring unit, the jump monitoring unit has obvious advantages in both response time and minimum working voltage, and the minimum working voltage is 0.46V.

TABLE 1 parameter comparison of jump monitoring unit and international similar time sequence monitoring unit

As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited to the invention itself. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

[ reference documents ]

[1]Seongjong Kim and Mingoo Seok.Variation-Tolerant，Ultra-Low-Voltage Microprocessor with a Low-Overhead，Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique[J].IEEE J.Solid-State Circuits，2015，50(6)：1478-1490

[2]S.Das et al.A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation[J].IEEE Transactions on Circuits and Systems I：Regular Papers，2014，61(8)：2290-2298

[3]Zhang Y，Khayatzadeh M，Yang K，et al.iRazor：3-transistor current-based error detection and correction in an arm cortex-r4 processor[C].IEEE Solid-State Circuits Conference(ISSCC)，2016：160-162

Claims

1. A current mode level jump monitoring unit, comprising: a charging path unit 1, a charging path unit 2, a controllable switch M9, an inverter U1 and a buffer U2; the input end of the phase inverter U1 is connected with an input data signal D, and the output end of the buffer U2The input end is connected with the output end of the phase inverter U1, and the output end of the buffer U2 outputs an inverted input data signal DN; the charging path unit 1 comprises three control input ends which are respectively connected with inverted clock signals

An input data signal D, an inverted input data signal DN; the charging path unit 2 comprises three control input ends which are respectively connected with a clock signal Pck, an input data signal D and an inverted input data signal DN; the output ends of the charging path unit 1 and the charging path unit 2 are connected to one end of a controllable switch M9 to form a node Error, the other end of the controllable switch M9 is grounded, and the control end of the controllable switch is connected with an inverted clock signal

2. A current mode level-jump monitoring unit as claimed in claim 1, wherein: the buffer U2 is implemented using high threshold transistors.

3. A current mode level transition monitoring unit as claimed in claim 1 or 2, wherein: the charging path unit 1 comprises three MOS transistors connected in series between a power supply VDD and a node Error, and gates of the three MOS transistors are used as three control input ends of the charging path unit 1.

4. A current mode level-jump monitoring unit as claimed in claim 3, wherein: the charging path unit 1 comprises PMOS transistors M1, M2 and M3, the PMOS transistors M1, M2 and M3 are sequentially connected in series, the source electrode of the PMOS transistor M1 is connected with a power supply VDD, the drain electrode of the PMOS transistor M3 is connected with a node Error, and the PMOS transistors M1, M2 and M3The grids are respectively connected with the inverted clock signals

Inverted input data signal DN, input data signal D.

5. A current mode level jump monitoring unit according to claim 1 or 2, wherein: the charging path unit 2 includes two MOS transistors connected in series between a power supply VDD and a node Error, and a control circuit that supplies a charging control signal to the two MOS transistors, the control circuit includes three MOS transistors connected in series between the power supply VDD and ground, and gates of the three MOS transistors serve as three control input terminals of the charging path unit 2.

6. A current mode level jump monitoring unit according to claim 5, wherein: the charging path unit 2 comprises PMOS transistors M4, M7 and M8 and NMOS transistors M5 and M6, the PMOS transistor M4 and the NMOS transistors M5 and M6 are sequentially connected in series, the PMOS transistors M7 and M8 are sequentially connected in series, the sources of the PMOS transistor M4 and the PMOS transistor M7 are respectively connected with a power supply VDD, the source of the NMOS transistor M6 is grounded, the drain of the PMOS transistor M8 is connected with a node Error, and the gates of the PMOS transistor M4 and the NMOS transistors M5 and M6 are respectively connected with a clock signal Pck, an inverted input data signal DN and an input data signal D; the gates of the PMOS transistors M7, M8 are connected to form a node M, and the drains of the PMOS transistor M4 and the NMOS transistor M5 are connected to the node M.

7. A current mode level-jump monitoring unit as claimed in claim 1 or 2, characterized in that: the controllable switch M9 is implemented by a MOS transistor.