CN107565953B - Control circuit of jump detector and clock frequency adjusting system - Google Patents

Abstract

The invention discloses a jump detector, which comprises a first PMOS tube, a first NMOS tube, a CMOS transmission gate, an inverter and an exclusive OR gate, and can be used for on-line time sequence monitoring to monitor whether input data arrives late or not, namely whether the input data arrives after a clock jump edge or not. Compared with the traditional jump detector, the invention has simple structure, only 16 transistors and greatly reduces the area of the jump detector. The jump detector with near threshold wide voltage works in cooperation with the trigger, the input end of the jump detector is connected with the input end of the trigger, the data jump condition can be effectively monitored in the detection window, and a time sequence early warning signal is output. In addition, a timing sequence early warning control system is disclosed, which comprises a dynamic OR gate, a frequency control state machine and a phase-locked loop.

Description

Control circuit of jump detector and clock frequency adjusting system

Technical Field

The invention relates to the technical field of integrated circuit design low power consumption, in particular to the technical field of self-adaptive voltage frequency adjustment based on-line time sequence monitoring.

Background

With the development of the integrated circuit (Integrated Circuit, IC) industry, electronic products have played an increasingly important role in life of people, especially in the field of mobile terminals, and as performance requirements of people on electronic products are continuously increased, the power consumption problem caused by the performance requirements is increasingly significant, so that performance is also a big target of integrated circuit design. The efficiency refers to the energy consumed by each operation, and if the efficiency is lower, the efficiency of energy utilization is higher, and research shows that when the voltage is reduced, the efficiency is reduced, and the optimal efficiency point is in a near-threshold area. Therefore, in order to address both performance and performance requirements, a wide voltage range (Wide voltage range) circuit is of great interest, meaning that the operating range of the circuit ranges from near-threshold to conventional voltage ranges. For a working scene with higher performance requirements, the circuit works in a conventional voltage area; when the circuit has a high performance requirement, the circuit may reduce the voltage to a near threshold region.

On the other hand, as the Process size is reduced, the influence of Process-Voltage-Temperature (PVT) deviation on the circuit design is also increasing. Considering the influence of PVT bias on the chip, an IC designer typically guarantees that the chip can operate normally even in a worst-case PVT environment by reserving a timing margin. The "worst case" comprehensively considers the adverse factors of all PVT deviations on the circuit timing, however, in the actual operation of the chip, the worst case is rarely or even not happened, which results in that the selected frequency is too conservative, so that the waste of the chip performance and the efficiency is caused, and therefore, how to reduce the reserved timing margin in the design becomes one of the main ideas for improving the performance and the efficiency.

In order to solve the problem of timing margin, adaptive frequency regulation (Adaptive Frequency Scaling, AFS) and adaptive voltage regulation (Adaptive Voltage Scaling, AVS) are mainly used internationally. The AFS can obtain effective frequency benefits by monitoring the time sequence of the chip and adaptively adjusting the working frequency, and the AVS can obtain effective power consumption benefits by monitoring the time sequence of the chip and adaptively adjusting the working voltage. The system applied to the invention adopts a self-adaptive frequency adjustment method, solves the problem of time sequence allowance, and obtains frequency benefit. While there are two main approaches to adaptive frequency adjustment, one is based on indirect monitoring and the other is based on direct monitoring. The self-adaptive frequency adjustment of the direct monitoring is widely applied because the time sequence condition of the circuit can be truly reflected. The jump detector is a core component of the direct monitoring adaptive frequency adjustment method.

A well-designed transition detector, in addition to meeting basic timing monitoring functions, is required to meet several requirements: 1. the number of transistors is as small as possible, and the area and power consumption of the detection unit can be reduced as much as possible. 2. A wide voltage range operation can be achieved. 3. The end load to the original critical path is as small as possible, as excessive load can cause the critical path to become more critical, affecting system performance.

Disclosure of Invention

Aiming at the design requirement of the jump detector with near threshold wide voltage, the invention designs the jump detector with 16 transistors, which has small area and low power consumption, and the working voltage range can reach 0.5V-1.1V under the 40nm CMOS technology. When the jump detector is matched with a trigger to serve as a time sequence monitoring unit at the tail end of the path, the structure of the original trigger is not changed, and the time sequence condition of the circuit can be effectively monitored. In addition, the invention provides a control circuit of the clock frequency adjusting system, so that on-line time sequence monitoring and system frequency self-adaptive adjustment are realized.

In order to achieve the above purpose, the technical scheme provided by the invention is as follows:

a control circuit of a clock frequency adjusting system comprises N jump detectors, N input dynamic OR gates, a frequency control state machine and a phase-locked loop; the data signal input ends of the N jump detectors are connected to the tail ends of N key paths of the SOC chip, the clock signal input ends of the N jump detectors are connected to the system clock of the SOC chip, the early warning signal output ends of the N jump detectors are connected with the input ends of N input dynamic OR gates, the output ends of the N input dynamic OR gates are connected with the input ends of a frequency control state machine, the output ends of the frequency control state machine are connected with the input ends of a phase-locked loop to transmit an up-conversion signal or a down-conversion signal to the phase-locked loop, one output end of the phase-locked loop is used for adjusting the frequency of the clock signal, and the other output end of the phase-locked loop is connected with the frequency control state machine to transmit the clock signal with the adjusted frequency to the frequency control state machine;

the jump detector comprises a first PMOS tube, a first NMOS tube, a CMOS transmission gate, an inverter and an exclusive-OR gate, wherein the grid electrodes of the first PMOS tube and the first NMOS tube are connected and serve as the data signal input end of the jump detector, the source electrode of the PMOS tube is used for being connected with a power supply, and the drain electrode of the PMOS tube is connected with the first input end of the exclusive-OR gate and the first port of the CMOS transmission gate; the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is connected with the second input end of the exclusive-OR gate and the second port of the CMOS transmission gate; the output end of the exclusive-OR gate is used as an early warning signal output end of the jump detector; the CMOS transmission gate consists of a second PMOS tube and a second NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube and is used as a first input end of the CMOS transmission gate, the source electrode of the second PMOS tube is connected with the source electrode of the second NMOS tube and is used as a second input end of the CMOS transmission gate, the grid electrode of the second PMOS tube is connected with the output end of the inverter, the output end of the inverter is connected with the grid electrode of the second NMOS tube, and the input end of the inverter is connected with the system clock;

the N input dynamic OR gate consists of 1 PMOS tube MP1, N+2 NMOS tubes and 1 inverter INV, wherein the N+2 NMOS tubes are NMOS tubes MN1 to MNN, an NMOS tube M0 and an NMOS tube M1 respectively, the source electrode of the PMOS tube MP1 is connected with a power supply, and the drain electrode of the PMOS tube MP1 is connected with the drain electrodes of the NMOS tubes MN1 to MNN, the drain electrode of the NMOS tube M1 and the input end of the inverter INV; the gates of the NMOS transistors MN1 to MNN are respectively connected with the early warning signal output ends of the N jump detectors, the sources of the NMOS transistors MN1 to MNN are connected with the drain electrode of the NMOS transistor M0, the source electrode of the NMOS transistor M0 is connected with the ground end, and the gate of the NMOS transistor M0 is used for inputting reset signals; the source electrode of the NMOS tube M1 is grounded, and the grid electrode of the NMOS tube M1 is connected with the output end of the inverter INV.

Compared with the prior art, the invention has the beneficial effects that: (1) The jump detector of the invention does not change the structure of the original trigger, thus having little influence on the original circuit. (2) The jump detector of the invention has only 16 transistors, thus the area cost and the power consumption cost are greatly reduced when the on-line time sequence monitoring is realized, the self-adaptive voltage regulating system based on the on-line time sequence monitoring can obtain considerable frequency benefit (3) the jump detector of the invention can stably work under low voltage, thus the on-line time sequence monitoring can be implemented within a wide voltage range near threshold value, the application range of the circuit applying the invention is wider, and the frequency benefit can be obtained from a near threshold value region to a conventional voltage region.

Drawings

Fig. 1 is a circuit configuration diagram of a timing jump detector.

Fig. 2 is a circuit diagram of a 10-pipe exclusive or gate.

Fig. 3 is a timing diagram of timing jump detector monitoring.

Fig. 4 is a structural diagram of a control system.

Fig. 5 is a diagram of an N-input dynamic or gate structure.

Fig. 6 is a simulation diagram of adaptive frequency adjustment at a conventional voltage.

Fig. 7 is a simulation of adaptive frequency adjustment at low voltage.

Detailed Description

The following describes the technical scheme of the present invention in detail with reference to the accompanying drawings, but the scope of the present invention is not limited to the embodiments.

The invention mainly monitors the time sequence of the critical path in the integrated circuit, and the jump detector is inserted into the tail end trigger of the critical path to form a time sequence monitoring unit for monitoring whether the time sequence of the critical path is tense or not. The time sequence monitoring scheme of the invention needs a clock duty ratio regulating circuit to shorten the low level time of the clock. Therefore, if the input data Din jumps during the low level of the clock (before the next rising edge), which means that the circuit timing is already tight at this time, even an error may be caused by the arrival of the next clock cycle, if the input data Din jumps at the high level of the clock, the timing is loose, and the data is normal. The traditional jump detector has the defects of complex structure, large area overhead, limited working voltage range and the like.

Therefore, the invention provides a jump detector, referring to fig. 1, comprising a first PMOS tube M1, a first NMOS tube M2, a CMOS transmission gate, an inverter and an exclusive-or gate, wherein the gates of the first PMOS tube M1 and the first NMOS tube M2 are connected and serve as the data signal input end of the jump detector, the source electrode of the first PMOS tube M1 is used for being connected with a power supply, and the drain electrode of the first PMOS tube M1 is connected with the first input end of the exclusive-or gate and the first port of the CMOS transmission gate; the source electrode of the first NMOS tube M2 is grounded, and the drain electrode of the first NMOS tube M2 is connected with the second input end of the exclusive-OR gate and the second port of the CMOS transmission gate; the output end of the exclusive-OR gate is used as an early warning signal output end of the jump detector; the CMOS transmission gate is composed of a second PMOS tube M4 and a second NMOS tube M3, the drain electrode of the second PMOS tube M4 is connected with the drain electrode of the second NMOS tube M3 and is used as a first input end of the CMOS transmission gate, the source electrode of the second PMOS tube M4 is connected with the source electrode of the NMOS tube M3 and is used as a second input end of the CMOS transmission gate, the grid electrode of the second PMOS tube M4 is connected with the output end of the inverter, the output end of the inverter is connected with the grid electrode of the second NMOS tube, and the input end of the inverter is connected with the system clock.

The data signal input and the clock signal input of the transition detector are the data input Din, the clock signal CLK and the inverted clock of the critical path end flip-flopThe output terminal is the early warning signal pre_error. The transition detector monitors the timing when the clock is low. The jump detector inserts a CMOS transmission gate between standard inverters, when the CMOS transmission gate is turned off, the jump detector can judge whether the input data jumps in the clock low level by judging the voltage difference of the A point and the B point at two ends of the transmission gate.

As shown in fig. 2, a circuit diagram of the 10-pipe exclusive or gate in fig. 1 is formed by 10 MOS transistors, and exclusive or logic is completed.

As shown in fig. 3, in the timing diagram monitored by the jump detector of the present invention, the 1 st period has shorter delay of the critical path, so the arrival time of the data is earlier, i.e. Din jumps in the high level region of the clock. At this time, the transmission gate between the node a and the node B is in an on state. Because of the CMOS transmission gate structure, there is no threshold loss in the voltage between a and B, i.e., the voltage values of the a and B nodes are the same, and after passing through the exclusive or gate, the output early warning signal pre_error is always in a low level state. After the clock transitions low, the transfer gate turns off and the data does not transition, so the node a and node B charges remain unchanged and the pre_error output remains low. In the 2 nd period, the data delay is longer, and in the low level region of the clock, the data Din jumps from high to low. In the clock high region, also because the CMOS transmission gate is on, node a and node B are on and the pre_error signal is not pulled high. In the clock low level region, the data Din jumps from high level to low level, the first PMOS tube M1 is conducted, the A node is charged to high level by the power supply through the first PMOS tube M1, and the level value of the A node is different from that of the B node, so that the output Pre_Error of the exclusive OR gate generates a high level pulse and generates an early warning signal. The 3 rd cycle, similar to the 2 nd cycle, is used to verify whether the early warning signal pre_error can be correctly generated when the data Din transitions from the low level to the high level. In the clock high region, the data Din is low, and then both node a and node B are high. In the low clock region, when the data Din jumps from low to high, the charge of the node B is discharged to ground through the first NMOS transistor M2, so that the values of a and B are different, the exclusive or gate output pre_error generates a high pulse signal, and after CLK reenters the high clock region, pre_error is pulled back to low.

Referring to fig. 4, a control circuit of a clock frequency adjustment system includes N transition detectors, N input dynamic or gates, a frequency control state machine, and a phase locked loop; the data signal input ends of the N jump detectors are used for being connected to N key path tail ends of the SOC chip, the clock signal input ends of the N jump detectors are connected to a system clock of the SOC chip, the early warning signal output ends of the N jump detectors are connected with the input ends of the N input dynamic OR gates, the output ends of the N input dynamic OR gates are connected with the input ends of the frequency control state machine, the output ends of the frequency control state machine are connected with the input ends of the phase-locked loop to transmit an up-conversion signal or a down-conversion signal to the phase-locked loop, one output end of the phase-locked loop is used for adjusting the frequency of the clock signal, and the other output end of the phase-locked loop is connected with the frequency control state machine to transmit the clock signal with the adjusted frequency to the frequency control state machine.

N critical paths are selected on the SOC chip, N time sequence line jump detectors are inserted into the tail ends of the N screened critical paths, the N time sequence jump detectors monitor the time sequence of the N critical paths in real time, the output time sequence early warning signals Pre_error [1] to Pre_error [ N ] are transmitted to N input dynamic OR gates, if the time sequence tension is monitored, early warning signals are immediately generated in a monitoring window, and one or more signals in the Pre_error [1] to Pre_error [ N ] are pulled up. N inputs the multiple time sequence early warning signals Pre_error [1] to Pre_error [ N ] generated by the dynamic OR gate real-time acquisition time sequence jump detector, and carries out the multi-bit OR operation to generate the total time sequence early warning signal Pre_error_all, and the total time sequence early warning signal Pre_error_all is transmitted to the frequency control state machine. The frequency control state machine outputs frequency control signals freq_up_id and freq_down_id to a phase-locked loop (PLL) according to the input signal timing early warning signal pre_error_all and the PLL locking signal pll_lock_id and the current state of the state machine. When the timing is tight, freq_up_id is low and freq_down_id is high, and the system frequency decreases. When the timing margin is high, freq_up_id and low, the system frequency rises. A phase-locked loop (PLL) adjusts the frequency of an output clock Clk according to frequency control signals Freq_up_id and Freq_down_id, and when time sequence tension is realized, the system frequency is reduced; with a wide timing margin, the system frequency increases, thereby adaptively adjusting the clock frequency.

The frequency control state machine adjusts state machine states and outputs according to the state machine current state and the input total timing early warning signal pre_error_all and the PLL lock signal pll_lock_id. After the frequency control state machine enters a normal working state, the system judges whether the timing sequence of the critical path is tense or loose by judging whether the early warning signal exists or not. If the timing is relaxed, the PLL is configured to raise the operating frequency. If the timing is tight, the frequency is reduced by configuring the PLL. The state machine is divided into three states, normal (00), frequency_up (01) and frequency_down (10). After the whole frequency control state machine system is started, the system firstly enters a Normal working state Normal (00), and at the moment, the working frequency of a phase-locked loop (PLL) is maintained. After the Normal working state is kept for 1000 clock cycles and no time sequence early warning signal Pre_error_all is generated, the clock enters an up-conversion state frequency_up (01), the PLL Frequency is regulated to increase, and after the PLL Frequency is stable, the clock enters a Normal working state Normal (00). When receiving a time sequence early warning signal Pre_error_all in a Normal working state Normal (00), the device enters a Frequency-reducing state frequency_Down (10), adjusts the Frequency reduction of a PLL model, and enters the Normal working state Normal (00) after the PLL Frequency is stable.

Normal (00) state

The Normal state refers to a state of Normal operation after the current system is started, and the system working frequency is the current PLL output frequency. The output control signals freq_up_id and freq_down_id are simultaneously low.

(1) If the trigger detects that the total timing early warning signal Pre_error_all is pulled high at this time, the critical path timing is tensed, and the system enters a Frequency-down state (10).

(2) If the Pre-alarm signal Pre-alarm-all is not detected, the No-alarm-count signal is used for recording the number of periods where No early alarm occurs, and if the early alarm signal is not detected for 1000 periods continuously, the timing margin of the circuit is more, the circuit enters a Frequency up (01) state, and the circuit Frequency is increased.

Frequency_up (01) state

The frequency_up state indicates that the system has no time sequence early warning signal for 1000 continuous periods, the time sequence is very loose, the PLL can be configured to improve the working Frequency, and the time sequence allowance is reduced. The output control signal freq_up_id is high and freq_down_id is low.

(1) The pll_lock signal is an output signal of the PLL and if the pll_lock signal is still low, it indicates that the PLL output Frequency is unstable and the Frequency up (01) state should be kept unchanged.

(2) If PLL_lock is high, indicating that the PLL configuration is over, a stable frequency has been output, at which point the state machine will switch back to Normal (00) state, indicating that the frequency modulation is over.

FrequencyDown (10) state

The frequency_down state indicates that the system timing is now tight and the PLL is performing the down configuration phase. The output control signal freq_up_id is low and freq_down_id is high.

(1) If PLL_lock is still low, meaning that the PLL is still in configuration, then the FrequencyDown (10) state is maintained.

(2) If PLL_lock is pulled high, indicating that the PLL configuration is over, a stable frequency has been output, at which point the state machine will switch back to Normal (00) state, indicating that the frequency modulation is over.

A Phase Locked Loop (PLL) adjusts the output frequency based on the input signals freq_up_id and freq_down_id. The output clock Clk of the Phase Locked Loop (PLL) is the division result of the input clock clk_id. The main input signals are a reference clock signal clk_id, an up-conversion signal freq_up_id and a down-conversion signal freq_down_id. The main output signals are Clk, freq_show_id and pll_lock_id.

The input clock signal is a system clock signal, the input reset signal is a system reset signal, the input signal PLL locking signal is PLL_lock_id, the data input signal is a total time sequence early warning signal (Pre_error_all), and the data output is an up-conversion signal Freq_up_id and a down-conversion signal Freq_down_id.

The input port of the phase-locked loop (PLL) includes: reference clock clk_id, frequency control signals freq_up_id and freq_down_id, and PLL initial frequency count_id. The output signal includes: the clocks Clk, pll_lock_id and freq_show_id are output. The pll_lock_id signal indicates whether the clock of the PLL is stably output. The freq_show_id signal can convert the clock frequency value into a voltage form, so that the rise and fall condition of the current frequency can be judged more conveniently.

Referring to fig. 5, the N input dynamic or gate is composed of 1 PMOS tube MP1, n+2 NMOS tubes and 1 inverter INV, the n+2 NMOS tubes are respectively an NMOS tube MN1 to an NMOS tube MNN, an NMOS tube M0 and an NMOS tube M1, the source of the PMOS tube MP1 is connected to a power supply, and the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN1 to the NMOS tube MNN, the drain of the NMOS tube M1 and the input end of the inverter INV; the gates of the NMOS transistors MN1 to MNN are respectively connected with the early warning signal output ends of the N jump detectors, the sources of the NMOS transistors MN1 to MNN are connected with the drain electrode of the NMOS transistor M0, the source electrode of the NMOS transistor M0 is connected with the ground end, and the gate of the NMOS transistor M0 is used for inputting reset signals; the source electrode of the NMOS tube M1 is grounded, and the grid electrode of the NMOS tube M1 is connected with the output end of the inverter INV.

In fig. 5, when the control signal i_reset is at a low level, the PMOS transistor MP1 is turned on, the drain dynamic node V0 thereof is charged to a high level, the low level is output after being inverted by the inverter INV, the output of the N-input dynamic or gate is at a low level, and simultaneously the NMOS transistors M0 and M1 are also turned off, the timing early warning signal does not affect the output of the dynamic or gate, which is equivalent to the N-input dynamic or gate being turned off at the moment; when the control switch signal i_reset is at a high level, the PMOS transistor MP1 is turned off, the NMOS transistor M0 is turned on, at this time, any one of the timing early-warning signals pre_error [1] to pre_error [ N ] is at a high level, and the corresponding NMOS transistor will be turned on, so that the charge on the dynamic node V0 is released to 0, and after being inverted by the inverter INV, the NMOS transistor M1 outputs a high level, the discharge of the dynamic node V0 is accelerated, and the output of the N input dynamic or gate remains at a high level until the control switch signal i_reset is set to "0", which is equivalent to the N input dynamic or "being turned on, and the logic function of" or "is realized.

As shown in fig. 6, the frequency adjustment process of the adaptive frequency adjustment system based on-line time sequence monitoring of the present invention is shown. The design is based on an SMIC 40nm process library, the process angle is TT, and 1.1V and 0 ℃ are taken as simulation environments. In order to simulate the working environment of a real chip, the design superimposes 5% of voltage fluctuation on the power supply voltage, and mainly verifies the frequency adjustment process.

Fig. 6 is an overall process of adaptive frequency adjustment at a conventional voltage by the control system. clk is a system clock, and because the clock frequency is higher, direct observation of frequency rise and fall is not facilitated, so that freq_show_id signals are used for observing frequency change, the voltage value corresponding to freq_show_id on a waveform diagram is the output frequency of the current PLL, freq_up_id is an up-conversion control signal and freq_down_id is a down-conversion control signal, PLL_lock_id is a locking signal of the PLL, and when the PLL_lock_id signal is pulled high, the output frequency of the PLL is locked, and the control system can continue to work. Pre_error_all is the total timing early warning signal. The initial frequency of the output frequency of Clk is 960MHz. Then the system starts to detect the time sequence early warning signal, the system cannot detect the time sequence early warning due to the fact that the initial time sequence allowance is quite wide, the freq_up_id signal is pulled up once every 1000 clock cycles, the system frequency is gradually increased, and the time sequence allowance is compressed. Along with the continuous reduction of the time sequence allowance, when the clock frequency is 969MHz, time sequence early warning is started to be generated, the system frequency is not increased any more, and finally the system tends to be in a stable state. The entire control system enables adaptive frequency adjustment at conventional voltages.

Fig. 7 shows a frequency adaptive regulation diagram of a low voltage down-jump detector with 0.66V, process angle SS, and temperature-25 degrees celsius, and its control circuit. Similar to fig. 6, the adaptive frequency adjustment process of the control system still performs well at 0.66V. The Clk has the initial frequency of 100MHz, the time sequence is relatively abundant, the system is continuously increased in frequency, the time sequence allowance is compressed, and when the final frequency is 124MHz, the time sequence early warning is generated, and the system clock is stable.

The above results show that the invention can obviously reduce the working frequency of the lifting circuit and realize frequency benefit.

Claims (1)

1. A control circuit of a clock frequency adjusting system comprises N jump detectors, N input dynamic OR gates, a frequency control state machine and a phase-locked loop; the data signal input ends of the N jump detectors are used for being connected to the tail ends of N key paths of the SOC chip, the clock signal input ends of the N jump detectors are used for being connected to a system clock of the SOC chip, the early warning signal output ends of the N jump detectors are connected with the input ends of N input dynamic OR gates, the output ends of the N input dynamic OR gates are connected with the input ends of a frequency control state machine, the output ends of the frequency control state machine are connected with the input ends of a phase-locked loop to transmit an up-conversion signal or a down-conversion signal to the phase-locked loop, one output end of the phase-locked loop is used for adjusting the frequency of the clock signal, and the other output end of the phase-locked loop is connected with the frequency control state machine to transmit a frequency locking signal with stable frequency to the frequency control state machine;

the jump detector comprises a first PMOS tube, a first NMOS tube, a CMOS transmission gate, an inverter and an exclusive-OR gate, wherein the grid electrodes of the first PMOS tube and the first NMOS tube are connected and serve as the data signal input end of the jump detector, the source electrode of the first PMOS tube is used for being connected with a power supply, and the drain electrode of the first PMOS tube is connected with the first input end of the exclusive-OR gate and the first port of the CMOS transmission gate; the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the second input end of the exclusive-OR gate and the second port of the CMOS transmission gate; the output end of the exclusive-OR gate is used as an early warning signal output end of the jump detector; the CMOS transmission gate consists of a second PMOS tube and a second NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube and is used as a first input end of the CMOS transmission gate, the source electrode of the second PMOS tube is connected with the source electrode of the NMOS tube and is used as a second input end of the CMOS transmission gate, the grid electrode of the second PMOS tube is connected with the output end of the inverter, the output end of the inverter is connected with the grid electrode of the second NMOS tube, and the input end of the inverter is used for being connected with a system clock;

the N input dynamic OR gate consists of 1 PMOS tube MP1, N+2 NMOS tubes and 1 inverter INV, wherein the N+2 NMOS tubes are NMOS tubes MN1 to MNN, an NMOS tube M0 and an NMOS tube M1 respectively, the source electrode of the PMOS tube MP1 is connected with a power supply, and the drain electrode of the PMOS tube MP1 is connected with the drain electrodes of the NMOS tubes MN1 to MNN, the drain electrode of the NMOS tube M1 and the input end of the inverter INV; the gates of the NMOS transistors MN1 to MNN are respectively connected with the early warning signal output ends of the N jump detectors, the sources of the NMOS transistors MN1 to MNN are connected with the drain electrode of the NMOS transistor M0, the source electrode of the NMOS transistor M0 is connected with the ground end, and the gate of the NMOS transistor M0 is used for inputting reset signals; the source electrode of the NMOS tube M1 is grounded, and the grid electrode of the NMOS tube M1 is connected with the output end of the inverter INV.