CN112101502B

CN112101502B - RFID (radio frequency identification) tag chip and EPC (evolved packet core) area and user area size distribution method thereof

Info

Publication number: CN112101502B
Application number: CN202010888115.4A
Authority: CN
Inventors: 王学先
Original assignee: Zhihui Xinlian Xiamen Microelectronics Co ltd
Current assignee: Zhihui Xinlian Xiamen Microelectronics Co ltd
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2022-06-21
Anticipated expiration: 2040-08-28
Also published as: CN112101502A

Abstract

An RFID tag chip and an EPC area and a user area size allocation method thereof, the chip includes a memory, the memory includes a user area and an EPC area, the EPC area includes a PC word, the PC word includes a field L and a UMI bit, a value of the field L indicates a size of the EPC area, the value of the field L can be modified by a standard command, and the UMI bit is used for marking whether the user area exists. The invention can quickly achieve the purpose of configuring the size of the EPC area and the user area by using the standard write command.

Description

RFID (radio frequency identification) tag chip and EPC (electronic product code) area and user area size distribution method thereof

Technical Field

The invention relates to the technical field of RFID (radio frequency identification devices), in particular to an RFID tag chip and an EPC (electronic product code) area and user area size distribution method thereof.

Background

The memory of the RFID tag chip is composed of the following parts: the reserved area (00) is used for accessing the password; an Electronic Product Code (EPC) area (01) is used to hold an electronic product code value for identifying a tag object; a Tag Identification (TID) field (10) for accessing a tag identification value; the user area (11) is used for accessing user data, as shown in fig. 1.

The size of each zone is generally fixed when the chip leaves the factory, and the sizes of the reserved zone (00) and the Tag Identification (TID) zone (10) are basically unchangeable according to the RFID protocol requirements, and only the EPC zone (01) and the user zone (11) can be reallocated.

Disclosure of Invention

The invention aims to provide an RFID tag chip and an EPC area and user area size distribution method thereof aiming at the defects in the prior art, and the purpose of configuring the sizes of the EPC area and the user area can be quickly achieved by using a standard write command.

Therefore, the invention adopts the following technical scheme.

An RFID tag chip comprising a memory, the memory comprising a user area and an EPC area, the EPC area comprising a PC word, the PC word comprising a field L and a UMI bit, a value of the field L indicating a size of the EPC area, a value of the field L being modifiable by a standard write command, the UMI bit being used to mark whether the user area is present.

Preferably, modifying the value of the field L can reallocate the logical space of the user area and the EPC area.

Preferably, after the logical space is reallocated, the user area and the EPC area are continuous logical intervals, respectively.

Preferably, the upper limit of the size of the EPC area is the sum of the sizes of the user area and the EPC area allocated by factory.

Preferably, the PC word is the second word of the EPC area, and the size of the field L is 5 bits.

Based on the same inventive concept, the invention also provides an EPC area size distribution method of the RFID tag chip, which comprises the following steps: modifying the value of the field L by a standard write command according to requirements; according to the value of the L field, the chip automatically configures the sizes of the EPC area and the user area.

Preferably, when the size of the configured EPC area reaches an upper limit, the chip automatically sets the UMI bit to 0, otherwise, to 1.

The technical scheme has the advantages that:

1. the value of the field L can be modified through a standard write command, so that the chip automatically configures the sizes of an EPC area and a user area;

2. the logical space of the user area and the EPC area can be flexibly distributed;

3. the chip automatically modifies the value of the UMI bit after the user area is exhausted.

Drawings

FIG. 1 is a schematic diagram of the structure of an RFID tag chip memory;

FIG. 2 is a schematic diagram of the components of an RFID system;

FIG. 3 is a schematic diagram of the components of an RFID tag chip;

FIG. 4 is a schematic diagram of the EPC region;

FIG. 5 is a schematic diagram of a PC word structure;

fig. 6 is a schematic structural diagram of an EPC area and a user area;

FIG. 7 is a flowchart illustrating the operation of a current method for resizing an EPC region;

fig. 8 is an operation flowchart of a method of resizing an EPC region of the present invention.

Detailed Description

In order that the objects, features and advantages of the invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings, which are illustrated in detail in order to provide a thorough understanding of the invention, but which may be carried out in other ways than those described. Accordingly, the invention is not limited by the specific implementations disclosed below.

The RFID system is composed of a reading head, an antenna and an RFID label chip, and is shown in the attached figure 1. The RFID tag chip is composed of: a transceiver for receiving a signal coupled from the antenna, deriving energy and information therefrom, and reflecting an output signal from the tag; a digital baseband processor for processing baseband signals and operating on memory; a memory for storing a chip ID and user information; as shown in fig. 2.

Different users have different requirements on the EPC area and the size of the user area. For example, some users may require a large EPC area with little or no user area requirements, while other users may require a generally sized EPC area but require a large user area, which creates a conflict.

The current methods for dealing with this conflict are mainly the following three types: one is to provide multiple chip versions, and the EPC area and the user area of each version are different in size; in the other method, a programmable bit is set in a memory, and the bit is written to adjust the different distribution modes of the EPC area and the user area of the chip; yet another is a mode switch chip EPC area and user area size allocation scheme with custom commands.

The invention discloses a method for configuring EPC area and user area size, which can quickly achieve the purpose of configuring EPC area and user area size by standard write command without using multiple chip versions, using extra space of memory in the chip to store control bits, additionally increasing the operation of writing control bits, and customizing command, namely non-standard command.

Example one

An embodiment of the present invention provides an RFID tag chip, including a memory, the memory including a user area and an EPC area, the EPC area including a PC word, the PC word including a field L and a UMI bit, a value of the field L indicating a size of the EPC area, a value of the field L being modifiable by a standard write command, and the UMI bit being used to mark whether the user area exists.

The standard write commands described in embodiments of the present invention, i.e., the specified write commands according to the RFID standard, are relative to the size of the EPC region and the user region that other chips may utilize custom commands to configure.

The physical structure of the EPC region is shown in fig. 4 and is formed by arranging words (16 bits), wherein the second word PC has stored therein a field L for specifying the length of the EPC. The structure of the PC word is shown in fig. 5, and the value of field L has 5 bits indicating the number of words of the EPC field following field L. E.g., field L is b00110, then the following EPCs 0 through 5 are valid, i.e., configured to the size of the EPC zone. But the size of the EPC region of current chips is limited to the maximum value of factory allocation. The UMI bit is a read-only bit for the user and is an indication of whether the chip has a user area. The UMI bit is 1 if a chip has a user area, and 0 otherwise.

The invention proposes an inventive concept: the chip automatically configures the size of the EPC area and the user area by modifying the value of the L field by the pattern of a standard write command.

The upper limit of the EPC area size is the sum of the EPC area and the user area size of the chip, that is, the value of the extended field L, and all of the logical spaces allocated to the user area by factory can be allocated in the range of the EPC area. On the contrary, if the value of the L field is set to 0, the logical space of the EPC area can be entirely divided into the range of the user area. The logical spaces of the user zone and the EPC zone can be flexibly allocated.

As shown in fig. 6, the logical address of the start of the user area is the next address of the end address of the EPC area. The hardware automatically adjusts the starting address of the user area according to the value of the L field, as shown by the dotted arrow in the figure, thereby adjusting the size of the EPC area and the user area.

The logical address of the user area may be after or before the EPC area. After the logical space is reallocated, the EPC area and the user area are respectively continuous logical intervals, i.e., a segment of continuous logical addresses.

Example two

The embodiment of the invention provides a method for allocating the sizes of an EPC area and a user area of an RFID tag chip in the first embodiment.

The basic operation of the conventional method for adjusting the size of the EPC area by a chip is shown in fig. 7, and includes the following steps.

The reading head sends a power-on signal to control the chip to be powered on.

And obtaining the EPC code by the hardware through inventory, and obtaining the factory default length of the chip, including the size value of the factory-allocated EPC area.

According to the user requirement, the EPC region is adjusted in one of the following two current ways: 1. sending a self-defining command; 2. the size of the EPC region is adjusted by writing a special register, i.e. modifying the value of a programmable bit in memory, modifying the value of field L.

The embodiment of the invention is shown in the attached figure 8, and is different from the method in that: the value of field L need only be modified by sending a standard command.

The embodiment of the invention is simple and practical, does not need additional control bits, correspondingly does not need to inform the user of the information of the additional control bits, can realize the redistribution of the EPC area and the size of the user area without using a mode of a custom command, and meets the requirements of most users.

The embodiment of the invention also comprises the following steps: and modifying the UMI indicating bit according to whether the user area is exhausted, wherein under the condition that all the user areas distributed from factories are distributed in the range of the EPC area, the UMI bit is automatically set to be 0 by hardware, and otherwise, the UMI bit is set to be 1 so as to correctly indicate whether the user area of the chip exists.

While the above description shows and describes the preferred embodiments of the present invention, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An RFID tag chip comprising a memory, the memory comprising a user area and an EPC area, the EPC area comprising a PC word, the PC word comprising a field L and a UMI bit, a value of the field L indicating a size of the EPC area, a value of the field L being modifiable by a standard write command, a modification of the value of the field L enabling a reallocation of a logical space of the user area and the EPC area, the UMI bit being used to mark whether the user area is present.

2. The RFID tag chip of claim 1, wherein the user zone and the EPC zone are contiguous logical intervals, respectively, after logical space is reallocated.

3. The RFID tag chip of claim 1, wherein the EPC area has an upper limit on a size of a sum of the user area and the EPC area that are factory allocated.

4. The RFID tag chip of claim 1, wherein the PC word is the second word of the EPC region and the field L has a size of 5 bits.

5. A method of allocating the EPC zone and the user zone size of an RFID tag chip according to any one of claims 1 to 4, comprising the steps of:

modifying the value of the field L by a standard write command according to requirements;

according to the value of the field L, the chip automatically configures the sizes of the EPC area and the user area.

6. The method of claim 5, wherein the chip automatically sets the UMI bit to 0 when the size of the configured EPC zone reaches an upper limit, and to 1 otherwise.