CN112099563A - Low-power-consumption CMOS current source circuit for NFC chip - Google Patents
Low-power-consumption CMOS current source circuit for NFC chip Download PDFInfo
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Abstract
The application relates to a low-power consumption CMOS current source circuit for NFC chip, includes: first NMOS pipe, second NMOS pipe, first resistance, second resistance, because the components and parts that are used for the low-power consumption CMOS current source circuit of NFC chip in this application to include are few, and its whole area and consumption are all very little. The grid end of the first NMOS tube is connected with the upper circuit current, and the source end of the first NMOS tube is grounded; the grid end of the second NMOS tube is connected with the current of the upper circuit, and the source end of the second NMOS tube is connected with the first end of the first resistor; the second end of the first resistor is connected with the first end of the second resistor; the second end of the second resistor is grounded. When the currents connected to the first NMOS tube and the second NMOS tube are equal, the temperature coefficient of the electron mobility of the NMOS tube is negative, and the current in the circuit can be kept unchanged along with the temperature only by making the temperature coefficients of the first resistor and the second resistor positive.
Description
Technical Field
The application relates to the technical field of low-power-consumption CMOS current source circuits, in particular to a low-power-consumption CMOS current source circuit for an NFC chip.
Background
NFC is a near field communication technology developed in the radio frequency communication technology, and can provide secure, fast, and automatic communication for various devices. The NFC chip requires an amplifier to receive the radio frequency signal and a phase locked loop to generate a clock to process the data. In the prior art, the NFC chip is heated up during operation, the current change inside the NFC chip is caused by the temperature change, and both the amplifier and the phase-locked loop of the NFC chip need a current that does not change with the temperature, that is, the reference current is required to be unrelated to the power supply voltage and the temperature, and the influence of the manufacturing process is small.
Disclosure of Invention
To overcome, at least to some extent, the problems in the related art, the present application provides a low power consumption CMOS current source circuit for an NFC chip.
The scheme of the application is as follows:
a low power CMOS current source circuit for an NFC chip, comprising:
the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a first resistor and a second resistor; wherein the temperature coefficients of the first and second resistors are positive;
the grid end of the first NMOS tube is connected with the current of an upper circuit, and the source end of the first NMOS tube is grounded;
the grid end of the second NMOS tube is connected with the current of an upper circuit, and the source end of the second NMOS tube is connected with the first end of the first resistor;
the second end of the first resistor is connected with the first end of the second resistor;
and the second end of the second resistor is grounded.
Preferably, in an implementation manner of the present application, if an upper circuit current accessed to a gate terminal of the first NMOS transistor is equal to an upper circuit current accessed to a gate terminal of the second NMOS transistor, an expression of a current value flowing through the low-power consumption CMOS current source circuit is as follows:
wherein I is the value of current flowing in the low-power CMOS current source circuit,
the electron mobility of the first NMOS transistor and the second NMOS transistor,
w1 is the width of the first NMOS tube, L1 is the length of the first NMOS tube,
the voltage difference of the grid electrode and the source electrode of the first NMOS tube,
w2 is the width of the second NMOS transistor, L2 is the length of the second NMOS transistor,
and R1 is the voltage difference between the grid electrode and the source electrode of the second NMOS transistor, R2 is the resistance value of the first resistor, and R2 is the resistance value of the second resistor.
Preferably, in an implementable manner of the present application, the second NMOS transistor
Is the first NMOS transistor
When the current value is m times, the expression of the current value flowing through the low-power consumption CMOS current source circuit is as follows:
wherein I is the value of current flowing in the low-power CMOS current source circuit, and m is that of the second NMOS transistor
And the first NMOS transistor
The multiplying factor of (2).
Preferably, in an achievable mode of the present application, the temperature coefficient of electron mobility of the first NMOS transistor and the second NMOS transistor is negative.
Preferably, in an implementable manner of the present application, the host circuit includes:
the power supply comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and a power supply.
Preferably, in an implementable manner herein,
the source ends of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected with a power supply;
the grid ends of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected with the drain end of the second PMOS tube;
the drain end of the seventh PMOS tube is connected with the source end of the first PMOS tube;
the drain end of the sixth PMOS tube is connected with the source end of the second PMOS tube;
the drain end of the fifth PMOS tube is connected with the source end of the fourth PMOS tube;
the grid ends of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with the drain end of the third PMOS tube;
the drain end of the first PMOS tube is connected with the drain end of the seventh NMOS tube;
the drain end of the second PMOS tube is connected with the drain end of the sixth NMOS tube;
the drain end of the third PMOS tube is connected with the drain end of the fifth NMOS tube;
the drain end of the fourth PMOS tube is connected with the drain end of the fourth NMOS tube;
the grid ends of the seventh NMOS tube, the sixth NMOS tube, the fifth NMOS tube and the fourth NMOS tube are all connected with the drain end of the fourth NMOS tube;
the source end of the seventh NMOS tube is connected with the drain end of the first NMOS tube;
the source end of the sixth NMOS tube is connected with the drain end of the second NMOS tube;
the source end of the fifth NMOS tube is connected with the drain end of the third NMOS tube;
the grid ends of the first NMOS tube, the second NMOS tube and the third NMOS tube are all connected with the drain end of the seventh NMOS tube;
the source ends of the third NMOS tube and the fourth NMOS tube are grounded.
Preferably, in an implementable manner of the present application, the gate terminal and the drain terminal of the third PMOS transistor are shorted together to provide a gate voltage for the first PMOS transistor, the second PMOS transistor, and the fourth PMOS transistor.
Preferably, in an implementable manner of the present application, the gate terminal and the drain terminal of the fourth NMOS transistor are shorted together to provide a gate voltage for the fifth NMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor.
Preferably, in an implementable manner of the present application, the sixth PMOS transistor and the seventh PMOS transistor are of the same size.
Preferably, in an implementable manner of the present application, the first PMOS transistor and the second PMOS transistor are of the same size.
The technical scheme provided by the application can comprise the following beneficial effects: the low-power consumption CMOS current source circuit for the NFC chip in the application only comprises: the first NMOS tube, the second NMOS tube, the first resistor, the second resistor, the whole area and the power consumption are small. The grid end of the first NMOS tube is connected with the upper circuit current, and the source end of the first NMOS tube is grounded; the grid end of the second NMOS tube is connected with the current of the upper circuit, and the source end of the second NMOS tube is connected with the first end of the first resistor; the second end of the first resistor is connected with the first end of the second resistor; the second end of the second resistor is grounded. When the currents connected to the first NMOS tube and the second NMOS tube are equal, the temperature coefficient of the electron mobility of the NMOS tube is negative, and the current in the circuit can be kept unchanged along with the temperature only by making the temperature coefficients of the first resistor and the second resistor positive.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a circuit diagram of a low power consumption CMOS current source for an NFC chip according to an embodiment of the present application;
fig. 2 is a circuit diagram of a low power consumption CMOS current source for an NFC chip according to another embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
Example one
A low power consumption CMOS current source circuit for an NFC chip, referring to fig. 1, comprising:
the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a first resistor and a second resistor; wherein the temperature coefficients of the first resistor and the second resistor are positive;
the grid end of the first NMOS tube is connected with the current of the upper circuit, and the source end of the first NMOS tube is grounded;
the grid end of the second NMOS tube is connected with the current of the upper circuit, and the source end of the second NMOS tube is connected with the first end of the first resistor;
the second end of the first resistor is connected with the first end of the second resistor;
the second end of the second resistor is grounded.
In fig. 1, N1 and N2 respectively represent a first NMOS transistor and a second NMOS transistor, R1 and R2 respectively represent a first resistor and a second resistor, and I1 and I2 respectively represent currents in two branches of the first NMOS transistor and the second NMOS transistor.
When the upper circuit current accessed to the grid end of the first NMOS tube is equal to the upper circuit current accessed to the grid end of the second NMOS tube, the expression of the current value flowing through the low-power-consumption CMOS current source circuit is as follows:
wherein I is the current value flowing in the low-power CMOS current source circuit,
the electron mobility of the first NMOS transistor and the second NMOS transistor,
w1 is the width of the first NMOS transistor, L1 is the length of the first NMOS transistor,
is the voltage difference between the gate and the source of the first NMOS transistor,
w2 is the width of the second NMOS transistor, L2 is the length of the second NMOS transistor,
the voltage difference between the gate and the source of the second NMOS transistor, R1 is the resistance of the first resistor, and R2 is the resistance of the second resistor.
If the second NMOS transistor
Is a first NMOS transistor
M times, the expression of the current value flowing in the low-power consumption CMOS current source circuit is as follows:
wherein I is the current value flowing in the low-power CMOS current source circuit, and m is that of the second NMOS transistor
And a first NMOS transistor
The multiplying factor of (2).
In the embodiment, the electron mobility of the first NMOS transistor and the second NMOS transistor
The temperature coefficient is negative. According to
The temperature coefficient of the resistor is suitable for the first resistor and the second resistor, and the current is guaranteed not to change along with the temperature.
It can be seen from equation (4) that the current hardly varies with the supply voltage.
For example, the following steps are carried out:
is-1.5, a first resistance with a temperature coefficient of 0.25 and a second resistance with a temperature coefficient of 0.5 are selected. The temperature coefficient of the sum of the resistances is 0.75, and since the resistances are squared, the temperature coefficient of the current is 0 and does not vary with temperature.
Preferably, the first resistor and the second resistor may not have the same resistance type.
Example two
In some embodiments, the low power CMOS current source circuit for an NFC chip, referring to fig. 2, the upper circuit includes:
the power supply comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and a power supply.
In fig. 2, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor are denoted by N3, N4, N5, N6, and N7, respectively;
p1, P2, P3, P4, P5, P6 and P7 respectively represent a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor and a seventh PMOS transistor;
the power supply is denoted by VDD.
In this embodiment, the upper circuit is implemented on the basis of the low power consumption CMOS current source circuit in the first embodiment.
Specific connection relationships refer to fig. 2:
the source ends of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected with a power supply;
grid ends of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are connected with a drain end of the second PMOS tube;
the drain end of the seventh PMOS tube is connected with the source end of the first PMOS tube;
the drain end of the sixth PMOS tube is connected with the source end of the second PMOS tube;
the drain end of the fifth PMOS tube is connected with the source end of the fourth PMOS tube;
the grid ends of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with the drain end of the third PMOS tube;
the drain end of the first PMOS tube is connected with the drain end of the seventh NMOS tube;
the drain end of the second PMOS tube is connected with the drain end of the sixth NMOS tube;
the drain end of the third PMOS tube is connected with the drain end of the fifth NMOS tube;
the drain end of the fourth PMOS tube is connected with the drain end of the fourth NMOS tube;
the grid ends of the seventh NMOS tube, the sixth NMOS tube, the fifth NMOS tube and the fourth NMOS tube are all connected with the drain end of the fourth NMOS tube;
the source end of the seventh NMOS tube is connected with the drain end of the first NMOS tube;
the source end of the sixth NMOS tube is connected with the drain end of the second NMOS tube;
the source end of the fifth NMOS tube is connected with the drain end of the third NMOS tube;
the grid ends of the first NMOS tube, the second NMOS tube and the third NMOS tube are all connected with the drain end of the seventh NMOS tube;
the source ends of the third NMOS tube and the fourth NMOS tube are grounded.
The grid end and the drain end of the third PMOS tube are in short circuit connection together to provide grid voltage for the first PMOS tube, the second PMOS tube and the fourth PMOS tube;
and the grid end and the drain end of the fourth NMOS tube are connected together in a short circuit mode to provide grid voltage for the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube.
The drain terminals of the NMOS transistor and the PMOS transistor are shown as the upper section interfaces of the NMOS transistor and the PMOS transistor in fig. 1-2, the gate terminal is shown as the middle section interface of the NMOS transistor and the PMOS transistor in fig. 1-2, and the source terminal is shown as the lower section interface of the NMOS transistor and the PMOS transistor in fig. 1-2.
In order to ensure that the two paths of current of the first NMOS tube and the second NMOS tube are the same, the sizes of the sixth PMOS tube and the seventh PMOS tube are the same, and the sizes of the first PMOS tube and the second PMOS tube are the same.
In this embodiment, only four currents are needed to realize the current that does not change with temperature, and the overall area and power consumption of the four currents are very small, which meets the requirements of the NFC chip.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (10)
1. A low power CMOS current source circuit for an NFC chip, comprising:
the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a first resistor and a second resistor; wherein the temperature coefficients of the first and second resistors are positive;
the grid end of the first NMOS tube is connected with the current of an upper circuit, and the source end of the first NMOS tube is grounded;
the grid end of the second NMOS tube is connected with the current of an upper circuit, and the source end of the second NMOS tube is connected with the first end of the first resistor;
the second end of the first resistor is connected with the first end of the second resistor;
and the second end of the second resistor is grounded.
2. The CMOS current source circuit for the NFC chip of claim 1, wherein an upper circuit current accessed to the gate terminal of the first NMOS transistor is equal to an upper circuit current accessed to the gate terminal of the second NMOS transistor, and a current value flowing through the CMOS current source circuit for the NFC chip is expressed as:
wherein I is the value of current flowing in the low-power CMOS current source circuit,
the electron mobility of the first NMOS transistor and the second NMOS transistor,
w1 is the width of the first NMOS tube, L1 is the length of the first NMOS tube,
the voltage difference of the grid electrode and the source electrode of the first NMOS tube,
w2 is the width of the second NMOS transistor, L2 is the length of the second NMOS transistor,
and R1 is the voltage difference between the grid electrode and the source electrode of the second NMOS transistor, R2 is the resistance value of the first resistor, and R2 is the resistance value of the second resistor.
3. The CMOS current source circuit for NFC chip of claim 2, wherein the second NMOS transistor is connected to the first NMOS transistor
Is the first NMOS transistor
When the current value is m times, the expression of the current value flowing through the low-power consumption CMOS current source circuit is as follows:
wherein I is the value of current flowing in the low-power CMOS current source circuit, and m is that of the second NMOS transistor
And the first NMOS transistor
The multiplying factor of (2).
4. The CMOS current source circuit for NFC chip of claim 3, wherein the temperature coefficient of electron mobility of the first NMOS transistor and the second NMOS transistor is negative.
5. The low-power consumption CMOS current source circuit for NFC chip of claim 4, wherein the host circuit comprises:
the power supply comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and a power supply.
6. The low-power CMOS current source circuit for NFC chip of claim 5,
the source ends of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected with a power supply;
the grid ends of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected with the drain end of the second PMOS tube;
the drain end of the seventh PMOS tube is connected with the source end of the first PMOS tube;
the drain end of the sixth PMOS tube is connected with the source end of the second PMOS tube;
the drain end of the fifth PMOS tube is connected with the source end of the fourth PMOS tube;
the grid ends of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with the drain end of the third PMOS tube;
the drain end of the first PMOS tube is connected with the drain end of the seventh NMOS tube;
the drain end of the second PMOS tube is connected with the drain end of the sixth NMOS tube;
the drain end of the third PMOS tube is connected with the drain end of the fifth NMOS tube;
the drain end of the fourth PMOS tube is connected with the drain end of the fourth NMOS tube;
the grid ends of the seventh NMOS tube, the sixth NMOS tube, the fifth NMOS tube and the fourth NMOS tube are all connected with the drain end of the fourth NMOS tube;
the source end of the seventh NMOS tube is connected with the drain end of the first NMOS tube;
the source end of the sixth NMOS tube is connected with the drain end of the second NMOS tube;
the source end of the fifth NMOS tube is connected with the drain end of the third NMOS tube;
the grid ends of the first NMOS tube, the second NMOS tube and the third NMOS tube are all connected with the drain end of the seventh NMOS tube;
the source ends of the third NMOS tube and the fourth NMOS tube are grounded.
7. The CMOS current source circuit for NFC chip of claim 6, wherein the gate terminal and the drain terminal of the third PMOS transistor are shorted together to provide gate voltage for the first, second and fourth PMOS transistors.
8. The CMOS current source circuit for NFC chip of claim 7, wherein the gate terminal and the drain terminal of the fourth NMOS transistor are shorted together to provide gate voltage for the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor.
9. The CMOS current source circuit for an NFC chip of claim 8, wherein the sixth PMOS transistor and the seventh PMOS transistor are of uniform size.
10. The low-power consumption CMOS current source circuit for an NFC chip according to claim 9, wherein the first PMOS transistor and the second PMOS transistor are of uniform size.
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| Title |
|---|
| 李健 等: "基于自偏置结构的参考电流源电路", 《电子与封装》 * |
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| Publication number | Publication date |
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| CN112099563B (en) | 2021-04-09 |
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Denomination of invention: Low power CMOS current source circuit for NFC chip Effective date of registration: 20210924 Granted publication date: 20210409 Pledgee: Bank of Chengdu science and technology branch of Limited by Share Ltd. Pledgor: SICHUAN KEDAO XINGUO INTELLIGENT TECHNOLOGY Co.,Ltd. Registration number: Y2021510000231 |